JPS6374697U - - Google Patents
Info
- Publication number
- JPS6374697U JPS6374697U JP16788486U JP16788486U JPS6374697U JP S6374697 U JPS6374697 U JP S6374697U JP 16788486 U JP16788486 U JP 16788486U JP 16788486 U JP16788486 U JP 16788486U JP S6374697 U JPS6374697 U JP S6374697U
- Authority
- JP
- Japan
- Prior art keywords
- bar graph
- graph display
- input signal
- reference signal
- display circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 230000007246 mechanism Effects 0.000 description 1
Landscapes
- Indicating Measured Values (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
第１図は本考案によるバーグラフ表示機構の１
実施例を示すブロツク図、第２図は本実施例にお
ける信号の動作タイミングを示すタイミング図、
第３図は基準波形発生回路の発生する基準波形を
示す図、第４図、第５図は基準波形信号の他の実
施例を示す図、第６図は従来例を示す図である。
１……基準波形発生回路、２……加算器、３…
…バーグラフ表示回路。
Figure 1 shows one of the bar graph display mechanisms according to the present invention.
A block diagram showing the embodiment, FIG. 2 is a timing diagram showing the signal operation timing in this embodiment,
FIG. 3 is a diagram showing a reference waveform generated by the reference waveform generating circuit, FIGS. 4 and 5 are diagrams showing other embodiments of the reference waveform signal, and FIG. 6 is a diagram showing a conventional example. 1...Reference waveform generation circuit, 2...Adder, 3...
...Bar graph display circuit.
Claims (1)
シユ・ホールド電圧と比較し、その比較結果に基
づいて入力信号レベルをバーグラフとして表示す
るバーグラフ表示回路３と、上記設定されたスレ
ツシユ・ホールド電圧間隔と等しいかそれよりも
小さな振幅を持つ交流基準信号発生回路１と、該
交流基準信号と入力信号とを加算または減算する
加算器２とを設け、該加算器２の出力信号を前記
バーグラフ表示回路の入力信号として供給するよ
うにしたことを特徴とするバーグラフ表示装置。 (2) 前記交流基準信号が鋸歯状波である実用新
案登録請求の範囲第１項記載のバーグラフ表示装
置。[Claims for Utility Model Registration] (1) A bar graph display circuit 3 that compares an input signal with threshold hold voltages set at approximately equal intervals and displays the input signal level as a bar graph based on the comparison result. , an AC reference signal generating circuit 1 having an amplitude equal to or smaller than the threshold voltage interval set above, and an adder 2 for adding or subtracting the AC reference signal and the input signal, 1. A bar graph display device, characterized in that the output signal of the bar graph display circuit 2 is supplied as an input signal to the bar graph display circuit. (2) The bar graph display device according to claim 1, wherein the AC reference signal is a sawtooth wave.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16788486U JPS6374697U (en) | 1986-10-31 | 1986-10-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16788486U JPS6374697U (en) | 1986-10-31 | 1986-10-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6374697U true JPS6374697U (en) | 1988-05-18 |
Family
ID=31100237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16788486U Pending JPS6374697U (en) | 1986-10-31 | 1986-10-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6374697U (en) |
-
1986
- 1986-10-31 JP JP16788486U patent/JPS6374697U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS59182747U (en) | interface circuit | |
| KR880009484A (en) | Method and circuit for generating triangular wave voltage | |
| JPS6374697U (en) | ||
| JPS63147082U (en) | ||
| JPS583780U (en) | Synchronous pulse signal generation circuit | |
| JPS5664565A (en) | Vertical deflecting circuit | |
| JPH0353035U (en) | ||
| SU734636A1 (en) | Method of pulse stabilizing of dc voltage of two-cycle stabilizer | |
| JPS63126882U (en) | ||
| JPS5912186U (en) | CRT display device | |
| KR930006135Y1 (en) | Circuit for generating electric pulses | |
| JPH02130124U (en) | ||
| JPH0369970U (en) | ||
| JPS6286738U (en) | ||
| JPS6157869U (en) | ||
| JPS6138570U (en) | Analog voltage measuring device | |
| JPS6381531U (en) | ||
| JPH02102522U (en) | ||
| JPS60136545U (en) | Gate circuit of gate turn-off thyristor | |
| JPH029925U (en) | ||
| JPS61189327U (en) | ||
| JPS5555670A (en) | Input circuit for horizontal synchronizing signal | |
| JPS59188406U (en) | dental checker | |
| JPH0229088U (en) | ||
| JPH0262049B2 (en) |