JPS6373639A - Trimming wiring in semiconductor device - Google Patents
Trimming wiring in semiconductor deviceInfo
- Publication number
- JPS6373639A JPS6373639A JP21714686A JP21714686A JPS6373639A JP S6373639 A JPS6373639 A JP S6373639A JP 21714686 A JP21714686 A JP 21714686A JP 21714686 A JP21714686 A JP 21714686A JP S6373639 A JPS6373639 A JP S6373639A
- Authority
- JP
- Japan
- Prior art keywords
- interconnection
- wiring
- trimming
- step difference
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000009966 trimming Methods 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 238000007664 blowing Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 19
- 239000000523 sample Substances 0.000 abstract description 10
- 238000001259 photo etching Methods 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 238000007689 inspection Methods 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 241000282412 Homo Species 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
- 238000010809 targeting technique Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置における配線トリミング技術に関し
、主として並列拡散抵抗に接続されたAノ(アルミニウ
ム)配線層を選択的にトリミングする場合のAA溶断技
術を対象とする。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to wiring trimming technology in semiconductor devices, and mainly relates to AA fusing when selectively trimming an A (aluminum) wiring layer connected to a parallel diffused resistor. Targeting technology.
IC(半導体集積回路装置)の製造において。 In the manufacture of ICs (semiconductor integrated circuit devices).
第7図に示すように半導体基体表面に異なる抵抗値をも
つ複数の拡散抵抗R,,R,,R,・・・・・・を形成
し、このうち不要とする抵抗(Rt = R1・・・)
よりの引出しへ2配線をトリミング(部分的切除)する
ことにより必要とする抵抗(R1)のみを残すトリミン
グ技術が知られている。As shown in FIG. 7, a plurality of diffused resistors R, , R, , R, .・)
A trimming technique is known in which only the necessary resistor (R1) is left by trimming (partially cutting) two wires to a drawer.
このトリミング手段には、一般忙グローブ検査で各拡散
抵抗の抵抗値を測定しながら、不要とする抵抗の引出し
配線にプローブ針を介して過を流を流す方法があり、こ
の他にレーザを用いて誘電体上の銀合金抵抗等をトリミ
ングする方法(株式%式%
〜124誘電体上の抵抗レーザトリミング)等がある。This trimming method includes a method in which the resistance value of each diffused resistor is measured during a general glove inspection, and a current is passed through a probe needle to the lead wire of the unnecessary resistor, and another method is to use a laser. There is a method of trimming a silver alloy resistor etc. on a dielectric material (resistance laser trimming on a dielectric material).
このうち、レーザな用いるトリミング方法は、大がかり
なレーザ装置が必要であり、人4配線のトリミングに適
合しないから対象外とし、ここでは主としてプローブ検
査を利用するものに限ることとする。Among these, the trimming method using a laser is excluded because it requires a large-scale laser device and is not suitable for trimming human 4 wiring, and here we will limit it to methods that mainly utilize probe inspection.
通常は第8図に示すように、人!配線2に接続される外
部端子(ポンディングパッド)3にプローブ針4を接触
させ、Al配線2の他端を接地した状態で過電流を流し
、AJl配線一部K、形成した細幅部5で溶断するよう
になっている。Usually, as shown in Figure 8, people! A probe needle 4 is brought into contact with an external terminal (ponding pad) 3 connected to the wiring 2, and an overcurrent is applied with the other end of the Al wiring 2 grounded. It is designed to melt.
上記トリミング法ではA1配線の一部であるパッドに接
触させるプローブ針先端の劣化が速いこと、人!配線が
切れにくいこと等の問題がある。In the above trimming method, the tip of the probe needle that comes into contact with the pad that is part of the A1 wiring deteriorates quickly. There are problems such as the wiring being difficult to cut.
また人!配線を切断できるよ5に十分な大電流を流すと
、第9図に示すように溶断時にA4が飛散して表面保護
用絶縁膜6が破壊されたり、汚染によって他のAJ3配
ねと短絡したりするため、ICの信頼度が大幅に低下す
るおそれがあった。Another person! If a large enough current is applied to the wiring 5 to cut the wiring, as shown in Figure 9, the A4 will scatter when it melts, destroying the surface protection insulating film 6, or causing short circuits with other AJ3 wiring due to contamination. Because of this, there was a risk that the reliability of the IC would drop significantly.
本発明者等は種々検討した結果、上記した問題は人!切
断の際に過大なエネルギを要するために生じることが判
り、これが解決を図った。As a result of various studies, the inventors of the present invention found that the above-mentioned problem can be solved by humans! It was discovered that this problem occurred because too much energy was required during cutting, and an attempt was made to solve this problem.
したがって本発明の目的とするところは、小さなエネル
ギを用いてA!l配線溶断する技術を提供することにあ
る。Therefore, it is an object of the present invention to obtain A! The purpose of this invention is to provide a technology for melting wiring.
本発明の前記ならびにそのほかの目的と新規な特徴は本
明細書の記述及び添付図面からあきらかになろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、牛導体基体上に形成されたl配線に電流を流
して上記Al配線を特定部位で溶断することによりトリ
ミングするにあたって、上記特定部位のA!配り直下に
段差部を設けこの段差部による人!配線膜厚の差を利用
するものである。That is, when trimming the Al wiring by flowing current through the l wiring formed on the conductor substrate and melting the Al wiring at a specific location, the A! of the specific location is trimmed. A step is provided directly below the distribution, and people can use this step! This utilizes the difference in wiring film thickness.
上記した手段によれば1段差部上でA!l配線膜厚が薄
くなり人!断面積が小さくなる結果、小さいエネルギで
溶断が可能となり、トリミング後も半導体装置の信頼度
を保持でき、前記目的を達成できる。According to the above-mentioned means, A! l Wiring film thickness becomes thinner! As a result of the cross-sectional area becoming smaller, it becomes possible to fuse the semiconductor device with less energy, and the reliability of the semiconductor device can be maintained even after trimming, thereby achieving the above object.
第1図乃至第5図は本発明の一実施例を人!配綜形成プ
ロセスの工程断面図及び平面図であられしたものである
。Figures 1 to 5 show an embodiment of the present invention! FIG. 3 is a process sectional view and a plan view of the heddle forming process.
以下工程順に沿って説明する。The steps will be explained below in order.
(1) 半導体(St)基体1上忙熱酸化又はCvD
(気相化学堆積)法によりSin、膜7を形成し、ホト
エツチング技術により段差部を設ける。このうち8は最
も深い段差をもつ段差部とする。これら段差のためのホ
トエツチングは半導体基体への選択拡散(ペース、エミ
ッタ拡散)工程に伴うものであってよい(第1図)。(1) Active thermal oxidation or CvD on semiconductor (St) substrate 1
A film 7 of Sin is formed by a (vapor phase chemical deposition) method, and a stepped portion is provided by a photoetching technique. Of these, 8 are the step portions with the deepest steps. Photoetching for these steps may be accompanied by a selective diffusion (paste, emitter diffusion) process into the semiconductor body (FIG. 1).
(2)人1配線形成のために全面にA2を蒸着し、ホト
エツチング罠より特定のパターンをもつ、1配腺2とす
る(第2図)。(2) To form wiring for person 1, A2 is deposited on the entire surface and formed into wiring 2 with a specific pattern by photo-etching (Figure 2).
+31g3図はA1配線の一つのパターンの例を示す。+31g3 Figure shows an example of one pattern of A1 wiring.
3はポンディングパッド、2はAJl配線ある。3 is a bonding pad, and 2 is an AJl wiring.
たとえばこの人!配線の他端は図示されない拡散抵抗に
オーミックコンタクトするとともに接地電位に接続され
る。この人1配蔵は前記Sin@膜70段差8上を横切
って形成されるものとする。For example, this person! The other end of the wiring is in ohmic contact with a diffused resistor (not shown) and is connected to a ground potential. It is assumed that this layer 1 is formed across the step 8 of the Sin@ film 70.
第4図は人!配線のパターンの他の例を示すものである
。この例では人!配線2が段差8上を横切る部位にm幅
部9が形成されている。Figure 4 is people! This figure shows another example of a wiring pattern. In this example, people! An m-width portion 9 is formed at a portion where the wiring 2 crosses the step 8.
鬼41 第5図に示すように、バッド3にプローブ針
4を接触させた状態で人!配線2に*流を流子と、段差
部に過大電流がながれてここ10が溶断しトリミングが
なされる。Oni 41 As shown in Figure 5, a person is in contact with the probe needle 4 on the pad 3! When a current flows through the wiring 2, an excessive current flows through the stepped portion, and this portion 10 is fused and trimmed.
A4膜は蒸着あるいはスパッタのいずれの手段で形成し
ても段差部においてAAの膜厚はう丁くなる。この人1
膜厚は段差が大きいほど5丁く。Regardless of whether the A4 film is formed by vapor deposition or sputtering, the thickness of the AA film at the step portion will be small. This person 1
The larger the difference in level, the greater the film thickness.
その部分でのAl配線断面積は小さくそこへ電流集中し
やすくなる。このため、A1溶断は低エネルギで可能と
なり、したがって人!飛散が少なく、保護膜の破壊や汚
染もなくなり、信頼度の低下、プローブ針の劣化等の問
題がなくなる。その結果トリミングが確実、容易となり
、高付加値のIC。The cross-sectional area of the Al wiring at that portion is small and current tends to concentrate there. For this reason, A1 fusing is possible with low energy and therefore less human! There is little scattering, there is no destruction or contamination of the protective film, and there are no problems such as reduced reliability or deterioration of the probe needle. As a result, trimming is reliable and easy, resulting in an IC with high added value.
LSIが実現できる。LSI can be realized.
Aノ瞑の直下に段差を設けるとともに、人ぷ配iパター
ンにm幅部を形成することにより、A2瞑厚と配線幅と
の相乗効果で人2配球断面積を−そ5小さいものとし、
わずかのエネルギでトリミングが可能である。By providing a step directly below the A-shaped ball and forming an m-width part in the I-pattern, the synergistic effect of the A2 thickness and the wiring width reduces the cross-sectional area of the A-2 ball by -5. ,
Trimming is possible with a small amount of energy.
以上本発明によってなされた発明を実施例にもとづき具
体的に説明したが、本発明は上記実施例に限定されるも
のではな(、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもな〜ゝ。Although the invention made by the present invention has been specifically explained based on Examples, the present invention is not limited to the above-mentioned Examples (it goes without saying that various changes can be made without departing from the gist of the invention). Mona~ゝ.
たとえばA)膜下の段差は1個所だけでなく第6図に示
すように複数個所の段差上を人!配線が横断することに
より、段差部でのAfflの溶断を確実に行ってトリミ
ングを実現することができる。For example, A) There is not only one level difference under the membrane, but there are multiple levels as shown in Figure 6. By crossing the wiring, Affl can be reliably fused at the stepped portion and trimming can be achieved.
本願はIC,LSI全般に適用することができ、とくに
高密度〜高性能の半導体装置に応用した場合にもっとも
効果が太きい。The present invention can be applied to ICs and LSIs in general, and is particularly effective when applied to high-density to high-performance semiconductor devices.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば下記のとおりである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
丁なわち、ICのトリミングを行っても信頼度を維持で
き、グローブの劣化を防げろため多機能のLSIが実現
できろ。さらにそのことにより、外付部品の削減および
無調整化等の高付加価値半導体製品を実現できる。In other words, even if the IC is trimmed, reliability can be maintained and the deterioration of the glove can be prevented, so a multi-functional LSI can be realized. Furthermore, by doing so, it is possible to realize a high value-added semiconductor product with fewer external parts and no adjustment required.
第1図乃至第5図は本発明の一冥施例を示し、このうち
、第1図、第2図、第5図は配諺形成プロセスの工程断
面図である。第3図及び第4図は第2図に対応する平面
図である。
第6図は本発明の応用例を示す一部工程断面図である。
第7図は複数の抵抗を選択的K ト!J ミンクする場
合の回路図である。
第8図はプローブ検査を利用するトリミングの一形態を
示す半導体チップの一部平面図である。
第9図はトリミング時のAノの複数の形祁を示す断面図
である。
1・・・基板、2・・・人!配線、3・・・ポンディン
グパッド、4・・・プローブ針、7・・・Sin、if
f、8・・・段差、9・・・細幅部、10・・・溶断部
。
代理人 弁理士 小 川 勝 男 。
第 1 図
第 3 図1 to 5 show some embodiments of the present invention, and among these, FIGS. 1, 2, and 5 are process sectional views of the proverb formation process. 3 and 4 are plan views corresponding to FIG. 2. FIG. 6 is a partial process sectional view showing an application example of the present invention. Figure 7 shows how to selectively connect multiple resistors. J It is a circuit diagram when minking. FIG. 8 is a partial plan view of a semiconductor chip showing one form of trimming using probe inspection. FIG. 9 is a sectional view showing a plurality of shapes of A during trimming. 1... board, 2... people! Wiring, 3... Bonding pad, 4... Probe needle, 7... Sin, if
f, 8...Step, 9...Narrow width part, 10...Fusion part. Agent: Patent attorney Katsuo Ogawa. Figure 1 Figure 3
Claims (1)
流して上記配線層の特定部位を溶断される半導体装置に
おけるトリミング配線であって、上記被トリミング配線
層の上記特定部位に対応する表面に段差部が形成されて
上記特定部位の配線層の膜厚が上記特定部以外の配線層
の膜厚より薄く形成されていることを特徴とする半導体
装置におけるトリミング配線。 2、上記段差は上記絶縁膜の段差に起因して形成される
ことを特徴とする特許請求の範囲第1項に記載の半導体
装置におけるトリミング配線。[Scope of Claims] 1. Trimming wiring in a semiconductor device in which a specific portion of the wiring layer is cut by blowing a current through a wiring layer formed on an insulating film on a semiconductor substrate, wherein the wiring layer to be trimmed is Trimming wiring in a semiconductor device, wherein a stepped portion is formed on the surface corresponding to the specific portion, and the thickness of the wiring layer at the specific portion is thinner than the thickness of the wiring layer other than the specific portion. . 2. The trimming wiring in a semiconductor device according to claim 1, wherein the step is formed due to a step of the insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21714686A JPS6373639A (en) | 1986-09-17 | 1986-09-17 | Trimming wiring in semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21714686A JPS6373639A (en) | 1986-09-17 | 1986-09-17 | Trimming wiring in semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6373639A true JPS6373639A (en) | 1988-04-04 |
Family
ID=16699575
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21714686A Pending JPS6373639A (en) | 1986-09-17 | 1986-09-17 | Trimming wiring in semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6373639A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007073625A (en) * | 2005-09-05 | 2007-03-22 | Nec Electronics Corp | Semiconductor device and method of manufacturing same |
-
1986
- 1986-09-17 JP JP21714686A patent/JPS6373639A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007073625A (en) * | 2005-09-05 | 2007-03-22 | Nec Electronics Corp | Semiconductor device and method of manufacturing same |
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