JPH0230139A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH0230139A JPH0230139A JP63181079A JP18107988A JPH0230139A JP H0230139 A JPH0230139 A JP H0230139A JP 63181079 A JP63181079 A JP 63181079A JP 18107988 A JP18107988 A JP 18107988A JP H0230139 A JPH0230139 A JP H0230139A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- moisture
- terminal
- aluminum
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000010410 layer Substances 0.000 claims abstract description 134
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 74
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 74
- 239000004020 conductor Substances 0.000 claims abstract description 49
- 239000011241 protective layer Substances 0.000 claims abstract description 15
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 6
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 abstract description 5
- 229910021344 molybdenum silicide Inorganic materials 0.000 abstract description 5
- 239000012466 permeate Substances 0.000 abstract 1
- 238000012360 testing method Methods 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［概要］
複数の端子を有する半導体集積回路装置に関し、プラス
チックパッケージを用いても十分な耐湿性を有する半導
体集積回路装置を提供することを目的とし、
半導体装基板の表面絶縁層上に設けたアルミニウム配線
層を絶縁保護層が覆い、複数の端子領域を有する半導体
集積回路装置において、水分遮蔽性の導電体構造か前記
複数の端子領域の各々を形成し、前期絶縁保護層の下で
、前記アルミニウム配線層と電気的に接触するように構
成する。[Detailed Description of the Invention] [Summary] An object of the present invention is to provide a semiconductor integrated circuit device having a plurality of terminals, which has sufficient moisture resistance even when using a plastic package. In a semiconductor integrated circuit device in which an insulation protection layer covers an aluminum wiring layer provided on an insulation layer and has a plurality of terminal regions, each of the plurality of terminal regions is formed with a moisture-shielding conductor structure, and the insulation protection layer is The aluminum wiring layer is configured to be in electrical contact with the aluminum wiring layer below the layer.
［産業上の利用分野］
本発明は、半導体装置に関し、特に複数の端子を有する
半導体集積回路装置に関する。[Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a semiconductor integrated circuit device having a plurality of terminals.
［従来の技術］
第６図（Ａ＞、（Ｂ）、（Ｃ）に従来例による半導体集
積回路装置（ＩＣ）の端子構造を示す。[Prior Art] FIGS. 6A, 6B, and 6C show the terminal structure of a conventional semiconductor integrated circuit device (IC).
（Ａ）、（Ｂ）が端子部の上面図と断面図、（Ｃ）かウ
ェーハ内の配置を示す。(A) and (B) show a top view and a cross-sectional view of the terminal portion, and (C) shows the arrangement within the wafer.
第６図（Ａ）に示すように、絶縁保護層の開孔８から端
子領域１０が露出する。As shown in FIG. 6(A), the terminal region 10 is exposed through the opening 8 in the insulating protective layer.
第６図（Ｂ）に示すように、半導体基板１の上に５ｉｎ
２、ＰＳＧ等の表面保護膜層２が形成され、その上に回
路部分から連続的に延在するアルミニウム層５が形成さ
れている。ＰＳＧ膜、窒化シリコン膜の積層等の絶縁保
護層６がアルミニウム層５を覆い、窓８内に端子領域９
を露出している。As shown in FIG. 6(B), a 5-inch
2. A surface protection film layer 2 made of PSG or the like is formed, and an aluminum layer 5 extending continuously from the circuit portion is formed thereon. An insulating protective layer 6 such as a laminated layer of a PSG film or a silicon nitride film covers the aluminum layer 5, and a terminal region 9 is formed within the window 8.
is exposed.
第６図（Ｃ）に示すように、周辺雛にこのような端子領
域９を複数備えたチップ領域１１が、ウェーハ１２内に
繰り返し配列されている。チップ領域とチップ領域との
間には、スクライブ（ダイシング）工程で切り代を提供
するスクライブ領域１３が配されている。As shown in FIG. 6(C), chip regions 11 each having a plurality of such terminal regions 9 on the periphery are repeatedly arranged within the wafer 12. As shown in FIG. A scribe region 13 that provides a cutting margin in a scribing (dicing) process is arranged between the chip regions.
上述のように、半導体集積回路装置において、低抵抗率
の配線材料としては一般にアルミニウムが広く利用され
ている。アルミニウムは極めて低い電気抵抗率を有する
点で、配線材料として優れているが、水分によって変化
しやすい。シリコンや別等を含むアルミニウム合金もア
ルミニウムとほぼ同等の特性を有するものは、本明細書
ではアルミニウムと呼ぶ。As mentioned above, aluminum is generally widely used as a low resistivity wiring material in semiconductor integrated circuit devices. Aluminum is excellent as a wiring material in that it has extremely low electrical resistivity, but it is easily changed by moisture. In this specification, aluminum alloys containing silicon and others having substantially the same characteristics as aluminum are referred to as aluminum.
半導体表面は、不純物原子、水分等によって影響されや
すいので、通常シリコン酸化膜、ＰＳＧ等の絶縁保護層
で覆われている。しかし、端子領域ではこれらの絶縁保
護膜が除去されている。Since the semiconductor surface is easily affected by impurity atoms, moisture, etc., it is usually covered with an insulating protective layer such as a silicon oxide film or PSG. However, these insulating protective films are removed in the terminal areas.
実装としては、プラスチックパッケージが広く利用され
ている。製造原価が低く、製造が容易である利点を持つ
が、セラミックパッケージ等と比べ、耐湿性が低い。Plastic packages are widely used for packaging. Although it has the advantages of low manufacturing cost and ease of manufacture, it has lower moisture resistance than ceramic packages and the like.
［発″明が解決しようとする課題］
耐水性は半導体集積回路装置における一般的課題の１つ
である。[Problems to be Solved by the Invention] Water resistance is one of the general issues in semiconductor integrated circuit devices.
特に、プラスチックパッケージを用いた場合、アルミニ
ウム配線の半導体集積回路装置においては、外部からの
水分の侵入によってアルミニウム配線層の腐蝕を起こし
易い。In particular, when a plastic package is used in a semiconductor integrated circuit device with aluminum wiring, the aluminum wiring layer is likely to be corroded by moisture entering from the outside.
本発明の目的は、プラスチックパッケージを用いても十
分な耐湿性を有する半導体集積回路装置を提供すること
である。An object of the present invention is to provide a semiconductor integrated circuit device that has sufficient moisture resistance even when using a plastic package.
また、耐湿性のある導電体は存在するが、そのような材
料で形成した導電層は、アルミニウム配線層に比べて抵
抗が高くなり易く、ワイヤボンディングが困難である等
の問題を有する。Further, although moisture-resistant conductors exist, conductive layers formed from such materials tend to have higher resistance than aluminum wiring layers, and have problems such as difficulty in wire bonding.
本発明の他の目的は、アルミニウムのみを用いて配線層
、端子層を形成した時と比べほぼ同等の配線抵抗、ワイ
ヤボンディング適性を有し、かつ耐湿性を向上させた半
導体集積回路装置を提供することである。Another object of the present invention is to provide a semiconductor integrated circuit device that has substantially the same wiring resistance and wire bonding suitability as when wiring layers and terminal layers are formed using only aluminum, and has improved moisture resistance. It is to be.
特に、高電圧、大電流を印加するテスト専用の端子にお
いて、アルミニウム配線層の腐蝕か激しく発生し易く、
腐蝕がアルミニウム配線を経て回路内部に侵入すること
が経験的に見出だされる。In particular, in terminals dedicated to testing that apply high voltages and large currents, severe corrosion of the aluminum wiring layer is likely to occur.
It has been found empirically that corrosion penetrates into the circuit through the aluminum wiring.
また、従来、スクライブ領域はスクライブの目的の他は
位置合せマークを配置するのに利用される程度であった
。Furthermore, conventionally, the scribe area has been used for the purpose of scribing and for arranging alignment marks.
本発明の他の目的は、スクライブ領域をテスト時の端子
用面積として利用し、スクライブ後は水分に対して抵抗
力を高めた半導体集積回路装置を提供することである。Another object of the present invention is to provide a semiconductor integrated circuit device that utilizes the scribe area as a terminal area during testing and has increased resistance to moisture after scribing.
また、半導体集積回路装置において、シリサイドの利用
が進められているが、その用途か十分開発されたとは言
えない。Further, although the use of silicide is being promoted in semiconductor integrated circuit devices, it cannot be said that its uses have been sufficiently developed.
本発明の他の目的は、シリサイドの特性を有効に利用し
た半導体集積回路装置を提供することである。Another object of the present invention is to provide a semiconductor integrated circuit device that effectively utilizes the characteristics of silicide.
１課題を解決するための手段］
第１図（Ａ）、（Ｂ）を参照して、半導体装基板（１）
の表面絶縁層（２）上に設けたアルミニウム配線層（３
）を絶縁保護層（６）が覆い、複数の端子領域（９）を
有する半導体集積回路装置において、水分遮蔽性の導電
体構造（４）が複数の端子領域（９）の各々を形成し、
絶縁保護層（６）の下で、アルミニウム配線層（３）と
電気的に接触する。Means for Solving Problem 1] With reference to FIGS. 1(A) and (B), a semiconductor packaging substrate (1)
aluminum wiring layer (3) provided on the surface insulating layer (2) of
) covered with an insulating protective layer (6) and having a plurality of terminal regions (9), a moisture-shielding conductor structure (4) forming each of the plurality of terminal regions (9);
Electrical contact is made with the aluminum wiring layer (3) under the insulating protection layer (6).
また、端子面を構成するアルミニウム端子層と、アルミ
ニウム配線層およびアルミニウム端子層に電気的に接触
する耐湿性導電体層とでこの水分遮蔽性の導電体構造（
４）を構成する。In addition, this moisture-shielding conductor structure (
4).
また、ワイヤ配線しない端子においては、スクライブ領
域内にアルミニウム端子層を配置し、チップ領域内のア
ルミニウム配線層と耐湿性導電体層を介して接続する。In addition, in a terminal without wire wiring, an aluminum terminal layer is arranged in the scribe region and connected to an aluminum wiring layer in the chip region via a moisture-resistant conductor layer.
耐湿性導電体層は、好ましくはシリサイドで形成する。The moisture-resistant conductor layer is preferably formed of silicide.
［作用］
半導体集積回路装置において、端子面においては絶縁保
護層に開孔が形成されており、水分が最も侵入しやすい
のはこの端子部分を介する経路を通ってである。[Function] In a semiconductor integrated circuit device, openings are formed in the insulating protective layer on the terminal surface, and it is through the path through this terminal portion that moisture most easily enters.
端子領域（９）を水分遮蔽性の導電体構造によって形成
すると、侵入した水分を端子領域で防ぎ止め、回路部分
を水分の侵入から保護することができる。When the terminal region (9) is formed of a moisture-shielding conductive structure, the terminal region can prevent and stop moisture from entering, and the circuit portion can be protected from moisture.
このような水分遮蔽性の導電体構造をアルミニウム配線
層と接触する耐湿性導電体層と、この耐湿性導電体層に
接触するアルミニウム端子層を用いて構成することによ
り配線抵抗、ワイヤポンデイ・ング適性はアルミニウム
のみを用いた場合とほぼ同等にすることができる。By constructing such a moisture-shielding conductor structure using a moisture-resistant conductor layer in contact with an aluminum wiring layer and an aluminum terminal layer in contact with this moisture-resistant conductor layer, wiring resistance and wire bonding suitability can be improved. can be made almost equivalent to using only aluminum.
また高電圧大電流を印加するテスト用端子は特に腐蝕が
激しいが、テスト用の端子をスクライブ領域内に配する
ことによって、半導体表面の利用率を向上でき、かつテ
スト後はスクライブすることにより、アルミニウム端子
層自身を消滅させ、内部のアルミニウム配線を腐蝕から
守ることができる。In addition, test terminals that apply high voltage and large current are particularly susceptible to severe corrosion, but by arranging test terminals within the scribe area, the utilization rate of the semiconductor surface can be improved, and by scribing after testing, It is possible to eliminate the aluminum terminal layer itself and protect the internal aluminum wiring from corrosion.
シリサイド、特にタングステンシリサイドとモリブデン
シリサイドは、化学的に安定で導電性も十分高く、アル
ミニウムと組み合わせて低抵抗導電体として用いるのに
適している。Silicides, particularly tungsten silicide and molybdenum silicide, are chemically stable and have sufficiently high conductivity, making them suitable for use in combination with aluminum as low-resistance conductors.
［実施例］
第１図（Ａ）、（Ｂ）に本発明の基本実施例による半導
体集積回路装置を示す、（Ａ）は断面図、（Ｂ）は上面
図である。[Embodiment] FIGS. 1A and 1B show a semiconductor integrated circuit device according to a basic embodiment of the present invention, in which FIG. 1A is a cross-sectional view and FIG. 1B is a top view.
シリコン（Ｓｉ）等の半導体基板１上には酸化シリコン
（ＳｉＯｚ）、ＰＳＧ等の表面絶縁層２が形成されてお
り、その上にアルミニウム（ＡＩ）またはアルミニウム
合金のアルミニウム配線層３が形成され導電パターンを
構成している。＃ｉ子付近の領域において、アルミニウ
ム配線層３は端子より手前で絶縁保護層６に完全に覆わ
れた状態で終端している。端子領域９は水分遮蔽性の導
電体構造４で形成され、絶縁保護層６の下に延在して配
線層３と重なり、配線層３と電気的に接続している０図
では、導電体構造４の上にアルミニウム配線層３が積層
しているか、これに限らなくてもよい、導電体構造４、
アルミニウム配線層３の上に燐珪酸カラス（ＰＳＧ）、
窒化シリコン（ＳｔＮ ）等の絶縁保護層６が形成され
、その窓８内に端子面を露出している。なお、水分遮蔽
性の導電体構造４は全体または１部が水分を通さず、水
分に侵されない導電体の構造物であり、侵入した水分は
アルミニウム配線層３に達しないものである。水分を通
さず、水分に侵されない低抵抗の導電体としてはモリブ
デンシリサイド、タングステンシリサイド等のシリサイ
ドが好適である。水分が侵入して、端子面が水分にさら
されても、端子領域９を通過して配線層３まで水分が到
達することは防止される。A surface insulating layer 2 made of silicon oxide (SiOz), PSG, etc. is formed on a semiconductor substrate 1 made of silicon (Si), etc., and an aluminum wiring layer 3 made of aluminum (AI) or aluminum alloy is formed thereon to provide conductivity. constitutes a pattern. In the region near the #i element, the aluminum wiring layer 3 terminates in a state where it is completely covered by the insulating protective layer 6 before the terminal. The terminal area 9 is formed of a conductor structure 4 with moisture-shielding properties, and extends under the insulating protection layer 6, overlaps with the wiring layer 3, and is electrically connected to the wiring layer 3. A conductor structure 4, which may or may not be limited to an aluminum wiring layer 3 laminated on the structure 4;
Phosphorsilicate glass (PSG) is placed on the aluminum wiring layer 3.
An insulating protective layer 6 such as silicon nitride (StN 2 ) is formed, and the terminal surface is exposed within the window 8 . The moisture-shielding conductor structure 4 is a conductor structure that is entirely or partially impermeable to moisture and is not attacked by moisture, and any moisture that enters does not reach the aluminum wiring layer 3. Silicides such as molybdenum silicide and tungsten silicide are suitable as low-resistance conductors that are impervious to moisture and are not attacked by moisture. Even if moisture enters and the terminal surface is exposed to moisture, the moisture is prevented from passing through the terminal region 9 and reaching the wiring layer 3.
ところでワイヤボンディングを行う端子面はアルミニウ
ム面であることが望まれることかある。By the way, it is sometimes desired that the terminal surface for wire bonding be an aluminum surface.
第２図に本発明の実施例によるアルミニウム端子面を有
する端子構造を示す、半導体基板１、表面絶縁層２、ア
ルミニウム配線層３、絶縁保護層６は第１図（Ａ）、（
Ｂ）の場合と同様である。FIG. 2 shows a terminal structure having an aluminum terminal surface according to an embodiment of the present invention. The semiconductor substrate 1, the surface insulating layer 2, the aluminum wiring layer 3, and the insulating protective layer 6 are shown in FIG.
This is the same as case B).
端子面はアルミニウム配線層３とは分離したアルミニウ
ム端子層４ｂによって形成されている。アルミニウム端
子層４ｂとアルミニウム配線層３とが耐湿性導電体層４
ａによって電気的に接続されている。The terminal surface is formed by an aluminum terminal layer 4b separated from the aluminum wiring layer 3. The aluminum terminal layer 4b and the aluminum wiring layer 3 form a moisture-resistant conductor layer 4.
electrically connected by a.
耐湿性導電体層４ａは水分に対して安定な導電体の層で
ある。半導体集積回路装置の場合、絶縁保護膜としてＰ
ＳＧを用いることが多いが、ＰＳＧの燐か水分によって
溶は出すと燐酸を形成する。The moisture-resistant conductive layer 4a is a conductive layer that is stable against moisture. In the case of semiconductor integrated circuit devices, P is used as an insulating protective film.
SG is often used, but when phosphorus in PSG is dissolved by moisture, phosphoric acid is formed.
ｉｆｆ湿性導電体層４はこのような水分による派生物に
対しても化学的に安定な材料、たとえばモリブデンシリ
サイド、タングステンシリサイド等のシリサイドで構成
する。The IF wet conductor layer 4 is made of a material that is chemically stable even against such moisture derivatives, such as a silicide such as molybdenum silicide or tungsten silicide.
第３図により具体的な実施例を示す。A concrete example is shown in FIG.
シリコン基板１上に酸化シリコン層２ａが形成されてお
り、その上にモリブデンシリサイドまたはタングステン
シリサイドの耐湿性導電体層４ａが形成されている。酸
化シリコン層２ａはウェット熱酸化によって、耐湿性導
電体層であるシリサイド層４ａは化学気相堆［（ＣＶＤ
）で堆積した後、高温熱処理を行うことによって形成で
きる。A silicon oxide layer 2a is formed on a silicon substrate 1, and a moisture-resistant conductive layer 4a of molybdenum silicide or tungsten silicide is formed thereon. The silicon oxide layer 2a is formed by wet thermal oxidation, and the silicide layer 4a, which is a moisture-resistant conductor layer, is formed by chemical vapor deposition [(CVD).
) and then high-temperature heat treatment.
耐湿性導電体層４ａの上にはＰＳＧ層２ｂが形成されて
いる。耐湿性導電体層４ａとコンタクトを形成する部分
では、ＰＳＧ層２ｂに開孔が開けられている。ＰＳＧ層
２ｂの上にアルミニウム配線層３とアルミニウム端子層
４ｂを形成する厚さ約１μｍのアルミニウム層が電子ビ
ーム蒸着されている。このアルミニウム層はパターニン
グの段階でアルミニウム配線層３とアルミニウム端子層
４ｂに分離される。アルミニウム配線層３はたとえば５
μｍ−１０μｍの幅のストライプ形状で、耐湿性導電体
層４ａとＰＳＧ層２ｂ中の幾つかのコンタクト開孔を通
して接触する。アルミニウム端子層４ｂはたとえば１０
０μｍＸ１００μｍのパッド領域を有し、パッド領域か
ら突出するたとえば５μｍ−１０μｍ幅の接続用領域を
有し、耐湿性導電体層４ａとＰＳＧ層２ｂ中の幾つかの
コンタクト開孔を通して接触する。A PSG layer 2b is formed on the moisture-resistant conductor layer 4a. An opening is made in the PSG layer 2b at a portion where contact is to be made with the moisture-resistant conductor layer 4a. On the PSG layer 2b, an aluminum layer having a thickness of about 1 μm is deposited by electron beam, forming an aluminum wiring layer 3 and an aluminum terminal layer 4b. This aluminum layer is separated into an aluminum wiring layer 3 and an aluminum terminal layer 4b at the patterning stage. The aluminum wiring layer 3 is, for example, 5
Contact is made through several contact openings in the moisture-resistant conductor layer 4a and the PSG layer 2b in the form of stripes with a width of .mu.m-10 .mu.m. For example, the aluminum terminal layer 4b has a thickness of 10
It has a pad area of 0 μm x 100 μm, and has a connecting region, for example 5 μm-10 μm wide, protruding from the pad area and makes contact through several contact openings in the moisture-resistant conductor layer 4a and the PSG layer 2b.
アルミニウム層の上には２３０層６ａと窒化シリコン層
６ｂか形成され、絶縁保護層６を形成している。２３０
層６ａはたとえば約１μｍの厚さ、窒化シリコン層６ｂ
はたとえば０．５μｍの厚さを持つ、端子領域９では窒
化シリコン層６ｂと２３０層６ａが選択エツチングされ
てアルミニウム端子層４ｂを露出している。窒化シリコ
ン層６ｂは水分に対する遮蔽効果が高く、２３０層６ａ
を覆っているか端子用開孔部分では２３０層６ａの側面
が露出することになる。しかし、侵入した水分によって
アルミニウム端子層４ｂが腐蝕されても耐湿性導電体層
４ａまで腐蝕されることはなく、回路部分は水分の侵入
から保護される。A 230 layer 6a and a silicon nitride layer 6b are formed on the aluminum layer to form an insulating protective layer 6. 230
Layer 6a is for example approximately 1 μm thick, silicon nitride layer 6b
In the terminal region 9, the silicon nitride layer 6b and the 230 layer 6a are selectively etched to expose the aluminum terminal layer 4b, which has a thickness of, for example, 0.5 μm. The silicon nitride layer 6b has a high moisture shielding effect, and the 230 layer 6a
The side surface of the 230 layer 6a is exposed at the opening for the terminal. However, even if the aluminum terminal layer 4b is corroded by the moisture that has entered, the moisture-resistant conductor layer 4a is not corroded, and the circuit portion is protected from the invasion of moisture.
第４図は、他の実施例による端子構造を示す。FIG. 4 shows a terminal structure according to another embodiment.
第６図（Ｃ）に示したように、半導体ウェーハにはチッ
プ領域１１とスクライブ領域１３とが配置されているか
、ワイヤボンディングする端子領域９ａはチップ領域１
１内に、テスト時のみに使用しワイヤボンディングしな
い端子領域９ｂはスクライブ領域１３に配置する。As shown in FIG. 6(C), a chip region 11 and a scribe region 13 are arranged on the semiconductor wafer, or the terminal region 9a to be wire bonded is located in the chip region 1.
1, a terminal area 9b that is used only during testing and is not wire-bonded is arranged in a scribe area 13.
ワイヤボンディングする端子領域９ａについては、チッ
プ領域１１周辺部に耐湿性導電体層４ａを設けられてい
る。その上面にアルミニウム配線層３とアルミニウム端
子層４ａは相互には分離されており、その下面で耐湿性
導電体層４ａと電気的接触を形成している。耐湿性導電
体層４ａは端子領域９ａの中央部を除去した環状の形状
をしている。電気的接触は耐湿性導電体層４ａ上の絶縁
層にいくつかのコンタクト開化を設けて行ってもよく、
耐湿性導電体層４ａの表面をほとんど露出して全面で行
ってもよい、アルミニウム端子層４ｂと耐湿性導電体層
４ａとのオーバラッグ部分全面でコンタクトをとれば断
線に対する抵抗力は増す、ワイヤボンディングしない端
子領域９ｂについては、スクライブ領域１３とチップ領
域１１をブリッジするように耐湿性導電体層２４ａを形
成し、アルミニウム配線層２３はチップ領域１１内で耐
湿性導電体層２４ａと電気的接触を形成し、アルミニウ
ム端子層２４ｂはスクライブ領域１３内で耐湿性導電体
層２４ａと電気的接触を形成する。Regarding the terminal area 9a for wire bonding, a moisture-resistant conductive layer 4a is provided around the chip area 11. The aluminum wiring layer 3 and the aluminum terminal layer 4a are separated from each other on the upper surface, and are in electrical contact with the moisture-resistant conductor layer 4a on the lower surface. The moisture-resistant conductor layer 4a has an annular shape with the center portion of the terminal region 9a removed. Electrical contact may be made by providing several contact openings in the insulating layer on the moisture-resistant conductor layer 4a,
Wire bonding may be carried out over the entire surface of the moisture-resistant conductor layer 4a with almost all of its surface exposed.If contact is made over the entire surface of the overlapping portion between the aluminum terminal layer 4b and the moisture-resistant conductor layer 4a, the resistance to disconnection increases. For the terminal area 9b that is not connected, the moisture-resistant conductor layer 24a is formed to bridge the scribe area 13 and the chip area 11, and the aluminum wiring layer 23 is in electrical contact with the moisture-resistant conductor layer 24a within the chip area 11. The aluminum terminal layer 24b forms electrical contact with the moisture-resistant conductor layer 24a within the scribe area 13.
テスト後、スクライブすることにより、スクライブ領域
に形成したアルミニウム端子層２４ｂは消滅する。これ
により、テスト時の高電圧、大電流の影響を減じること
ができる。切断面には耐湿性導電体層２４ａが露出する
が、水分によってダメージを受けない。After the test, the aluminum terminal layer 24b formed in the scribe area disappears by scribing. This makes it possible to reduce the effects of high voltage and large current during testing. Although the moisture-resistant conductor layer 24a is exposed at the cut surface, it is not damaged by moisture.
なお、耐湿性導電体層は種々の形状とすることができる
。第５図（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）にその例を示
す、第５図（Ａ）は第４図のワイヤボンディングする端
子９ａで示した構成と同類の形状であり、アルミニウム
端子層４ｂの下の部分で中央部を開孔し、周辺部の下に
広めに耐湿性導電体層４ａが形成されている。第５図（
Ｂ）では、アルミニウム端子層４ｂの中央部にも耐湿性
導電体層４ａが形成されている。第５図（Ｃ）は、接続
部のみに耐湿性導電体層４ａを備えたもので第４図のワ
イヤボンディングしない端子９ｂに用いたものと同類の
形状である。スクライブ領域のワイヤボンディングしな
い端子の場合に限らずチツグ領域の端子、ワイヤボンデ
ィングする端子に適用してもよい、第５図（Ｄ）は第１
図の構成に対応するもので、端子部分が耐湿性導電体層
４ａで構成され、絶縁保護層下でアルミニウム配線層３
と接触する形状である。Note that the moisture-resistant conductor layer can have various shapes. Examples are shown in FIGS. 5(A), (B), (C), and (D). FIG. 5(A) has a configuration similar to that shown in the wire bonding terminal 9a in FIG. 4. A hole is formed in the center below the aluminum terminal layer 4b, and a moisture-resistant conductive layer 4a is formed widely below the periphery. Figure 5 (
In B), a moisture-resistant conductor layer 4a is also formed in the center of the aluminum terminal layer 4b. FIG. 5(C) has a moisture-resistant conductive layer 4a only at the connection portion, and has a similar shape to that used for the terminal 9b without wire bonding in FIG. The application is not limited to terminals in the scribe area that are not wire-bonded, but may also be applied to terminals in the scribe area and terminals that are wire-bonded.
This corresponds to the configuration shown in the figure, in which the terminal portion is composed of a moisture-resistant conductor layer 4a, and an aluminum wiring layer 3 is formed under the insulating protective layer.
It has a shape that makes contact with the
アルミニウム配線層３ないしアルミニウム端子層４ｂと
耐湿性導電体層４との接触はオーバラップする部分内で
コンタクト開孔を通して選択的に部分的に行ってもよく
、また全面で行ってもよい。The contact between the aluminum wiring layer 3 or the aluminum terminal layer 4b and the moisture-resistant conductor layer 4 may be selectively made partially through contact holes in the overlapping portion, or may be made over the entire surface.
なお、各実施例について説明した内容を適宜組み合わせ
てもよいことは当業者に自明であろう。It will be obvious to those skilled in the art that the contents described for each embodiment may be combined as appropriate.
［発明の効果コ
プラスチックパッケージのような水分にたいして十分な
遮蔽性を有しないパッケージを採用しても、侵入した水
分か回路部分に達するのを防止できる。これによって半
導体集積回路装置の倍額性を向上できる。[Effects of the Invention] Even if a package such as a co-plastic package is used that does not have sufficient shielding properties against moisture, it is possible to prevent moisture from entering the circuit. This makes it possible to improve the multiplicity of the semiconductor integrated circuit device.
第１図（Ａ＞、（Ｂ）は本発明の基本実施例を示す断面
図と上面図、
第２図は、本発明の実施例による端子構造を示す断面図
、
第３図は、本発明の他の実施例による端子構造を示す断
面図、
第４図は本発明の池の実施例のよる端子構造を示す上面
図、
第５図（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）は耐湿性導電体
層の形状を示す上面図、
第６図（Ａ）、（Ｂ）、（Ｃ）は従来のｒｃ＠子を説明
するための上面図、断面図、ウェーハ内配置図である。
ａ
ｂ
ｉｆ？湿性導電体層
アルミニウム端子層
絶縁保護層
開孔
端子領域
図において、
１ 半導体基板
２ 表面絶縁層
３ Ａ！配線層
４ 水分遮蔽性の導電体構造
（Ｂ）
上面図
本発明の基本実施例
第
図
第
図
第
図
第
図
（Ａ）
（Ｂ）
（Ｃ）
耐湿性導電１の形状例
第
図
従未伊１のＩＣの端子構造
第
図FIGS. 1A and 1B are a sectional view and a top view showing a basic embodiment of the present invention, FIG. 2 is a sectional view showing a terminal structure according to an embodiment of the present invention, and FIG. 3 is a sectional view showing a basic embodiment of the present invention. FIG. 4 is a top view showing a terminal structure according to another embodiment of the present invention; FIGS. 5(A), (B), (C), (D ) is a top view showing the shape of the moisture-resistant conductor layer, and Figures 6 (A), (B), and (C) are top views, cross-sectional views, and layout diagrams within the wafer to explain the conventional RC@. a b if? Wet conductor layer Aluminum terminal layer Insulating protective layer Open terminal area diagram: 1 Semiconductor substrate 2 Surface insulating layer 3 A! Wiring layer 4 Moisture-shielding conductor structure (B) Top view of the present invention (A) (B) (C) Example of shape of moisture resistant conductor 1 Figure 1 Terminal structure of IC 1
Claims (4)
けたアルミニウム配線層（３）を絶縁保護層（６）が覆
い、複数の端子領域（９）を有する半導体集積回路装置
において、 水分遮蔽性の導電体構造（４）が前記複数の端子領域（
９）の各々を形成し、前期絶縁保護層（６）の下で、前
記アルミニウム配線層（３）と電気的に接触することを
特徴とする半導体集積回路装置。(1) A semiconductor integrated circuit device in which an insulating protective layer (6) covers an aluminum wiring layer (3) provided on a surface insulating layer (2) of a semiconductor board (1) and has a plurality of terminal regions (9). In the method, a moisture-shielding conductor structure (4) is provided in the plurality of terminal regions (
9), and is in electrical contact with the aluminum wiring layer (3) under the insulating protective layer (6).
を形成するアルミニウム端子層（４ｂ）と、前記アルミ
ニウム配線層（３）および前記アルミニウム端子層（４
ｂ）に電気的に接触する耐湿性導電体層（４ａ）とを含
むことを特徴とする請求項１記載の半導体集積回路装置
。(2), the moisture-shielding conductor structure (4) includes an aluminum terminal layer (4b) forming a terminal surface, the aluminum wiring layer (3) and the aluminum terminal layer (4b);
2. The semiconductor integrated circuit device according to claim 1, further comprising a moisture-resistant conductor layer (4a) in electrical contact with the semiconductor integrated circuit device (b).
ウム端子層（４ｂ）が、スクライブ領域内に配置され、
前記耐湿性導電体層（４ａ）がチップ領域内の前記アル
ミニウム配線層（３）と前スクライブ領域内のアルミニ
ウム端子層（４ｂ）をブリッジし、電気的に接続するこ
とを特徴とする請求項２記載の半導体集積回路装置。(3) for terminals that are not wired, the aluminum terminal layer (4b) is arranged within the scribe area;
2. The moisture-resistant conductor layer (4a) bridges and electrically connects the aluminum wiring layer (3) in the chip area and the aluminum terminal layer (4b) in the pre-scribe area. The semiconductor integrated circuit device described above.
成されていることを特徴とする請求項２ないし３記載の
半導体集積回路装置。(4) The semiconductor integrated circuit device according to claim 2 or 3, wherein the moisture-resistant conductor layer (4a) is formed of silicide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63181079A JPH0230139A (en) | 1988-07-20 | 1988-07-20 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63181079A JPH0230139A (en) | 1988-07-20 | 1988-07-20 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0230139A true JPH0230139A (en) | 1990-01-31 |
Family
ID=16094443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63181079A Pending JPH0230139A (en) | 1988-07-20 | 1988-07-20 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0230139A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61123468U (en) * | 1985-01-22 | 1986-08-04 | ||
| JPH07130789A (en) * | 1993-11-04 | 1995-05-19 | Nec Corp | Semiconductor device |
-
1988
- 1988-07-20 JP JP63181079A patent/JPH0230139A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61123468U (en) * | 1985-01-22 | 1986-08-04 | ||
| JPH07130789A (en) * | 1993-11-04 | 1995-05-19 | Nec Corp | Semiconductor device |
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