JPS61121348A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61121348A JPS61121348A JP59242385A JP24238584A JPS61121348A JP S61121348 A JPS61121348 A JP S61121348A JP 59242385 A JP59242385 A JP 59242385A JP 24238584 A JP24238584 A JP 24238584A JP S61121348 A JPS61121348 A JP S61121348A
- Authority
- JP
- Japan
- Prior art keywords
- conductor wiring
- wiring metal
- bonding pad
- nitride film
- whole surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分骨)
コノ発明は、高信頼性モールドパッケージデバイスの信
頼性を大幅に向上できるようにした半導体装置に関する
。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application) The present invention relates to a semiconductor device that can significantly improve the reliability of a highly reliable mold package device.
(従来の技術)
現在、半導体素子のパッケージは、価格上の問題からモ
ールドパッケージが主流となっている。(Prior Art) Currently, mold packages are the mainstream for semiconductor device packages due to cost considerations.
第2図は従来のボンディングパッド部の断面図であり、
この第2図に招ける10は基板である。基板10上に導
体配線メタル1が形成されてお9、その上にパシベーシ
ョン膜2が形成されている。FIG. 2 is a cross-sectional view of a conventional bonding pad section.
10 in FIG. 2 is a substrate. A conductor wiring metal 1 is formed on a substrate 10, and a passivation film 2 is formed thereon.
7はポンディングワイヤを示す。しかし、半導体素子信
頼性に関しては、セラミックパッケージに比較し、基本
的な欠点(樹脂自体の水分透過性、樹脂とリードの界面
からの水分浸入など)を有しており、糎々の対策により
、この基本的な欠点を補い、セラミックパッケージでの
信頼性に近づける努力がなされている。具体的には、
(1)半導体素子自体のパシベーション膜副湿性向上、
(2) リードの蛇行化などによる外気水分のチップ
への到達距1m(時間)の引きのばしくたとえば特公昭
51−4905号公報)、
+31 1f脂材質検討による最適化、などが行なわれ
ている。7 indicates a bonding wire. However, in terms of semiconductor device reliability, compared to ceramic packages, it has fundamental drawbacks (moisture permeability of the resin itself, moisture intrusion from the interface between the resin and leads, etc.). Efforts are being made to compensate for this fundamental drawback and bring the reliability closer to that of ceramic packages. Specifically, (1) Improving the sub-humidity of the passivation film of the semiconductor element itself, (2) Prolonging the reach distance of outside air moisture to the chip by 1 m (hour) due to meandering of the leads, etc. (publication), +31 1f Optimization by examining lipid materials, etc.
(発明が解決しようとする問題点)
しかしながら、モールドパッケージデバイスの耐湿性向
上のために、種々対策が実施されているにもかかわらず
、今もって信頼性向上対策は重大な課題となっている。(Problems to be Solved by the Invention) However, although various measures have been taken to improve the moisture resistance of mold packaged devices, measures to improve reliability still remain a serious issue.
モールドパッケージデバイスへの外気水分の浸入a路と
しては、リードフレームを介したボンディングワイヤか
らの経路およびモールドパッケージ自体の透過経路が挙
げられる。Paths for the entry of outside air moisture into the molded package device include a path from the bonding wire via the lead frame and a permeation path through the molded package itself.
この発明は、前記従来技術がもっている問題点のうち1
モールドパツケージデバイスの信頼性の欠如について解
決した半導体装置を提供するものである。This invention solves one of the problems that the prior art has.
The present invention provides a semiconductor device that solves the problem of unreliability of molded package devices.
(問題点を解決するための手段)
この発明は、半導体装置において、導体配線ホトリソ・
エツチング工程でボンディングパッドエリア形成を行な
うことなく、パシベーション膜およびポリイミド系樹脂
層を形成し、ポリイミド系樹脂層上に、ボンディングパ
ッドのみを分離形成する際、ボンディングパッド周辺導
体配線メタルのみを除去し、ポリイミド系樹脂層上はぼ
全面に、導体配線メタル層を形成したものである。(Means for Solving the Problems) This invention provides conductor wiring photolithography in semiconductor devices.
A passivation film and a polyimide resin layer are formed without forming a bonding pad area in an etching process, and when only the bonding pad is separately formed on the polyimide resin layer, only the conductor wiring metal around the bonding pad is removed. A conductive wiring metal layer is formed almost entirely on the polyimide resin layer.
(作 用)
この発明によれば、以上のようにウニへ表面のポリイミ
ド系樹脂層上に、ボンディングパッドエリアを形成して
回路形成エリアとボンディングパッドエリアの分離を行
い、ポリイミド系樹脂層上にボンディングパッドととも
に導体配線用メタル層を形成する。(Function) According to the present invention, as described above, a bonding pad area is formed on the polyimide resin layer on the surface of the sea urchin to separate the circuit forming area and the bonding pad area, and the bonding pad area is separated from the bonding pad area on the polyimide resin layer. A metal layer for conductor wiring is formed together with the bonding pad.
(実施例)
息下、この発明の半導体装置の実施例について図面に基
づき説明する。第1図(alないし第1図(clはその
一実施例を説明するための工程図である。(Example) An example of the semiconductor device of the present invention will now be described based on the drawings. FIG. 1(al) to FIG. 1(cl) are process diagrams for explaining one embodiment.
この第1図(al〜第1図(clにおいて、第2図と同
一部分には同一符号を付して述べる。In FIG. 1(al) to FIG. 1(cl), the same parts as in FIG. 2 will be described with the same reference numerals.
まず、第1図(alに示すように、基板10に導体配線
メタル1の導体配線パターニング後に、パシベーション
膜2を全面に形成し、引き続きポリイミド系樹脂3を全
面にコーテイング後十分にキュアを施こす。First, as shown in FIG. 1 (al), after patterning the conductor wiring metal 1 on the substrate 10, a passivation film 2 is formed on the entire surface, and then a polyimide resin 3 is coated on the entire surface and sufficiently cured. .
次いで、ポリイミド系樹脂3上にプラズマCVDによl
)、aso℃以下で窒化膜4を全面に形成する。さらに
、この窒化膜4上には、レジスト膜5を塗布することに
より、導体配線メタル1との導通をポリイミド系樹脂3
上に引き出すためのコンタクトホトリソパターン8を形
成し、プラズマドライエツチングにより□、コンタクト
部の窒化膜4の除去を行なう。Next, a film was formed on the polyimide resin 3 by plasma CVD.
), a nitride film 4 is formed over the entire surface at a temperature below aso°C. Furthermore, by applying a resist film 5 on this nitride film 4, conduction with the conductive wiring metal 1 is established using the polyimide resin 3.
A contact photolithographic pattern 8 is formed for drawing upward, and the nitride film 4 at the contact portion is removed by plasma dry etching.
次いで、CF4+02系プラズマにより、コンタクト部
のポリイミド系樹脂3および窒化膜4上のレジスト膜5
を同時に除去する。Next, the resist film 5 on the polyimide resin 3 and nitride film 4 in the contact area is removed using CF4+02 plasma.
remove at the same time.
次に、コンタクト部パシベーション膜2およびポリイミ
ド系i脂3上の窒化膜4をプラズマドライエツチングに
より同時除去する。Next, the contact passivation film 2 and the nitride film 4 on the polyimide i-based resin 3 are simultaneously removed by plasma dry etching.
次に、第1図fblに示すように、導体配線メタル6を
スパッタリングにより全面に形成する。この際、導体配
線メタル6は、導体配線メタル1に比較し、電気化学的
に同等かまたは卑な材質とする。Next, as shown in FIG. 1 fbl, a conductor wiring metal 6 is formed over the entire surface by sputtering. At this time, the conductor wiring metal 6 is made of a material that is electrochemically equivalent to or less noble than the conductor wiring metal 1.
最後に、第1図(C1に示すように、ポリイミド系1m
膳3上の導体配線メタル6のボンディングパッドエリア
6aにボンディングワイヤ7をボンディングパッドする
とともに、回路形成エリア6bでな(、このボンディン
グパッドエリア6aのボンディングパッドエリア6aに
おいて本トリソエッチングを行なう。この際は、ポリイ
ミド系樹脂3上のボンディングパッドエリア6aのボン
ディングワイヤ70周辺部のみを除去するものとする。Finally, as shown in Figure 1 (C1), a polyimide 1 m
The bonding wire 7 is bonded to the bonding pad area 6a of the conductor wiring metal 6 on the tray 3, and the main triso etching is performed on the bonding pad area 6a of the bonding pad area 6a. Assume that only the peripheral portion of the bonding wire 70 in the bonding pad area 6a on the polyimide resin 3 is removed.
以上の構成によゆ、デバイス最上層は、導体配線メタル
6によりほぼ全面が覆われた状態となる。According to the above configuration, the uppermost layer of the device is almost entirely covered with the conductor wiring metal 6.
モールドパッケージにおいて、モールド1lfNl自体
を透過浸入して来た水分は、デバイス最上層の導体配線
メタル6と最初に接することになり、この導体配線メタ
ル6と選択的に反応(腐食反応)を生じることにより、
透過水分を消耗する。In the mold package, the moisture that permeates through the mold 1lfNl itself comes into contact with the conductor wiring metal 6 on the top layer of the device, and selectively reacts (corrosion reaction) with the conductor wiring metal 6. According to
Consumes permeated water.
このことから、デバイス自体への水分到達時間に大幅な
遅れを生じさせろことができ、モールドパッケージデバ
イスの耐湿性に関する大幅な信頼性向上をはかることが
できろ。From this, it is possible to cause a significant delay in the time that moisture reaches the device itself, and it is possible to significantly improve the reliability of the moisture resistance of the mold packaged device.
(発明の効果)
以上詳細に説明したように、この発明によれば、ウニ八
表面上にポリイミド系樹脂層を形成し、その上にボンデ
ィングパッドエリアを回路形成エリアと分離形成する製
造プロセスにおいて新たな製造プロセスを付加すること
な(、デバイス最上層をほぼ全面に、導体配線メタル層
を形成するようにしたので、モールドパッケージデバイ
スの耐湿性に関する信頼性を大幅に向上させることがで
きる。(Effects of the Invention) As explained in detail above, according to the present invention, a new manufacturing process is adopted in which a polyimide resin layer is formed on the surface of the sea urchin, and a bonding pad area is formed separately from a circuit forming area thereon. Since the conductive wiring metal layer is formed almost entirely on the top layer of the device, the reliability of the moisture resistance of the molded package device can be greatly improved without adding any additional manufacturing process.
第1@(a)ないし第1rM(e)ばこの発明の半導体
装置の一実施例を説明するための工程説明図、第2図は
従来のボンディングパッドの断面図である。
1.6・・・導体配線メタル、2・・・パシベーシコン
膜、3・・・ポリイミド系樹脂、4・・・窒化膜、5・
・・レジスト膜、6a・・ボンディングパッドエリア、
6b・・・回路形成エリア、7・・・ポンディングワイ
ヤ、8・・・コンタクトホトリソパターン。
第2図
手続補正書
昭和60年11月−7日1@(a) to 1rM(e) are process explanatory diagrams for explaining one embodiment of the semiconductor device of the present invention, and FIG. 2 is a sectional view of a conventional bonding pad. 1.6... Conductor wiring metal, 2... Passibasic film, 3... Polyimide resin, 4... Nitride film, 5...
...Resist film, 6a...Bonding pad area,
6b...Circuit formation area, 7...Bonding wire, 8...Contact photolithography pattern. Figure 2 Procedural amendments November-7, 1985
Claims (1)
膜を介して形成されたポリイミド系樹脂と、このポリイ
ミド系樹脂および上記パシベーション膜を通して上記第
1導体配線メタルを露出させるコンタクトホトリソパタ
ーンを通して上記第1の導体配線メタルと導通するとと
もに上記ポリイミド系樹脂上に回路形成エリアとボンデ
ィングパッドエリアと分離して形成された第2の導体配
線メタルと、上記ボンディングパッドエリアにボンディ
ングパッドされたボンディングワイヤとよりなる半導体
装置。A polyimide resin formed on a substrate via a first conductor wiring metal and a passivation film, and a contact photolithography pattern that exposes the first conductor wiring metal through the polyimide resin and the passivation film. A semiconductor comprising a second conductive wiring metal that is electrically connected to the conductive wiring metal and formed on the polyimide resin separately from a circuit formation area and a bonding pad area, and a bonding wire that is bonded to the bonding pad area. Device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59242385A JPS61121348A (en) | 1984-11-19 | 1984-11-19 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59242385A JPS61121348A (en) | 1984-11-19 | 1984-11-19 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61121348A true JPS61121348A (en) | 1986-06-09 |
Family
ID=17088372
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59242385A Pending JPS61121348A (en) | 1984-11-19 | 1984-11-19 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61121348A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5147822A (en) * | 1988-08-26 | 1992-09-15 | Semiconductor Energy Laboratory Co., Ltd. | Plasma processing method for improving a package of a semiconductor device |
JPH1126460A (en) * | 1997-07-03 | 1999-01-29 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and its manufacture |
US6756670B1 (en) | 1988-08-26 | 2004-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device and its manufacturing method |
-
1984
- 1984-11-19 JP JP59242385A patent/JPS61121348A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5147822A (en) * | 1988-08-26 | 1992-09-15 | Semiconductor Energy Laboratory Co., Ltd. | Plasma processing method for improving a package of a semiconductor device |
US6756670B1 (en) | 1988-08-26 | 2004-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device and its manufacturing method |
JPH1126460A (en) * | 1997-07-03 | 1999-01-29 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and its manufacture |
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