JPS6373641A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6373641A JPS6373641A JP21714886A JP21714886A JPS6373641A JP S6373641 A JPS6373641 A JP S6373641A JP 21714886 A JP21714886 A JP 21714886A JP 21714886 A JP21714886 A JP 21714886A JP S6373641 A JPS6373641 A JP S6373641A
- Authority
- JP
- Japan
- Prior art keywords
- film
- interconnection
- trimming
- insulating film
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000009966 trimming Methods 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 abstract description 14
- 239000010410 layer Substances 0.000 abstract description 9
- 239000000523 sample Substances 0.000 abstract description 7
- 239000011229 interlayer Substances 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 3
- 229920001721 polyimide Polymers 0.000 abstract description 3
- 239000004642 Polyimide Substances 0.000 abstract 1
- 239000011347 resin Substances 0.000 abstract 1
- 229920005989 resin Polymers 0.000 abstract 1
- 239000012528 membrane Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置1(IC,LSI)におけ
ろ配線トリミング技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring trimming technique in a semiconductor integrated circuit device 1 (IC, LSI).
IC等において、第4図に示すように半導体基体の表面
に異なる抵抗値をもつ複数の拡散抵抗R0R,R,・・
・・・・を形成し、このうち、不要とする抵抗、たとえ
ばRt Rs・・・・・・よりの引出し人形配線をトリ
ミング(部分的切除)することKより、必要とする抵抗
(R1)のみを残すトリミング技術が知られている。In ICs, etc., a plurality of diffused resistors R0R, R, . . . with different resistance values are placed on the surface of a semiconductor substrate as shown in Fig. 4.
..., and trimming (partially cutting) the drawer wires from unnecessary resistors, such as Rt and Rs...K, only the necessary resistor (R1) is formed. Trimming techniques that leave behind are known.
このトリミング手段としては、一般にプローブ検査で各
拡散抵抗の抵抗値を測定しながら、不要とする抵抗の引
出しA−13配線にプローブ針を介して過大電流を流す
方法があり、この他にレーザを用いて誘電膜上の銀合金
抵抗等をトリミングする方法(工業調査会発行電子材料
1985年5月p118〜124誘電体上の抵抗のレー
ザトリーミング)等がある。レーザトリーミング方式は
犬がかりの設備を必要とし、ここでは対象外とする。As a method for this trimming, there is generally a method in which the resistance value of each diffused resistor is measured by a probe test, and an excessive current is passed through the lead A-13 wiring of the unnecessary resistor through a probe needle. There is a method of trimming a silver alloy resistor, etc. on a dielectric film using a laser beam (laser trimming of a resistor on a dielectric material, published by Kogyo Kenkyukai, Electronic Materials, May 1985, p. 118-124). The laser trimming method requires dog-heavy equipment and is not considered here.
本発明では上記プローブ検査を利用するトリミング法を
例として説明する。In the present invention, a trimming method using the above-mentioned probe test will be explained as an example.
通常は第5図に示すように人形配線に接続される外部端
子(ポンディングパッド)IOKプローブ針11を接触
させ、AA配線の他端を接地電位とした状態で過電流を
流し、人石配線の一部位に形成した細幅部4に電流集中
させて溶断する。Normally, as shown in Figure 5, an external terminal (ponding pad) IOK probe needle 11 connected to the doll wiring is brought into contact with the doll wiring, and an overcurrent is applied with the other end of the AA wiring set to ground potential. A current is concentrated on the narrow part 4 formed at one part of the pipe to fuse it.
上記した溶断を利用したトリミング法を本発明者で検討
したところ下記の問題が生じることが判りた。すなわち
、第6図で示すように、過電流でAA配線3を溶断した
場合、配線の上を覆う保護絶縁膜6も同時に溶融飛散す
ることがあり、このように保護膜6が消失したり、薄く
なったりすることにより外部からの水分が人石配線を侵
し、ICの信頼性を大幅忙低下させることになった。When the present inventor investigated the above-mentioned trimming method using fusing, it was found that the following problems occurred. That is, as shown in FIG. 6, when the AA wiring 3 is fused due to overcurrent, the protective insulating film 6 covering the wiring may also be melted and scattered at the same time, causing the protective film 6 to disappear or As the wiring became thinner, moisture from the outside attacked the wiring, significantly reducing the reliability of the IC.
本発明は上記した問題を克服するためになされたもので
ある。The present invention has been made to overcome the above-mentioned problems.
本発明の目的とするところはトリミングによって保護絶
縁膜が損われることなく、半導体装置の信頼性を保持で
きる配線構造を提供することKある。An object of the present invention is to provide a wiring structure that can maintain reliability of a semiconductor device without damaging a protective insulating film due to trimming.
本発明の前記ならびKそのほかの目的と新規な特徴は本
明細書の記述ならびに添付図面からあきらかになろう。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体基体上に第1の絶縁膜を介し文人!配
線が形成され、この人2配線の一部ICトリミングのた
めの特定部位を有し、その上が第2の絶縁膜で覆われた
半導体基体上おいて、上記A4配線の特定部位の上に第
2の絶縁膜を介してA4膜又はその他の硬質な材料から
なる膜を蓋状に設げその上にさらに第3の絶縁膜が保護
膜として形成されているものである。In other words, the literati! A wiring is formed, a part of this 2 wiring has a specific part for IC trimming, and the top is covered with a second insulating film. A film made of A4 film or other hard material is provided as a lid via a second insulating film, and a third insulating film is further formed thereon as a protective film.
上記した硬質な材料からなる膜をトリミング部位に蓋状
に設けることにより、トリミングのための溶断時に保護
膜が破壊されることなく半導体装置の信頼性を確保でき
前記目的を達成できる。By providing a film made of the above-mentioned hard material in the shape of a lid at the trimming region, the reliability of the semiconductor device can be ensured without destroying the protective film during cutting for trimming, and the above object can be achieved.
第1図、第2図は本発明の一実施例を示すものであり、
ICの一部配線構造におけるトリミング部位を有する配
線パターン平面図とその断面図である。FIG. 1 and FIG. 2 show an embodiment of the present invention,
FIG. 2 is a plan view of a wiring pattern having a trimmed portion in a partial wiring structure of an IC and a cross-sectional view thereof.
1はSi半導体基体、2は半導体表面酸化膜(SiOz
膜)である。3はAノ配線、4はトリミングのための細
幅部である。5は層間絶縁膜で、たとえばCVD(気相
化学堆積)法によるPSG(リン・シリケート・ガラス
)又はSin、からなる。1 is a Si semiconductor substrate, 2 is a semiconductor surface oxide film (SiOz
membrane). 3 is the A wiring, and 4 is a narrow portion for trimming. Reference numeral 5 denotes an interlayer insulating film made of, for example, PSG (phosphorus silicate glass) or Sin formed by CVD (chemical vapor deposition).
7はA2よりなる蓋状膜で、上記細幅部4の上方を覆う
位置に設けられる。人石配線が2層構造の場合には、蓋
状膜は2層目(上層)のAA配線と同じ工程で形成され
る。蓋状膜7は下層のi配線3とは電気的九分離された
フローティングの状態にある。Reference numeral 7 denotes a lid-like membrane made of A2, which is provided at a position to cover the upper part of the narrow part 4. When the human stone wiring has a two-layer structure, the lid-like film is formed in the same process as the second layer (upper layer) AA wiring. The lid-like film 7 is in a floating state electrically isolated from the i-wire 3 in the lower layer.
6は最終保護用絶縁膜でたとえばポリイミド系樹脂など
の有機絶縁膜を厚く塗布し硬化させたものである。図示
されないがこの保護絶縁膜はチップ周辺で窓開されA!
配線延長部であるポンディングパッドを露出させる。Reference numeral 6 denotes a final protective insulating film, which is formed by applying a thick organic insulating film such as polyimide resin and curing it. Although not shown, this protective insulating film is opened around the chip A!
Expose the bonding pad, which is the wiring extension.
第3図はトリミング後の配線の形態を示すものである。FIG. 3 shows the form of the wiring after trimming.
すなわち、第5図を参照し、トリミングのための特定部
位(細幅部)4を有するAA配線3が接続されたポンデ
ィングパッドにプローブ針を接触させて過電流を流し、
上記特定部位(4)で配線を溶断する。人2配線3が溶
けると同時にその上の眉間膜5も破壊されて空隙部8が
生じる。このとぎ、上部に人!の蓋状部7が存在するこ
とKより、その上の保護膜6は破壊されることがない。That is, referring to FIG. 5, a probe needle is brought into contact with a bonding pad to which an AA wiring 3 having a specific portion (narrow portion) 4 for trimming is connected, and an overcurrent is applied.
The wiring is fused at the specific location (4). At the same time as the person 2 wiring 3 melts, the glabellar membrane 5 above it is also destroyed, creating a void 8. There's a person at the top of this sword! Because of the existence of the lid-shaped portion 7, the protective film 6 thereon is not destroyed.
溶けたA2の一部はAぷ残渣9として蓋状部7の下面に
付着する。A portion of the melted A2 adheres to the lower surface of the lid-shaped portion 7 as an Ap residue 9.
この実施例で述べたような配線構造においては1層目の
Ak配線を溶断したとき層間膜5は捜物な受けるがフロ
ーティング状態にある2層目の入l膜である蓋状部7に
よりブロックされるため表面の保護膜は影響を受けるこ
とがない。In the wiring structure as described in this embodiment, when the first-layer Ak wiring is blown, the interlayer film 5 will be caught, but it will be blocked by the lid-shaped part 7, which is the second-layer film, which is in a floating state. The protective film on the surface is not affected.
従来はICの信頼度が低下するためトリミングが難しか
ったが、上記したように配線の溶断によりて表面保護膜
が損われずトリミングが容易になり、高付加価値のIC
,LSIを実現できる。In the past, trimming was difficult because it lowered the reliability of the IC, but as mentioned above, trimming is now easier without damaging the surface protective film due to the wiring melting, making it possible to create high-value-added ICs.
, LSI can be realized.
以上本発明によってなされた発明を実施例にもとづき具
体的に説明したが、本発明は上記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present invention has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples and can be modified in various ways without departing from the gist thereof. do not have.
たとえば、トリミング部位の上部に設ける蓋状部はA2
膜以外の硬質の膜、たとえばSi窒化膜(S;、N4)
を使用しても同様の効果が期待できる。For example, the lid-shaped part provided above the trimming area is A2
Hard films other than the film, such as Si nitride film (S;, N4)
A similar effect can be expected by using .
本発明は高性能のLSI全般に適用できる。The present invention is applicable to all high performance LSIs.
第1図は本発明の一実施例を示すもので、半導体装置に
おけるトリミング部位を有する配線パターン平面図であ
る。
第2図は第1図におげろA−A視断面図である。
第3図はトリミング後の配線の断面図である。
第4図は複数の抵抗を選択的にトリミングする場合の回
路図である。
第5図はプローブ検査を利用するトリミングの一形態を
示す半導体チップの一部平面図である。
第6図はトリミング後の配線の形態を示す断面図である
。
1・・・Si基板、2・・・第1の絶縁膜(SiOt)
、3・・・第1層A2配線、4・・・トリミング部位(
細幅部)、訃・・第2の絶縁膜(層間膜、CVD−PS
G)、6・・・第3の絶縁膜(保護膜、ポリイミド樹脂
)、7・・・蓋状部(第2層A2膜)、8・・・空隙部
、9・・・A[残渣
代理人 弁理士 小 川 勝 男
1、、 、.7
・て=」
第 3 図
第 4 図
第 5 図
第 6 図FIG. 1 shows one embodiment of the present invention, and is a plan view of a wiring pattern having a trimming portion in a semiconductor device. FIG. 2 is a sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view of the wiring after trimming. FIG. 4 is a circuit diagram for selectively trimming a plurality of resistors. FIG. 5 is a partial plan view of a semiconductor chip showing one form of trimming using probe inspection. FIG. 6 is a sectional view showing the form of the wiring after trimming. 1... Si substrate, 2... First insulating film (SiOt)
, 3... First layer A2 wiring, 4... Trimming site (
narrow part), second insulating film (interlayer film, CVD-PS
G), 6... Third insulating film (protective film, polyimide resin), 7... Lid-like part (second layer A2 film), 8... Cavity part, 9... A [residue agent Person Patent Attorney Katsoo Ogawa 1. 7 ・te=” Figure 3 Figure 4 Figure 5 Figure 6
Claims (1)
層の配線層が形成され、この第1層の配線層の一部にト
リミングのための部位を有し、少なくとも上記第1層の
配線層上を覆う第2の絶縁膜を有し、少なくとも上記部
位の配線層の上に第2の絶縁膜を介して電気的にフロー
ティングな蓋状膜が設けられて、その蓋状膜上にさらに
第3の絶縁膜が形成されることを特徴とする半導体装置
。 2、上記蓋状膜は第2層の配線層と同一工程で形成され
ている特許請求の範囲第1項に記載の半導体装置。[Claims] 1. A first insulating film formed on a semiconductor substrate.
A wiring layer is formed, a portion of the first wiring layer has a trimming portion, a second insulating film covers at least the first wiring layer, and at least the first wiring layer has a trimming portion. A semiconductor characterized in that an electrically floating lid-like film is provided on the wiring layer of the part via a second insulating film, and a third insulating film is further formed on the lid-like film. Device. 2. The semiconductor device according to claim 1, wherein the lid-like film is formed in the same process as the second wiring layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21714886A JPS6373641A (en) | 1986-09-17 | 1986-09-17 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21714886A JPS6373641A (en) | 1986-09-17 | 1986-09-17 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6373641A true JPS6373641A (en) | 1988-04-04 |
Family
ID=16699607
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21714886A Pending JPS6373641A (en) | 1986-09-17 | 1986-09-17 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6373641A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01293535A (en) * | 1988-05-20 | 1989-11-27 | Rohm Co Ltd | Protective element for semiconductor device |
-
1986
- 1986-09-17 JP JP21714886A patent/JPS6373641A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01293535A (en) * | 1988-05-20 | 1989-11-27 | Rohm Co Ltd | Protective element for semiconductor device |
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