JPH01293535A - Protective element for semiconductor device - Google Patents
Protective element for semiconductor deviceInfo
- Publication number
- JPH01293535A JPH01293535A JP63124269A JP12426988A JPH01293535A JP H01293535 A JPH01293535 A JP H01293535A JP 63124269 A JP63124269 A JP 63124269A JP 12426988 A JP12426988 A JP 12426988A JP H01293535 A JPH01293535 A JP H01293535A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- wiring
- silicon chip
- metal wiring
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 230000001681 protective effect Effects 0.000 title description 2
- 239000002184 metal Substances 0.000 claims abstract description 35
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000011347 resin Substances 0.000 claims abstract description 22
- 229920005989 resin Polymers 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 230000015556 catabolic process Effects 0.000 claims abstract description 7
- 239000000155 melt Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000206 photolithography Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 239000004642 Polyimide Substances 0.000 abstract description 2
- 239000007769 metal material Substances 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 239000004411 aluminium Substances 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 150000003376 silicon Chemical class 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Fuses (AREA)
Abstract
Description
【発明の詳細な説明】
（ａｌ産業上の利用分野
この発明は、半導体装置を過電流から保護する半導体装
置用保護素子に関する。DETAILED DESCRIPTION OF THE INVENTION (Al Industrial Application Field) This invention relates to a protection element for a semiconductor device that protects the semiconductor device from overcurrent.
（ｂ）従来の技術
パワートランジスタ、パワーＩＣのような半導体装置の
出力によって負荷を駆動するとき、負荷が短絡したよう
なとき半導体装置に過電流が流れて破壊することがある
。これを防ぐために、対をなすリード間に半導体装置の
破壊電流よりわずかに低い電流によって瞬時に溶断する
金属線を設け、これを樹脂モールドした保護素子を用い
、半導体装置の出力端と負荷との間に接続できるように
したものは、本出願人が既に提案したように実公昭５８
−３８９８８号に示されている。(b) Prior Art When a load is driven by the output of a semiconductor device such as a power transistor or a power IC, an overcurrent may flow through the semiconductor device and destroy it if the load is short-circuited. In order to prevent this, a metal wire that instantly melts at a current slightly lower than the breakdown current of the semiconductor device is installed between the pair of leads, and a protective element made of resin molded metal wire is used to connect the output end of the semiconductor device and the load. As already proposed by the present applicant, a device that allows connection between
-38988.
第５図は既提案の保護素子を示し、対をなすリード１．
２にまたがって金属線３を設置し、この金属線３の外周
に柔軟性の樹脂６をコーティングしている。このコート
部６の周囲およびリード１．２の先端部の周囲を樹脂モ
ールドすることによってパフケージ４を形成している。FIG. 5 shows a previously proposed protection element, with paired leads 1.
A metal wire 3 is installed across 2, and the outer periphery of this metal wire 3 is coated with a flexible resin 6. The puff cage 4 is formed by resin molding around the coat portion 6 and around the tips of the leads 1.2.
ここで金属線３は金線、銀線、銅線または金メツキした
銀線などが用いられ、その長さおよび太さなどは溶断電
流によって定まる抵抗値にしたがって適宜決定されてい
る。すなわち半導体装置の破壊電流よりわずかに低い電
流が流れることによって瞬時（例えば０．５秒以内）に
溶断するように設計されている。金属線３が過電流によ
って溶断するとき、発熱によって金属線の一箇所が溶け
て切断されるが、その切断の直後、溶解した部分が表面
張力によって丸まろうとする。金属線３の外周にコーテ
ィングされている樹脂６は柔軟性であるため、金属線の
溶断時、溶断部分が容易に丸くなり、切断長が充分長く
なり、切断された金属線間で放電を開始するといった不
都合が生じない。Here, a gold wire, a silver wire, a copper wire, a gold-plated silver wire, or the like is used as the metal wire 3, and its length and thickness are appropriately determined according to the resistance value determined by the fusing current. That is, it is designed to melt instantly (for example, within 0.5 seconds) when a current slightly lower than the breakdown current of the semiconductor device flows. When the metal wire 3 is cut by overcurrent, one part of the metal wire melts and is cut due to heat generation, but immediately after the cut, the melted part tends to curl up due to surface tension. Since the resin 6 coated on the outer periphery of the metal wire 3 is flexible, when the metal wire is fused, the fused part easily becomes round, the cutting length becomes sufficiently long, and electric discharge starts between the cut metal wires. There will be no inconvenience caused.
（Ｃ）発明が解決しようとする課題
ところで第５図に示した従来の保護素子を製造するには
、例えば第６図に示すようにフープ材で連結されたリー
ドフレームの各リード間に金属線３を順次ワイヤボンデ
ィングし、デイスペンサなどによって各金属線の外周に
柔軟性樹脂を塗布し、さらに樹脂モールドすることによ
って製造することができる。(C) Problems to be Solved by the Invention In order to manufacture the conventional protection element shown in FIG. 5, for example, as shown in FIG. 3 are sequentially wire-bonded, a flexible resin is applied to the outer periphery of each metal wire using a dispenser or the like, and further resin molding is performed.
しかしながら金属線の外周に柔軟性樹脂を塗布する際に
金属線を破損させることなく、しかも必要な範囲にのみ
柔軟性樹脂を塗布しなければならない。このような作業
性の問題から、あまり小型の保護素子を製造することが
できなかった。However, when applying the flexible resin to the outer periphery of the metal wire, it is necessary to apply the flexible resin only to the necessary range without damaging the metal wire. Due to such workability problems, it has not been possible to manufacture very small protection elements.
この発明の目的は、より小型で容易に製造できるように
した半導体装置用保護素子を提供することにある。An object of the present invention is to provide a protection element for a semiconductor device that is smaller and easier to manufacture.
（ｄ）課題を解決するための手段
この発明の半導体装置用保護素子は、保護対象の半導体
装置の破壊電流よりわずかに低い電流が流れたとき瞬時
に溶断する金属配線と、この金属配線の両端に接続され
たワイヤボンディング用電極を、シリコンチップ上に形
成し、前記金属配線上のす（なくとも溶断箇所に柔軟性
樹脂を被覆するとともに、前記シリコンチップをリード
に対してワイヤボンディングし、パッケージ内にモール
ドしたことを特徴としている。(d) Means for Solving the Problems The protection element for a semiconductor device of the present invention includes a metal wiring that instantly melts when a current slightly lower than the breakdown current of the semiconductor device to be protected flows, and a metal wiring at both ends of the metal wiring. A wire bonding electrode connected to the lead is formed on the silicon chip, a flexible resin is coated on the metal wiring (at least the melted part), the silicon chip is wire bonded to the lead, and the package is packaged. It is characterized by being molded inside.
（ｅ）作用
この発明の半導体装置用保護素子においては、保護対象
の半導体装置の破壊電流よりわずかに低い電流が流れた
とき瞬時に溶断する金属配線がシリコンチップ上に形成
され、この金属配線上のすくなくとも溶断箇所に柔軟性
樹脂が被覆されている。また、シリコンチップ上の金属
配線の両端にはワイヤボンディング用の電極が形成され
ていて、このシリコンチップはリードに対してワイヤボ
ンディングされ、パッケージ内にモールドされている。(e) Function In the protection element for a semiconductor device of the present invention, a metal wiring is formed on the silicon chip, which instantly melts when a current slightly lower than the breakdown current of the semiconductor device to be protected flows. A flexible resin is coated at least at the fused portion. Furthermore, electrodes for wire bonding are formed at both ends of the metal wiring on the silicon chip, and this silicon chip is wire-bonded to the leads and molded within the package.
以上のように構成された半導体装置用保護素子の主要部
であるシリコンチップは、−ａ的な半導体素子の製造技
術であるウェハプロセスによって製造できるため、金属
線の外周に柔軟性樹脂を個々に塗布する必要がなく容易
に小型化することができる。The silicon chip, which is the main part of the protection element for a semiconductor device configured as described above, can be manufactured by a wafer process, which is a manufacturing technology for semiconductor devices. There is no need for coating and it can be easily miniaturized.
（ｆｌ実施例
第２図はこの発明の実施例である半導体装置用保護素子
におけるシリコンチップの構成を表す平面図である。図
において１３はＡ１やＡｕなどからなる金属配線であり
、その両端にワイヤボンディング用電極１３ａ、１３ｂ
を形成している。金属配！１３の中央部には後述するく
びれ部分１３Ｃを形成している。１６はこのくびれ部分
１３ｃの上部に被覆した柔軟性樹脂を示している。(fl Embodiment FIG. 2 is a plan view showing the structure of a silicon chip in a protection element for a semiconductor device which is an embodiment of the present invention. In the figure, 13 is a metal wiring made of A1, Au, etc. Wire bonding electrodes 13a, 13b
is formed. Metal arrangement! A constricted portion 13C, which will be described later, is formed in the center of the tube 13. Reference numeral 16 indicates a flexible resin coated on the upper part of this constricted portion 13c.
以上のように構成したことにより、金属配線１３に所定
電流が流れたとき、くびれ部分１３ｃが発熱し、溶断す
る。その際、少なくとも溶断箇所には柔軟性申脂が被覆
されているため、モールド樹脂に保持されることなく、
金属配置１３の自己加熱による溶融・切断が速やかに進
行する。With the above configuration, when a predetermined current flows through the metal wiring 13, the constricted portion 13c generates heat and fuses. At that time, at least the melted part is covered with flexible resin, so it is not held by the mold resin.
Melting and cutting of the metal arrangement 13 due to self-heating progresses rapidly.
以上に示した半導体装置用保護素子のシリコンチップは
次のようにして製造することができる。The silicon chip of the protection element for a semiconductor device described above can be manufactured as follows.
第４図はシリコンチップの主要部の断面構造を表す図で
あり、まずｎ型またはｐ型基板１７を酸化させることに
よってＳｉＯ□膜１８全１８に形成する。その表面にＡ
１などの配線金属材料を蒸着し第１図に示したようなパ
ターン化を行う。これは一般的なフォトリソグラフィに
よって形成することができる。その後、金属配線の施さ
れた基板表面の全面にポリイミドからなるコーティング
剤をスピンナで塗布し、フォトリソグラフィによって第
１図に示したよう溶断箇所を除く領域を除去する。なお
、必要に応じてＳｉＯ□、ＳｉＮ、。FIG. 4 is a diagram showing a cross-sectional structure of the main part of a silicon chip. First, an n-type or p-type substrate 17 is oxidized to form a SiO□ film 18 on the entire 18. FIG. A on the surface
A wiring metal material such as No. 1 is vapor-deposited and patterned as shown in FIG. This can be formed by general photolithography. Thereafter, a coating agent made of polyimide is applied with a spinner to the entire surface of the substrate on which the metal wiring is applied, and the area excluding the melted portion is removed by photolithography as shown in FIG. Note that SiO□, SiN, etc. are added as necessary.
、ｐｓＧ（リンガラス）などのパフシベーシッン膜を形
成する。このようにしてウェハープロセスを終了し、こ
れを分断して個々のシリコンチップを得る。, psG (phosphorus glass) or the like is formed. The wafer process is thus completed, and the wafer is divided into individual silicon chips.
第２図は第１図に示した金属配線のくびれ部分を詳細に
表す平面図である。ここで（びれの深さをａ、くびれの
幅をｂ、金属配線の線幅をＣとすれば、
ｂ≧４ａ
に溶断させることができる。FIG. 2 is a plan view showing in detail the constricted portion of the metal wiring shown in FIG. 1. Here, (if the depth of the constriction is a, the width of the constriction is b, and the line width of the metal wiring is C, then b≧4a).
第３図はこの発明の実施例である半導体装置用保護素子
の構成を示す図である０図において１１．１２はリード
であり、リード１２の先端部に前述のシリコンチップ１
０をマウントするとともにリード１１．１２にワイヤボ
ンディングしている。図中１９．２０はそのワイヤであ
る。このようにリード先端部にシリコンチップを取りつ
けた後、リード先端部全体を樹脂モールドすることによ
ってパッケージ化を行う０図中４はその樹脂モールド範
囲を示している。FIG. 3 is a diagram showing the structure of a protection element for a semiconductor device according to an embodiment of the present invention. In FIG.
0 is mounted and wire bonded to leads 11 and 12. In the figure, 19.20 is the wire. After attaching the silicon chip to the lead tip in this way, the entire lead tip is molded with resin to form a package. 4 in Figure 0 indicates the range of the resin mold.
（ｇ）発明の効果
以上のようにこの発明の半導体装置用保護素子によれば
、過電流が流れたとき溶断する金属配線をシリコンチッ
プ上に形成するとともに、その溶断箇所に柔軟性樹脂を
被覆することによって構成したため、金属配線および柔
軟性樹脂はいわゆるウェハープロセスによって形成する
ことができ、容易に小型化できる。しかも金属配線と柔
軟性樹脂の形状および寸法の再現性が高いため、均一な
特性を得ることができる。(g) Effects of the Invention As described above, according to the protection element for a semiconductor device of the present invention, a metal wiring that melts when an overcurrent flows is formed on a silicon chip, and the melting portion is covered with a flexible resin. Therefore, the metal wiring and the flexible resin can be formed by a so-called wafer process, and the size can be easily reduced. Moreover, since the shape and dimensions of the metal wiring and flexible resin have high reproducibility, uniform characteristics can be obtained.
第１図はこの発明の実施例である半導体装置用保護素子
におけるシリコンチップの構成を表す平面図である。第
２図は第１図における主要部の詳細図である。第３図は
同半導体装置用保護素子の構成を表す図である。第４図
は前記シリコンチップの主要部の構成を表す断面図であ
る。また、第５図は従来の半導体装置用保護素子の構成
を表す図であり、第６図はその製造工程の一部を表す図
である。
１０−シリコンチップ−
１１，１２＝Ｊ−ド、
１３−金属配線、
１３ａ、１３ｂ−ワイヤボンディング用電極、１６−柔
軟性樹脂。FIG. 1 is a plan view showing the structure of a silicon chip in a protection element for a semiconductor device according to an embodiment of the present invention. FIG. 2 is a detailed view of the main parts in FIG. 1. FIG. 3 is a diagram showing the configuration of the protection element for the semiconductor device. FIG. 4 is a sectional view showing the structure of the main part of the silicon chip. Further, FIG. 5 is a diagram showing the structure of a conventional protection element for a semiconductor device, and FIG. 6 is a diagram showing a part of its manufacturing process. 10-Silicon chip-11, 12=J-do, 13-Metal wiring, 13a, 13b-Wire bonding electrode, 16-Flexible resin.
Claims (1)
い電流が流れたとき瞬時に溶断する金属配線と、この金
属配線の両端に接続されたワイヤボンディング用電極を
、シリコンチップ上に形成し、前記金属配線上のすくな
くとも溶断箇所に柔軟性樹脂を被覆するとともに、前記
シリコンチップをリードに対してワイヤボンディングし
、パッケージ内にモールドしたことを特徴とする半導体
装置用保護素子。(1) A metal wiring that instantly melts when a current slightly lower than the breakdown current of the semiconductor device to be protected flows, and wire bonding electrodes connected to both ends of this metal wiring are formed on a silicon chip, A protection element for a semiconductor device, characterized in that at least a fusing point on the metal wiring is coated with a flexible resin, the silicon chip is wire-bonded to the leads, and the silicon chip is molded in a package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63124269A JP2839143B2 (en) | 1988-05-20 | 1988-05-20 | Protective element for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63124269A JP2839143B2 (en) | 1988-05-20 | 1988-05-20 | Protective element for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01293535A true JPH01293535A (en) | 1989-11-27 |
| JP2839143B2 JP2839143B2 (en) | 1998-12-16 |
Family
ID=14881157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63124269A Expired - Fee Related JP2839143B2 (en) | 1988-05-20 | 1988-05-20 | Protective element for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2839143B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011146539A (en) * | 2010-01-14 | 2011-07-28 | Denso Corp | Electronic device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5838988U (en) * | 1981-09-09 | 1983-03-14 | 昭和電線電纜株式会社 | connector |
| JPS5984574A (en) * | 1982-11-08 | 1984-05-16 | Matsushita Electronics Corp | Semiconductor device |
| JPS6373641A (en) * | 1986-09-17 | 1988-04-04 | Hitachi Ltd | Semiconductor device |
-
1988
- 1988-05-20 JP JP63124269A patent/JP2839143B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5838988U (en) * | 1981-09-09 | 1983-03-14 | 昭和電線電纜株式会社 | connector |
| JPS5984574A (en) * | 1982-11-08 | 1984-05-16 | Matsushita Electronics Corp | Semiconductor device |
| JPS6373641A (en) * | 1986-09-17 | 1988-04-04 | Hitachi Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011146539A (en) * | 2010-01-14 | 2011-07-28 | Denso Corp | Electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2839143B2 (en) | 1998-12-16 |
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