JPS6370615A - Differential type dynamic frequency divider - Google Patents

Abstract

PURPOSE:To obtain a dynamic frequency divider capable of deviding to broad band areas while withstanding power supply fluctuation by adopting a double loop constitution in which a differential amplifier is employed in place of an inverter part and two outputs are fed back respectively via a buffer and a switch. CONSTITUTION:The FET 3 of level shift circuit 4, 5 of a differential amplifier 1 is a constant current circuit and the output of a level shift diode becomes an inverted terminal output. The output of a circuit 4 is given to a switch SW1 and fed to a buffer 3. The output of a buffer 3 is returned to a FET 1 via a switch SW2. The output of a level shift diode is sent to a switch SW1' and the output of a switch SW1 is inputted to a buffer 2. The output of the buffer 2 is returned to the FET 2 of the amplifier 1. In applying the signal C of a frequency (f) to the switches SW1, SW1' and applying a signal, the inverse of C, to the switches SW2, SW2', then outputs having the frequency of f/2 opposed to each other are obtained from output terminals Q and Q.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figures 3 and 4) Problems to be Solved by the Invention Means for Solving the Problems (Figure 1) Effects Embodiment (Fig. 2) Effects of the invention [Overview] The inverter part of the dynamic frequency divider is a differential amplifier, and the two outputs are fed back via buffers and switches, respectively, in a double loop configuration, and the power supply margin and operation are This solves the problem of narrow margins and ensures stable operation.

[Industrial application field]

The present invention relates to a dynamic frequency divider, and particularly to a dynamic frequency divider that operates in a microwave band.

[Conventional technology]

In the field of high-speed frequency dividers in the microwave region, a dynamic frequency divider has been proposed, which requires only one logic gate to pass through, compared to a static frequency divider that uses conventional flip-flops. There is. (Mark Roch et al. I
E E E Journal of S.

lid -5tate C1rcuits SC-18
@, No. 3, pp. 369-376 rGaAs Digital
Dynamic IC's for Application
ation up to l0GH2), (Shigaki et al. 61st General National Conference of the Institute of Electronics and Communication Engineers, No. 813, pp. 3-250 “6GH2GaAs Dynamic Statec 1/
4 frequency divider") The basic circuit of this dynamic frequency divider is as shown in Figure 3 (al).
, consists of buffer BF, switches SW + and SW
2 is controlled on/off in reverse phase.

The dynamic frequency divider in FIG. 3(al) operates as follows.

■ That is, as shown in Fig. 3(b), switch SWl
, SW2 is supplied with an opposite phase clock C, υ to perform on/off operation (on when in H state). At this time, if a 1 level signal is input to the switch SW +, this signal becomes H until the output of the buffer BF at time To due to the switch SW + being turned on, but since the switch SW2 is off, no voltage is applied to the inverter INV. Not done. Therefore, when the switch SW + is on at time To, the output is H.
level.

■ At time T+, when switch SW2 is turned on and SWl is turned off, the output of buffer BF becomes H via this SW2.
is applied to the inverter INV, and an L level is output from the inverter INV. At this time, the switch SW +
Since it is off, the input H level of the high sofa BF up to that point is output.

■ At time T2, switch SW + is turned on, SW 2
When inverter INV turns off, the L level output of inverter INV is input to buffer BF, and the output becomes L level.

At this time, the switch SW2 is off, so the buffer BF is at the low level.
No level output is applied to the impurity IN.

■ When the switch SW2 is turned on and the switch SW1 is turned off at time T3, the output of the buffer BF is applied to the inverter INV via SW2, and an H level is output from the inverter INV. Since + is off, the output becomes the L level input to the buffer BF up to that point.

■ At time T4, switch SW + is turned on, SW 2
When inverter INV turns off, the H level output of inverter INV is input to buffer BF, and the output becomes H level. At this time, the switch SW2 is off, so the H level output of the buffer BF is not applied to the inverter INV.

In this way, the output of the frequency divider obtains a divided output having a frequency of 1/2 of the control clock of the switches SWI and SW2, as shown in FIG.

By the way, the dynamic frequency divider shown in FIG. 3(a) is specifically constructed as shown in FIG. 4.

In the circuit shown in FIG. 4, the parts corresponding to the inverter INV, buffer BF, switches SW1 and SW2 in FIG. It is provided.

The circuit in Figure 4 uses the inverter INV and all circuits are directly connected with DC, so the inverter INV output is connected to the FET switch SW+.
, buffer BF, , When the DC level returns to the inverter INV via the switch SW2 of the FET, it is necessary to match the level shift amount so that the inverter operates properly, so a level shift circuit is used.

[Problem that the invention seeks to solve]

By the way, in the circuit shown in FIG. 4, the inverter IN is used, and the source of the FET is fixed to the ground, so that the gate input DC level must be controlled with high precision. Therefore, this circuit is extremely sensitive to externally applied power supply and input offsets, and is vulnerable to these fluctuations. For example, when the input off point I- is changed, the operating frequency changes, and when the input power increases, the operating point changes, causing problems such as frequency division not being possible.

An object of the present invention is to provide a dynamic frequency divider that does not cause such problems and operates stably.

[Failure to solve the problem]

In order to achieve the above object, the present invention uses 1, a differential amplifier 1 as an inverter part, as shown in FIG.
Switch SW+, Sofa 3, Switch SW2, Frequency division loop of differential amplifier j, Switch SW+', Buffer 2
, switch SW2', and a differential amplifier with a frequency division loop of 10.

[Effect]

As a result, if an input signal C of frequency r is applied to the switches SWt and SW+', and the same input signal C is applied to the switches SW2 and SW2', the output terminals Q and
A frequency-divided output of (f/2) is obtained from Q.

Then, the signal output from the output terminal of differential amplifier 1 is transmitted to line 12.
, /2' and line β1, ff+'. When the input terminal is confused, even if the DC level fluctuates a little, there will be a difference!
! J] In the amplifier 1, the T)C levels of the forward and reverse signals similarly fluctuate relatively. A differential amplifier operates based on whether the input voltage is above or below the reference voltage, rather than the state of the power supply voltage, so it operates accurately even if the power supply voltage fluctuates.

〔Example〕

An embodiment of the present invention will be described with reference to FIG.

In FIG. 2, ζ and the same reference numerals as in FIG. 1 indicate the same parts.

The differential amplifier l is provided with a level shift circuit 4.5. FET3 of differential amplifier 1 is a constant current circuit.
As a result, the output of the FETI is input to the level shift circuit 4, and the output of the level shift diode becomes the invert terminal output in FIG. Then, the output of this level shift circuit 4 is sent via line 7!2 to the switch SW.
+, and the output of the switch S W 1 is input to the buffer 3 .

The output of this buffer 3 is then returned to the FETI of the differential amplifier 1 via the switch S W 2.

The output of FET2 of the differential amplifier 1 is input to the level shift circuit 5, the output of the level shift diode is transmitted to the switch SWI' via the line A12', and the output of the switch SWI is transmitted to the buffer 2. is input. The output of this buffer 2 is then returned to the FET 2 of the differential amplifier 1 via the switch SW2'.

Then, if a signal C with a frequency f is applied to the switches SW+ and SW+', and a signal C is applied to the switches SW2 and SW2', the output terminals Q and Q will output an output with a frequency of f/2 and opposite phases to each other. get.

Although the above description has been made with reference to an example using a GaAs substrate, the present invention is of course not limited to this, and other substrates, such as St, may be used.

When the circuit of the present invention is used, an IC using Au/WS + self-alignment gate process (gate length 1 μm
) simulation revealed that it is possible to divide the frequency by 8GllZ.

〔Effect of the invention〕

According to the present invention, since a differential amplifier is used instead of an inverter circuit, it is possible to obtain a dynamic frequency divider that is resistant to power supply fluctuations and capable of frequency division over a wide band.

[Brief explanation of the drawing]

FIG. 1 is a diagram of the principle of the present invention, FIG. 2 is an embodiment of the present invention, FIG. 3 is an explanatory diagram of a dynamic frequency divider, and FIG. 4 is a conventional dynamic frequency divider. 1-Differential amplifier 2.3-Buffer 4.5. −Level shift circuit

Claims (1)

[Claims] A differential dynamic frequency divider that controls on/off of a plurality of switching elements in opposite phases to each other and obtains an output from a buffer section, comprising: a differential amplifier (1); and the differential amplifier (1); A first buffer (2) is connected to the negative phase output portion of 1) via the switching section (SW_1'), and a first buffer (2) is connected to the in-phase output section of the differential amplifier (1) via the switching section (SW_1). 2 buffers (3) are connected, and the output side of the first buffer (2) is connected to a switching section (S
W_2) is connected to the positive input terminal of the differential amplifier (1), and the output side of the second buffer (3) is connected to the switching section (S
A differential dynamic frequency divider, characterized in that it is connected to the negative input terminal of the differential amplifier (1) via the differential amplifier (W_2').