JP2564915B2 - Divider circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a frequency dividing circuit configured by an integrated circuit having a GaAs Schottky barrier FET as a basic element.

[Prior Art] As a frequency dividing circuit for a GaAs IC used for applications requiring high-speed processing, the one shown in FIG. 3 is conventionally known. This circuit includes an inverter circuit in which an active load 12 is connected to the drain and a source is grounded, a first source follower type buffer 3 for amplifying the output of the inverter circuit, and a first input to the input terminal 10. A first switch FET4 for switching the output of the first source follower type buffer 3 according to an input signal, a second source follower type buffer 5 for amplifying the output of the first switch FET4, and an input to an input terminal 11. A second switch FET6 that switches the output of the second source follower type buffer 5 in response to a second input signal that is generated. The source of the second switch FET6 is connected to the gate of the inverter FET2. It has become a thing. In the figure, 8 and 9 are power supply voltages supplied to the above FETs.

In the divider circuit configured as above, input terminals 10,1
Switch FETs 4 and 6 with phase-shifted input signals input to 1
Switch sequentially, each source follower type buffer
While shifting the outputs of 4 and 6, the outputs are fed back to the inverter circuit to perform the frequency dividing operation.

[Problems to be Solved by the Invention] However, in the above-described frequency dividing circuit using the GaAs IC, the output impedance of the switch FET6 is higher than the input impedance of the inverter FET2. However, there is a drawback that the gate input amplitude cannot be taken sufficiently and the maximum operating frequency is lowered.

The present invention has been made in view of such problems, and it is possible to greatly improve the maximum operating frequency.
The purpose is to provide an AsIC divider circuit.

[Means for Solving the Problems] A GaAs IC divider circuit according to the present invention comprises an inverter circuit,
A first source follower type buffer circuit that amplifies the output of the inverter circuit, a first switch transistor that switches the output of the first source follower type buffer circuit by a first input signal, and the first switch A second source follower type buffer circuit for amplifying the output of the transistor, and a second switch transistor for switching the output of the second source follower type buffer circuit by a second input signal having a phase different from that of the first signal. And a third source follower type buffer circuit which amplifies the output of the second switch transistor and supplies the output to the inverter circuit, and divides the first and second input signals. Characterize.

[Operation] According to the present invention, the source of the second switch transistor is connected to the inverter via the third source follower type buffer circuit without being directly connected to the inverter circuit. Impedance conversion is performed by, and a sufficiently large input amplitude can be supplied to the gate of the FET that constitutes the inverter even in the high frequency region. As a result, the maximum operating frequency can be significantly increased.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a frequency dividing circuit according to the first embodiment of the present invention.

An inverter circuit is composed of the load resistor 1 and the inverter FET 2 whose drain is connected to the load resistor 1 and whose source is grounded. The output of this inverter circuit is connected to the drain of the first switch FET 4 via the first source follower type buffer 3. The gate of the first switch FET 4 is connected to the input terminal 10, and the source of the first switch FET 4 is connected to the drain of the second switch FET 6 via the second source follower type buffer 5. The gate of the second switch FET 6 is connected to the second input terminal 11. Then, in this circuit, the source of the second switch FET 6 is the newly provided third source follower type buffer 7
It is connected to the gate of the inverter FET2 via the. In the figure, 8 and 9 are power supply voltages supplied to the above FETs.

According to such a configuration, since the source follower type buffer 7 is interposed between the source of the switch FET6 and the gate of the inverter FET2, impedance conversion is performed by the source follower type buffer 7 and the inverter is used up to a high frequency range. A sufficiently large value can be obtained as the gate input amplitude of the FET2 for use. Therefore, the maximum operating frequency can be greatly improved as compared with the conventional case.

FIG. 2 is a circuit diagram showing a frequency dividing circuit according to the second embodiment of the present invention. In FIG. 2, the same parts as those in FIG. 1 are designated by the same reference numerals, and the description of the overlapping parts will be omitted.

The circuit of FIG. 2 differs from the circuit of the first embodiment in that the load of the inverter FET 2 is replaced by an active load instead of the load resistor 1.
12 is connected.

Also in this circuit, since the source follower type buffer circuit 7 is connected between the source of the switch FET 6 and the gate of the inverter FET 2, the same effect as that of the first embodiment can be obtained.

[Effects of the Invention] As described above, according to the present invention, in the frequency dividing circuit including the GaAs IC, the source of the second switch transistor,
Since the third source follower type buffer circuit is connected to the input of the inverter circuit, a sufficient input amplitude can be given to the inverter circuit even in a high frequency region, and the maximum operating frequency can be significantly increased.

[Brief description of drawings]

1 is a circuit diagram of a frequency dividing circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of a frequency dividing circuit according to a second embodiment of the present invention, and FIG. 3 is a conventional frequency dividing circuit. It is a circuit diagram of a circuit. 1; load resistance, 2; inverter FET, 3; first source follower type buffer, 4; first switch FET, 5; second source follower type buffer, 6; second switch FET, 7; Three
Source follower type buffer, 8,9; Power supply voltage, 10,11; Input terminal, 12; Active load

Claims (1)

(57) [Claims] 1. A frequency divider circuit using a gallium arsenide Schottky barrier field effect transistor as a basic element, and an inverter circuit and a first amplifier for amplifying the output of the inverter circuit.
Source follower type buffer circuit, a first switch transistor for switching the output of the first source follower type buffer circuit by a first input signal, and a second source for amplifying the output of the first switch transistor. A follower type buffer circuit, a second switch transistor for switching the output of the second source follower type buffer circuit by a second input signal having a phase different from that of the first signal, and an output of the second switch transistor And a third source follower type buffer circuit which amplifies the signal and supplies the output to the inverter circuit, and frequency-divides the first and second input signals.