JPS63151117A - Dynamic frequency divider - Google Patents

Abstract

PURPOSE:To reduce an influence of the variance of a supply voltage and the variation of elements, and to stabilize the operation by constituting an inverter part and a buffer part of differential amplifiers and constituting dual frequency division loops to extend a power margin and an operation margin. CONSTITUTION:The inverter part and the buffer part constituting a dynamic frequency divider consist of first and second differential amplifiers 11 and 12 respectively. In-phase and anti-phase outputs of the first differential amplifier 11 are connected to opposite input terminals of the second differential amplifier 12 through switches 13 and 14. In-phase and anti-phase outputs of the second differential amplifier 12 are connected to input terminals of the first differential amplifier 11 through switches 15 and 16 so that they are equal to differential inputs of the second differential amplifier 12. The loop gain is obtained in both of the inverter part and the buffer part and dual frequency division loops are constituted in this manner. Thus, the influence due to the variance of the supply voltage, the variation of elements, or the like is reduced.

Description

[Detailed Description of the Invention] [Summary] In a dynamic frequency divider using logic gates, the inverter section and buffer section are each configured with a differential amplifier, and the frequency division loop is doubled, thereby improving the power supply margin and The operation margin is expanded, and the effects of power supply voltage fluctuations and element variations are reduced to stabilize operation, and stable operation can be performed even with a low voltage power supply.

[Industrial application field]

The present invention relates to a dynamic frequency divider that performs stable frequency division operations in high frequency bands such as microwaves.

[Conventional technology]

A static type frequency divider using a flip-flop circuit has been known as a high-speed frequency divider used in the microwave region. In addition, there is a dynamic frequency divider that requires only one stage of logic gates to pass through compared to the static frequency divider, for example, as described by Mark Rosoch et al.: IE
EE Journal of Solid-5tate
C4rcuits, Volume 5C-18, No. 3, 369
~page 376, “GaAs Digital D
ynamic rc"5for Application
ion up to 10GHz”, Shigaki et al.
Institute of Electronics and Communication Engineers 61st Annual General Conference, No. 813, 3-2
50, "6 GHz GaAs Dynamic Static 1/4 Frequency Divider", etc.

The basic circuit of this dynamic frequency divider has the configuration shown in FIG. Basically, a switch 3 is interposed between the output of the imperc l and the input of the buffer 2, and a switch 4 is interposed between the output of the buffer 2 and the input of the inverter 1.

Note that the switches 3 and 4 described above are configured of switches that are alternately turned on and off, respectively, and an output that is 1/2 of the switching frequency is obtained.

FIG. 5 shows, for example, GaAs based on the basic configuration of FIG. 4.
FIG. 2 is an actual circuit configuration diagram manufactured using a monolithic IC composed of FETs. The output of the inverter 1 is supplied to the input of the buffer 2 via the level shift diode 5 and the FET switch 31, and the output of the buffer 2 is supplied to the input of the inverter 1 via the FET switch 4I.

And FET switch 3. ．． 4. An input clock C2C is supplied to the gates of the FETs constituting the FETs, respectively, and switching is performed. Although the output is not shown in the basic circuit of FIG. 4, it is actually taken out via the buffer 6.

The circuit shown in FIG. 5 uses an inverter and all stages are directly coupled in terms of DC, so that
FET switch 4. In the loop that returns to the inverter 1 through , it is necessary to match the amount of level shift with respect to the DC level so that the inverter 1 operates normally.

Since the source of the FET constituting the above-mentioned inverter 1 is fixed at the ground level, the DC level input to the gate of this FET via the FET switch 41 must be controlled with high precision with respect to the ground level. .

[Problem that the invention seeks to solve]

The conventional frequency divider with the above configuration is extremely sensitive to externally applied power supply voltage and input offset, and circuit operation is greatly affected by these fluctuations. There was a problem.

For example, when the input offset changes, the operating frequency changes, and when the input power increases, the operating point changes, causing problems such as frequency division not being possible. Furthermore, a sufficient loop gain cannot be obtained with a low voltage power supply, and it has been difficult to achieve stable operation with a low voltage power supply.

In the present invention, the inverter section and the buffer section of the dynamic frequency divider are each configured with a differential amplifier, and the frequency division loop is configured in a double configuration to reduce the effects of power supply voltage fluctuations and element variations, and to reduce the effects of power supply voltage fluctuations and element variations. The purpose of the present invention is to provide a dynamic frequency divider that can operate even when

Measures for Solving Problem c] As shown in the principle diagram in FIG. It consists of an amplifier 12, and the first
The in-phase and anti-phase outputs of the differential amplifiers 11 are respectively connected to the input terminals of the second differential amplifier 12 opposite to the first differential amplifier 11 via switches 13.14, and The in-phase and anti-phase outputs of the differential amplifiers 12 are connected to the input terminals of the first differential amplifier 11 via switches 15 and 16, respectively, so as to be the same as the differential inputs of the second differential amplifier 12. By connecting them, a loop gain is obtained in both the inverter section and the buffer section, and the frequency dividing loop has a double configuration, thereby reducing the effects caused by fluctuations in the power supply voltage, variations in elements, etc.

[For production]

By configuring both the inverter section and the buffer section with differential amplifiers, and by configuring the frequency division loop in a double configuration, sufficient loop gain can be obtained, allowing sufficiently stable operation even with a low voltage power supply. Since a circuit with a balanced circuit configuration is used, the effects caused by fluctuations in power supply voltage and variations in elements can be reduced.

〔Example〕

An embodiment according to the present invention will be described below.

FIG. 2 is a block diagram of a basic circuit showing an embodiment of the present invention, and shows the FET switch 13. ．． 14,. 15. ．．
16. are the switches 13 and 14 shown in FIG.
, 15, 16.

Further, a specific example of an actual circuit configuration is shown in FIG.

The inverter section constituting the dynamic frequency divider is composed of a first differential amplifier 11, and the buffer section is composed of a second differential amplifier 12. The common mode output of the first differential amplifier 11 is supplied to the drain or source terminal which is one terminal of the FET switch 13I, and is supplied to the second terminal via the source or drain terminal which is the other terminal of the FET switch 131. is supplied to the anti-phase input terminal of the differential amplifier 12. Moreover, the negative phase output of the first differential amplifier 11 is
FET switch 14. The drain or source terminal of this FET switch 14. through the source or drain terminal, which is the other terminal of
It is supplied to the common mode input terminal of the second differential amplifier 12.

The in-phase output from the second differential amplifier 12 is connected to the FET switch 15. is supplied to one drain or source terminal of the first
is supplied to the in-phase input terminal of the differential amplifier 11. Also,
The negative phase output from the second differential amplifier 12 is supplied to one drain or source terminal of the FET switch 161, and is supplied to the negative phase input terminal of the first differential amplifier 11 via the other source or drain terminal. is supplied to

In addition, the above FET switch 13. ．． 141 are each driven by the input clock C supplied to its gate, and the FET switch 15+.

16 are each driven by an input clock C supplied to its gate, and a frequency dividing operation is performed based on two input frequency divided waves having positive and opposite phases. Note that 171 to 174 shown in FIG. 3 are level shift diodes, respectively.

By having the above circuit configuration, the inverter section (first
differential amplifier 11) and a buffer section (second differential amplifier 1)
Since the loop gain of two stages can be obtained by 2), the gain per stage can be small. Therefore, the resistor 18. shown in the circuit of FIG. ~18. Since the value of can be small, the switching operation of the circuit becomes faster and high-speed operation can be realized.

〔Effect of the invention〕

According to the present invention described above, differential amplifiers each having a gain are used in the inverter section and the buffer section constituting the dynamic frequency divider, and the frequency division loop has a double configuration, so that fluctuations in the power supply voltage can be avoided. It is also highly resistant to the effects of element variations, and can operate stably even with low voltage power supplies.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a block diagram of the basic circuit of a dynamic frequency divider that is an embodiment of the present invention, Fig. 3 is a specific circuit block diagram of the embodiment, and Fig. 4 is FIG. 5 is a diagram showing a basic circuit configuration of a conventional dynamic frequency divider. FIG. 5 is a diagram showing a specific circuit configuration of a conventional example. 11... First differential amplifier, 12... Second differential amplifier, 13, 14, 15, 16... Switch, 1'3
,． 14. ．． 15. ．． 16. ...FET switch. Patent applicant: Fujitsu Honto Co., Ltd. Y3 ¥4
Figure 1: Mu 5 directions 7 ≧ I tai-kyu - Kio ≦ times g Figure 2 Figure 3

Claims (1)

[Claims] A first differential amplifier (11) constituting an inverter section;
and a second differential amplifier (12) constituting a buffer section, the in-phase and anti-phase outputs of the first differential amplifier are connected to the second differential amplifier through switches (13, 14), respectively. The in-phase and anti-phase outputs of the second differential amplifier are supplied to the input terminal opposite to that of the first differential amplifier, respectively, through switches (15, 16). A dynamic frequency divider, characterized in that the dynamic frequency divider performs a frequency division operation based on two input frequency divided waves having positive and opposite phases, which are supplied to in-phase and anti-phase input terminals of an amplifier.