JPS6370598A - Method of forming layer insulating film - Google Patents
Method of forming layer insulating filmInfo
- Publication number
- JPS6370598A JPS6370598A JP21512786A JP21512786A JPS6370598A JP S6370598 A JPS6370598 A JP S6370598A JP 21512786 A JP21512786 A JP 21512786A JP 21512786 A JP21512786 A JP 21512786A JP S6370598 A JPS6370598 A JP S6370598A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- hole
- interlayer insulating
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 11
- 239000004020 conductor Substances 0.000 claims description 24
- 239000011229 interlayer Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000010408 film Substances 0.000 description 34
- 239000010410 layer Substances 0.000 description 13
- 229920001721 polyimide Polymers 0.000 description 11
- 239000000758 substrate Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、基板上に抵抗やコンデンサなどの受動素子を
薄膜技術で形成し、さらにｒｃなどの能動素子を基板上
に取り付け、各素子間を導体配線で相互接続を行って形
成する混成集積回路の製造方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention forms passive elements such as resistors and capacitors on a substrate using thin film technology, and furthermore, attaches active elements such as RC on the substrate, and connects each element with The present invention relates to a method of manufacturing a hybrid integrated circuit in which circuits are interconnected using conductor wiring.
本発明は、集積回路で、上層導体膜を下層導体部に接触
させる層間絶縁膜の穴部の形成方法において、
成膜する層間絶縁膜の穴寸法を漸次縮小してゆるやかな
傾斜を呈する穴を形成することにより、上層導体膜の大
斜面に発生する段切れを防止することができるようにし
たものである。The present invention relates to a method for forming a hole in an interlayer insulating film in which an upper conductive film is brought into contact with a lower conductor in an integrated circuit. By forming this, it is possible to prevent step breaks that occur on large slopes of the upper layer conductor film.
従来、この種の混成集積回路は、層間絶８＆膜を用いて
セラミックス基板上に多層配線回路を形成する場合に、
基板表面の凸凹や絶縁膜のピンポール対策のために数μ
ｍの厚い絶縁層を必要とするので、層間接続用の穴が深
くなる。したがって、（色縁膜の膜厚と同じ程度の膜厚
の導体膜で段切れの発生を防止する必要がある。Conventionally, in this type of hybrid integrated circuit, when a multilayer wiring circuit is formed on a ceramic substrate using a layer interlayer 8& film,
A few microns to prevent irregularities on the substrate surface and pinholes in the insulating film.
Since a thick insulating layer of m is required, the hole for interlayer connection becomes deep. Therefore, it is necessary to prevent the occurrence of step breakage by using a conductor film having a thickness similar to that of the color border film.
このように、従来の混成集積回路では厚い導体膜を必要
とするので、成膜に時間がかがる上に、金などの貴金属
で導体配線をする場合には、さらにコスト面で不利にな
る欠点がある。In this way, conventional hybrid integrated circuits require a thick conductor film, which takes time to form, and is even more disadvantageous in terms of cost when conductor wiring is made of precious metals such as gold. There are drawbacks.
本発明は、このような欠点を除去するもので、導体膜の
厚さを特別に増さなくても、段切れが発生しない層間絶
縁膜の形成方法を提供することを目的とする。SUMMARY OF THE INVENTION The present invention aims to eliminate such drawbacks and to provide a method for forming an interlayer insulating film that does not cause breakage without particularly increasing the thickness of the conductor film.
本発明は、下層導体部上に複数層の層間絶縁膜を成膜し
、さらにこの膜上に上層導体膜を成膜する集積回路の製
造工程に含まれ、この下層導体部の所定部分を露出させ
る穴を有する層間絶縁膜を形成する工程において、層間
絶縁膜の穴の外周をこの膜が成膜される工程の前工程で
形成した層間絶縁膜の穴の外周の内側の領域に形成する
ことを特徴とする。The present invention is included in an integrated circuit manufacturing process in which a plurality of interlayer insulating films are formed on a lower conductor part, and an upper conductor film is further formed on this film, and a predetermined portion of the lower conductor part is exposed. In the step of forming an interlayer insulating film having a hole, the outer periphery of the hole in the interlayer insulating film is formed in a region inside the outer periphery of the hole in the interlayer insulating film formed in the step before the step in which this film is formed. It is characterized by
複数層の層間絶縁膜で上層導体膜と下層導体部とは絶縁
される。層間絶縁膜の一部に設けられた穴部で上Ｎ導体
膜は下層導体部上に直接成膜され導通ずるが、この上層
導体膜は穴の沿面で段切れが発生しやすい。本発明の製
造方法で形成された穴は、ゆるやかな勾配を呈した沿面
を有し、特にポリイミド膜を利用したときは、そのプレ
ーナー化効果により、その勾配はさらにゆるやかになり
、過分の厚さの上層導体膜を成膜しなくても段切れが発
生しない。The upper conductor film and the lower conductor portion are insulated by a plurality of interlayer insulating films. Although the upper N conductor film is formed directly on the lower conductor portion and conducts through the hole provided in a part of the interlayer insulating film, the upper conductor film is likely to be broken along the surface of the hole. The hole formed by the manufacturing method of the present invention has a creeping surface exhibiting a gentle slope, and especially when a polyimide film is used, the slope becomes even gentler due to its planarization effect, and excessive thickness Even if the upper conductor film is not formed, no step breaks will occur.
以下、本発明実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１図ないし第４図は本発明の製造方法の工程の進捗を
示す仕掛品の層間配線接続用穴の部分の断面図である。1 to 4 are cross-sectional views of the interlayer wiring connection hole portion of the work-in-process product showing the progress of the manufacturing method of the present invention.
まず、第一工程で、９６％アルミナ・セラミックスの基
板１上に抵抗体膜２および下層導体膜３をマグネトロン
スパッタ法で順次成膜する。この基板１に公知のホトレ
ジスト技術を用いて膜回路パターンを形成する。抵抗体
および導体膜厚は合計８０００人である。次に、抵抗体
安定化熱処理（３５０’ｃ、１時間）を行って第１図に
示す形態を形成する。First, in a first step, a resistor film 2 and a lower conductor film 3 are sequentially formed on a substrate 1 made of 96% alumina ceramics by magnetron sputtering. A film circuit pattern is formed on this substrate 1 using a known photoresist technique. The total thickness of the resistor and conductor is 8,000. Next, a resistor stabilization heat treatment (350'c, 1 hour) is performed to form the configuration shown in FIG.
ひきつづき、第二工程で、１００ Ｃｐのポリイミド膜
４をスピン・オン法で２００Ｏｒｐｍ 、６０秒の条件
で塗布する。１３５℃で３０分間乾燥した後にポジ型ホ
トレジストを塗布し、露光後に配線接続用の穴５をあけ
る部分のホトレジストの現像とポリイミド膜４のエツチ
ングをポジレジストの現像液で連続して行う。さらに、
３００℃で６０分間の乾燥を行って、第２図に示す形態
に形成する。Subsequently, in a second step, a 100 Cp polyimide film 4 is applied by a spin-on method at 200 rpm for 60 seconds. After drying at 135° C. for 30 minutes, a positive type photoresist is applied, and after exposure, the development of the photoresist at the portion where the wiring connection hole 5 is to be made and the etching of the polyimide film 4 are successively performed using a positive resist developer. moreover,
Drying is performed at 300° C. for 60 minutes to form the shape shown in FIG.
ひきつづき、第三工程で、第二工程と同様に、同じ条件
でポリイミド膜６を塗布して、−ｉ目のポリイミド膜４
の穴より径の小さい穴７を第３図に示すように形成する
。さらに、第二工程でポリイミド膜８を形成して、第２
層目の穴径よりさらに径の小さい穴９を第４図に示すよ
うに形成し、絶縁膜上に上層導体膜１０をマグネトロン
スパッタ法で９０００人の厚さで形成して、公知のホト
レジスト法で上層４体回路を第４図に示すように形成す
る。Continuously, in the third step, the polyimide film 6 is applied under the same conditions as in the second step, and the −i-th polyimide film 4 is coated.
A hole 7 having a smaller diameter than the hole 7 is formed as shown in FIG. Furthermore, in a second step, a polyimide film 8 is formed, and a second
A hole 9 with a smaller diameter than that of the layer is formed as shown in FIG. 4, and an upper conductor film 10 is formed on the insulating film to a thickness of 9,000 mm using a magnetron sputtering method, using a known photoresist method. Then, an upper layer four-body circuit is formed as shown in FIG.
次に、下層に形成した抵抗体をレーザートリミング法で
切削して、抵抗値を微調整する。このようにして製作さ
れた抵抗回路素子にダイオードやトランジスタまたは受
動素子をリフロー法で半田接続し、端子を接続して外装
樹脂で被覆し、混成集積回路を得る。Next, the resistor formed in the lower layer is cut using a laser trimming method to finely adjust the resistance value. A diode, a transistor, or a passive element is soldered to the resistive circuit element thus manufactured by a reflow method, terminals are connected, and the resistive circuit element is covered with an exterior resin to obtain a hybrid integrated circuit.
また、この実施例では同じ膜厚のポリイミド膜を積層し
たが、それぞれの膜の膜厚を変えることにより傾斜のゆ
るやかな穴を形成しても、本発明を実施することができ
る。Further, in this embodiment, polyimide films of the same thickness are laminated, but the present invention can also be practiced by forming holes with a gentle slope by changing the thickness of each film.
本発明は、以上説明したように、漸次径の小さい穴を形
成した有機膜を積層して傾斜のゆるやがな穴を形成し、
さらにこの穴の傾斜はポリイミド自体のプレーナー化効
果によりよりゆるやかになり、したがってより薄い上Ｎ
導体膜を形成しても段切れの発生しにくい穴を形成する
ことができる効果がある。As explained above, the present invention forms gently sloping holes by laminating organic films in which holes with gradually smaller diameters are formed.
Furthermore, the slope of this hole is more gradual due to the planarization effect of the polyimide itself, and therefore the thinner upper N
Even if a conductive film is formed, it is possible to form a hole in which breakage is unlikely to occur.
【図面の簡単な説明】
第１図ないし第４図は本発明の製造工程順の層間配線接
続用穴の部分の断面図。
１・・・基板、２・・・抵抗体膜、３・・・下Ｊ！！導
体膜、４・・・ポリイミド膜（第１層目）、５・・・穴
（第１層目）、６・・・ポリイミド膜（第２層目）、７
・・・穴（第２層目）、８・・・ポリイミド膜（第３Ｎ
目）、９・・・穴（第３層目）、１０・・・上層導体膜
。
特許出願人 日本電気株式会社 −
代理人 弁理士 井 出 直 孝゛ ′第一工程時の
形態
第１図
第二工程時の形態
第２図BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 4 are cross-sectional views of interlayer wiring connection holes in the order of manufacturing steps of the present invention. 1...Substrate, 2...Resistor film, 3...Bottom J! ! Conductor film, 4... Polyimide film (first layer), 5... Hole (first layer), 6... Polyimide film (second layer), 7
...hole (second layer), 8...polyimide film (third layer)
), 9... hole (third layer), 10... upper layer conductor film. Patent Applicant: NEC Corporation − Agent: Patent Attorney Nao Takashi Ide
Claims (1)
らにこの膜上に上層導体膜を成膜する集積回路の製造工
程に含まれ、この下層導体部の所定部分を露出させる穴
を有する層間絶縁膜を形成する工程において、 層間絶縁膜の穴の外周をこの膜が成膜される工程の前工
程で形成した層間絶縁膜の穴の外周の内側の領域に形成
する ことを特徴とする層間絶縁膜の形成方法。(1) Included in the integrated circuit manufacturing process in which multiple layers of interlayer insulating film are formed on a lower conductor part, and an upper conductor film is further formed on this film, and a predetermined portion of this lower conductor part is exposed. In the step of forming an interlayer insulating film having a hole, the outer periphery of the hole in the interlayer insulating film is formed in a region inside the outer periphery of the hole in the interlayer insulating film formed in the step before the step in which this film is formed. Characteristic method for forming an interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21512786A JPS6370598A (en) | 1986-09-12 | 1986-09-12 | Method of forming layer insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21512786A JPS6370598A (en) | 1986-09-12 | 1986-09-12 | Method of forming layer insulating film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6370598A true JPS6370598A (en) | 1988-03-30 |
Family
ID=16667173
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21512786A Pending JPS6370598A (en) | 1986-09-12 | 1986-09-12 | Method of forming layer insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6370598A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005317932A (en) * | 2004-03-29 | 2005-11-10 | Yamaha Corp | Semiconductor device and its manufacturing method |
| US7728423B2 (en) | 2004-03-29 | 2010-06-01 | Yamaha Corporation | Semiconductor device having step-wise connection structures for thin film elements |
-
1986
- 1986-09-12 JP JP21512786A patent/JPS6370598A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005317932A (en) * | 2004-03-29 | 2005-11-10 | Yamaha Corp | Semiconductor device and its manufacturing method |
| US7728423B2 (en) | 2004-03-29 | 2010-06-01 | Yamaha Corporation | Semiconductor device having step-wise connection structures for thin film elements |
| US8008127B2 (en) | 2004-03-29 | 2011-08-30 | Yamaha Corporation | Method of fabricating an integrated circuit having a multi-layer structure with a seal ring |
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