JPH08288102A - Electronic component and its manufacture - Google Patents

Electronic component and its manufacture

Info

Publication number
JPH08288102A
JPH08288102A JP7111217A JP11121795A JPH08288102A JP H08288102 A JPH08288102 A JP H08288102A JP 7111217 A JP7111217 A JP 7111217A JP 11121795 A JP11121795 A JP 11121795A JP H08288102 A JPH08288102 A JP H08288102A
Authority
JP
Japan
Prior art keywords
electrodes
film
electrode
substrate
edge part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP7111217A
Other languages
Japanese (ja)
Inventor
Yukihiro Koyama
幸宏 小山
Kazuyuki Osuga
一行 大須賀
Hiroaki Abe
宏昭 阿部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP7111217A priority Critical patent/JPH08288102A/en
Publication of JPH08288102A publication Critical patent/JPH08288102A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE: To provide an electronic component and its manufacturing method with which edge part electrodes can be formed, regardless of a manufacturing process and functional element material, the fine pattern edge part electrodes and the multilayer edge part electrodes can be realized easily, the high precision, the high reliability, the size reduction, the low profile, the cost reduction, etc., can be achieved and, further, the multilayer structure of electrodes corresponding to various purposes can be realized easily. CONSTITUTION: Edge part electrodes 5 which are connected to extraction electrodes 3 or to internal electrodes are formed on the edge part of a chip or a substrate 1 which has functional elements at least either in the interior or on the surface. Photoresist layers are formed on the areas on the edge part of the chip or the substrate 1 except the areas for the extraction electrodes 3 or the internal electrodes by an intaglio printing method, a screen printing method or a photolithography method. Then conducting material is deposited by a vacuum film forming method and, after that, the photoresist layers are removed to form the edge part electrodes 5.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、絶縁体(磁性体あるい
は誘電体として使用される場合を含む)またはプリント
基板からなるチップの内部もしくは表面にコンデンサ、
インダクタあるいは抵抗体もしくはこれらの複合体等、
一種以上の機能素子を形成したチップの端部に端部電極
を設けた電子部品とその製造方法に係り、特に端部電極
とその形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor formed inside or on the surface of a chip made of an insulating material (including a magnetic material or a dielectric material) or a printed board.
Inductor or resistor or composite of these,
The present invention relates to an electronic component in which an end electrode is provided at an end of a chip on which one or more functional elements are formed, and a manufacturing method thereof, and more particularly, to an end electrode and a forming method thereof.

【0002】[0002]

【従来の技術】チップの端面に電極を形成する方法を、
複数の端部電極を有する抵抗ネットワークについて説明
すると、下記の3つの例がある。 (例1)同一絶縁基板表面に、上部電極となる銀、銀/
パラジウム、金等の導体ペーストと、抵抗体となる酸化
ルテニウム等の抵抗ペーストと、保護膜となるガラスペ
ーストとを、スクリーン印刷法により形成した後焼成す
る一連の厚膜プロセスにより、上部電極と、複数の抵抗
体と、保護膜とを形成する。その後、凸形状のチップ端
部に、銀、銀/パラジウム、金等からなる導体ペースト
をディップや浸漬法等で付着させ、乾燥した後、焼成す
ることにより、端部電極を形成する。 (例2)アルミナ等の絶縁基板に、端部電極となるスル
ーホールを設けておき、導体ペーストをスルーホール部
に印刷すると当時にスルーホール部下面から導体ペース
トを吸引することにより、スルーホール全面に導体ペー
ストを回り込ませ、その後、乾燥、焼成する。そして、
前記スルーホール部の導体層に端部が重なるように抵抗
ペーストを印刷し、その上にガラスペーストを印刷して
焼成する一連の厚膜プロセスにより、複数の抵抗体と保
護膜を形成する。その後、予め基板上に形成されている
スナップ溝にそって分割するか、あるいはダイシングや
レーザスクライブによって分割することにより、スルー
ホール部を2分割し、凹形状の端部電極を形成する。 (例3)同一絶縁基板上に、厚膜プロセスにより上部電
極、複数の抵抗体、保護膜を形成し、予め基板上に形成
されているスナップ溝やダイシング、レーザスクライブ
により基板をチップ状に分割する。必要であればエッジ
部の面取りをバレルにより行う場合もある。その後、チ
ップの端面に凹版印刷やスクリーン印刷により直接導体
ペーストを転写、印刷し、一連の厚膜プロセスを経て端
部電極を形成する。
2. Description of the Related Art A method of forming electrodes on the end surface of a chip is
To describe a resistance network having a plurality of end electrodes, there are the following three examples. (Example 1) On the surface of the same insulating substrate, silver to be the upper electrode, silver /
Palladium, a conductor paste such as gold, a resistance paste such as ruthenium oxide to be a resistor, and a glass paste to be a protective film, by a series of thick film process of firing by screen printing, the upper electrode, A plurality of resistors and a protective film are formed. After that, a conductor paste made of silver, silver / palladium, gold, or the like is attached to the end of the convex chip by dipping, dipping, or the like, dried, and then baked to form an end electrode. (Example 2) A through hole serving as an end electrode is provided on an insulating substrate made of alumina or the like, and when the conductor paste is printed on the through hole portion, the conductor paste is sucked from the lower surface of the through hole at that time so that the entire through hole is formed. The conductive paste is wrapped around, then dried and fired. And
A plurality of resistors and a protective film are formed by a series of thick film processes in which a resistance paste is printed on the conductor layer of the through hole portion so that the end portions overlap each other, and a glass paste is printed on the resistance paste and baked. After that, the through hole portion is divided into two by dividing along the snap groove formed on the substrate in advance or by dicing or laser scribing to form a concave end electrode. (Example 3) An upper electrode, a plurality of resistors and a protective film are formed on the same insulating substrate by a thick film process, and the substrate is divided into chips by snap grooves, dicing, and laser scribing which are formed on the substrate in advance. To do. If necessary, the edge may be chamfered by a barrel. After that, the conductor paste is directly transferred and printed on the end surface of the chip by intaglio printing or screen printing, and an end electrode is formed through a series of thick film processes.

【0003】以上の方法により形成された端部電極には
ニッケルと錫のメッキや半田メッキが施され、面実装型
の抵抗ネットワークが作製される。コンデンサ(C)や
抵抗体(R)以外に、インダクタ(L)、またはこれら
の2種以上のものを厚膜プロセスにより積層することに
より機能素子を構成した面実装型電子部品においても、
同様の方法により端部電極が形成されている。
The end electrodes formed by the above method are plated with nickel and tin or solder to form a surface mount resistance network. In addition to the capacitor (C) and the resistor (R), an inductor (L) or a surface mount electronic component in which a functional element is formed by laminating two or more of these by a thick film process,
The end electrodes are formed by the same method.

【0004】[0004]

【発明が解決しようとする課題】上述したように、従来
は端部電極を厚膜プロセスにより形成しているので、次
のような問題点がある。 (1)蒸着、スパッタリング、イオンプレーティング、
CVDといった真空成膜法(薄膜プロセス)によって抵
抗体、コンデンサ、インダクタ等の受動素子を形成する
場合、端部電極の焼成条件(空気中、600℃〜900
℃)では真空成膜法で形成した膜の酸化や組成物質の蒸
発等の問題があり、薄膜と厚膜プロセスの併用は困難で
ある。このため、薄膜プロセスによる場合の優位性、す
なわち、薄膜の電気的特性、信頼性、安定性における優
位性や、抵抗値の面内分布等のプロセス上の優位性が得
られない。また、スクリーン印刷法等の厚膜プロセスで
は、パターン解像度と位置精度に限界があり、微細パタ
ーン形成や高密度化が可能なフォトリソ技術による小型
化、低背化の優位性が生かせず、市場における高精度化
や高信頼性の要求、並びに低価格化の要求に対応できな
い。 (2)保護膜にポリイミド、エポキシ、フェノール等の
樹脂を使用する場合、端部電極を厚膜プロセスによって
形成しようとすると、樹脂の耐熱性に問題があり、さら
に低融点の金属または可溶体等の厚膜プロセスによる端
部電極形成時の熱履歴に耐性を持たない材料を用いる場
合、樹脂の場合と同様に耐熱性に問題がある。 (3)凹凸形状の端部電極や凹版またはスクリーン印刷
による端部電極の形成には、絶縁基板の加工精度や転
写、印刷の限界があるため、狭ピッチの端部電極形成が
困難である。 (4)端部電極の形成に導体ペーストを用いた場合、ペ
ーストの選択枝が少なく、また、端部電極の多層構造が
とれないといった問題があり、被着基板との密着性、す
なわち端部電極と取り出し電極あるいは内部電極との接
合部のオーミックコンタクトが得にくいとか、材料間の
拡散防止の役目をもつバリヤ層の形成等の対策がとれな
かった。 (5)ガラスエポキシ、フェノール等の基板上に銅のメ
ッキ膜や圧延箔を配線加工したプリント基板は、耐熱温
度が低いため、厚膜プロセスによって基板を直接形成す
ることは困難であるため、リードフレーム等の外部取り
出し用材料を使用しなければ、面実装型の形状にはでき
ないという問題がある。
As described above, since the end electrodes are conventionally formed by the thick film process, there are the following problems. (1) Vapor deposition, sputtering, ion plating,
When forming passive elements such as resistors, capacitors, and inductors by a vacuum film forming method (thin film process) such as CVD, firing conditions for end electrodes (in air, 600 ° C. to 900 ° C.)
At (° C.), there are problems such as oxidation of the film formed by the vacuum film formation method and evaporation of the composition material, and it is difficult to use both thin and thick film processes together. For this reason, it is impossible to obtain superiority in the case of the thin film process, that is, superiority in electrical characteristics, reliability, stability of the thin film and in-plane distribution of resistance value. Also, in thick film processes such as screen printing, there is a limit in pattern resolution and positional accuracy, and the advantage of miniaturization and low profile by the photolithography technology that enables fine pattern formation and high density cannot be used We cannot meet the demands for higher precision, higher reliability, and lower prices. (2) When a resin such as polyimide, epoxy, or phenol is used for the protective film, if the end electrodes are formed by a thick film process, there is a problem in the heat resistance of the resin, and a low melting point metal or fusible material is used. When a material having no resistance to the heat history at the time of forming the end electrodes by the thick film process is used, there is a problem in heat resistance as in the case of the resin. (3) It is difficult to form an end electrode with a narrow pitch in forming an end electrode having an uneven shape or an intaglio plate or an end electrode by screen printing, because there are limitations in processing accuracy of an insulating substrate, transfer, and printing. (4) When a conductor paste is used to form the end electrodes, there are problems that there are few selection options of the paste and that the end electrodes cannot have a multilayer structure, and the adhesion to the adherend substrate, that is, the end portion However, it is difficult to obtain ohmic contact at the junction between the electrode and the lead-out electrode or the internal electrode, and it is impossible to take measures such as forming a barrier layer having a role of preventing diffusion between materials. (5) Since a printed circuit board in which a copper plating film or a rolled foil is processed on a substrate made of glass epoxy, phenol, etc. has a low heat resistance temperature, it is difficult to directly form the substrate by a thick film process. There is a problem that the surface mounting type cannot be formed unless a material for taking out such as a frame is used.

【0005】本発明は、上記した問題点に鑑み、製造プ
ロセスや機能素子構成材料の如何を問わず端部電極の形
成が可能であり、端部電極の微細パターン化や多層化が
容易となり、高精度化、高信頼性、小型化、低背化、低
価格化等が達成でき、さらに種々の目的に応じた電極の
多層化が容易に行える電子部品とその製造方法を提供す
ることを目的とする。
In view of the above-mentioned problems, the present invention can form the end electrodes regardless of the manufacturing process or the material for forming the functional element, which facilitates fine patterning and multi-layering of the end electrodes. An object of the present invention is to provide an electronic component and a manufacturing method thereof, which can achieve high precision, high reliability, downsizing, low profile, low price, etc., and can easily form a multi-layered electrode according to various purposes. And

【0006】[0006]

【課題を解決するための手段】本発明の電子部品は、内
部または表面の少なくともいずれかに機能素子を形成し
たチップまたは基板の端部に、取り出し電極または内部
電極に接続された端部電極を形成する電子部品におい
て、前記端部電極が、真空成膜法により形成されたもの
でなることを特徴とする。
In the electronic component of the present invention, an end electrode connected to a take-out electrode or an internal electrode is provided at the end of a chip or substrate having a functional element formed on at least one of the inside and the surface thereof. The electronic component to be formed is characterized in that the end electrode is formed by a vacuum film forming method.

【0007】また、本発明の電子部品の製造方法は、内
部または表面の少なくともいずれかに機能素子を形成し
たチップまたは基板の端部に、取り出し電極または内部
電極に接続された端部電極を形成する電子部品を製造す
る方法において、前記チップまたは基板の端面における
取り出し電極または内部電極を除くエリアに、凹版印刷
法、スクリーン印刷法またはフォトリソグラフィにより
リフトオフレジストを形成した後、真空成膜法により導
電体を着膜し、その後リフトオフレジストを除去するこ
とにより、端部電極を形成することを特徴とする。
Further, according to the method of manufacturing an electronic component of the present invention, a lead-out electrode or an end electrode connected to the internal electrode is formed at the end of a chip or substrate having a functional element formed on at least one of the inside and the surface thereof. In the method of manufacturing an electronic component, a lift-off resist is formed by an intaglio printing method, a screen printing method or photolithography in an area excluding the extraction electrode or the internal electrode on the end surface of the chip or the substrate, and then conductive by a vacuum film forming method. The end electrodes are formed by depositing the body and then removing the lift-off resist.

【0008】[0008]

【作用】本発明においては、真空成膜法により端部電極
を形成するものであり、また真空成膜を行うに当たり、
リフトオフ法を用いる。リフトオフレジストの形成は、
凹版印刷法、スクリーン印刷法またはフォトリソグラフ
ィのいずれの方法による場合においても、低温において
形成できる。また、その後の導体膜の形成も真空成膜法
によるため、端部電極形成の全工程について低温で形成
できる。従って、製造プロセスや材料の制約が緩和され
る。また、多層膜用成膜装置を使用することにより、多
層の端部電極構造が採用可能となる。また、真空成膜法
により成膜する場合には、厚膜プロセスによる場合にお
けるバレルメッキ時の耐メッキ性の問題や取り出し電極
あるいは内部電極との接合部とのオーミックコンタクト
の問題を解決できる。また、リフトオフレジストの形成
方法は、チップサイズ、チップ形状、または形成する端
部電極ピッチに応じて、シリコン樹脂等で型取りされた
凹版にレジストを埋込み転写する方法や、スクリーン印
刷による方法、さらに微細パターンの形成に効果を発揮
するフォトレジストとフォトリソ技術による形成方法の
いすれかが選択される。
In the present invention, the end electrodes are formed by the vacuum film formation method, and in performing the vacuum film formation,
The lift-off method is used. The lift-off resist is formed by
It can be formed at a low temperature by any of the intaglio printing method, the screen printing method and the photolithography method. Further, since the subsequent conductor film is also formed by the vacuum film forming method, it can be formed at a low temperature in all the steps of forming the end electrodes. Therefore, restrictions on manufacturing processes and materials are alleviated. Further, by using the film forming apparatus for a multilayer film, a multilayer end electrode structure can be adopted. Further, when the film is formed by the vacuum film forming method, it is possible to solve the problem of resistance to plating during barrel plating and the problem of ohmic contact with the connection portion with the extraction electrode or the internal electrode in the case of the thick film process. Further, the lift-off resist is formed by a method of embedding and transferring the resist in an intaglio plate molded with a silicone resin or the like, or a method by screen printing, according to the chip size, the chip shape, or the end electrode pitch to be formed. Either a photoresist effective for forming a fine pattern or a forming method using a photolithography technique is selected.

【0009】[0009]

【実施例】図1(A)は本発明による電子部品の一実施
例を示す斜視図、図1(B)、(C)はそれぞれ(A)
のE−E、F−F断面図である。本実施例は、アルミナ
等の絶縁基板1上に、蒸着、スパッタリング等の真空成
膜法により、ニッケル−クロム系の抵抗膜2と、取り出
し電極としての上部電極3とを形成し、その上にエポキ
シ系樹脂からなる保護膜4を、上部電極3の一部が露出
するように覆い、個々のチップに分割後、チップの端部
に、上部電極3にそれぞれ一体に接続させて端部電極5
を形成したものである。ここで、端部電極5は、リフト
オフ法により銅や銀により形成した薄膜をベース膜と
し、その上にニッケルメッキと錫メッキを施すかあるい
は半田メッキを施したものである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A is a perspective view showing an embodiment of an electronic component according to the present invention, and FIGS.
FIG. 6 is a sectional view taken along line EE and FF of FIG. In this embodiment, a nickel-chromium resistance film 2 and an upper electrode 3 as a take-out electrode are formed on an insulating substrate 1 made of alumina or the like by a vacuum film forming method such as vapor deposition or sputtering, and formed on the resistive film 2. The protective film 4 made of an epoxy resin is covered so that a part of the upper electrode 3 is exposed, and the upper electrode 3 is divided into individual chips.
Is formed. Here, the end electrode 5 is formed by using a thin film formed of copper or silver by a lift-off method as a base film, and nickel plating and tin plating or solder plating on the base film.

【0010】図2、図3は図1の電子部品の製造方法
を、チップ1個分についてそれぞれ断面図あるいは平面
図で示す工程図であり、図2(A)の断面図に示すよう
に、アルミナ基板あるいはアルミナの内部に電極を有し
た誘電体基板1上に、蒸着またはスパッタリングにより
抵抗膜となるニッケル−クロム系の薄膜2を形成する。
次に図2(B)の断面図に示すように、上部電極の下地
膜となる銅薄膜3aを蒸着またはスパッタリングにより
形成する。次に図2(C)の断面図に示すように、感光
性レジスト6を全面に形成後、図2(D)の断面図と図
2(E)の平面図に示すように、上部電極3の下地膜と
なる銅薄膜3aが窓(6a)開きとなるように露光、現
像を行い、図2(F)に示すように、露出した銅薄膜3
a上に、ニッケル膜3bをメッキにより形成し、その後
図2(G)の断面図に示すように、レジスト6を剥離す
る。
FIGS. 2 and 3 are process diagrams showing the method of manufacturing the electronic component of FIG. 1 in a cross-sectional view or a plan view for one chip, respectively. As shown in the cross-sectional view of FIG. A nickel-chromium-based thin film 2 serving as a resistance film is formed on an alumina substrate or a dielectric substrate 1 having an electrode inside alumina by vapor deposition or sputtering.
Next, as shown in the cross-sectional view of FIG. 2B, a copper thin film 3a to be a base film of the upper electrode is formed by vapor deposition or sputtering. Next, as shown in the sectional view of FIG. 2C, after the photosensitive resist 6 is formed on the entire surface, as shown in the sectional view of FIG. 2D and the plan view of FIG. The exposed copper thin film 3 is exposed and developed so that the copper thin film 3a serving as the underlying film of FIG.
A nickel film 3b is formed on a by plating, and then the resist 6 is peeled off as shown in the sectional view of FIG.

【0011】レジスト6の剥離を終えた基板1の表面
は、ニッケル膜3bと銅薄膜でなる下地膜3aで覆われ
ており、この状態から過硫酸アンモニウム水溶液によっ
て銅薄膜3aをエッチングすることにより、図2(H)
の断面図、(I)の平面図に示すように、ニッケル膜3
bで被覆された部分以外の銅薄膜3aは除去され、最下
層のニッケル−クロム薄膜2が露出する。
The surface of the substrate 1 on which the resist 6 has been peeled off is covered with a nickel film 3b and a base film 3a made of a copper thin film. From this state, the copper thin film 3a is etched with an aqueous solution of ammonium persulfate to form a film. 2 (H)
As shown in the cross-sectional view of FIG.
The copper thin film 3a other than the portion covered with b is removed, and the lowermost nickel-chromium thin film 2 is exposed.

【0012】次に図2(J)の断面図に示すように、感
光性レジスト6を再度塗布し、抵抗パターンの露光と現
像とベークを行い、ニッケル−クロム薄膜2を溶解する
硝酸セリウム系エッチング溶液でエッチングし、図2
(K)の平面図に示すように、ニッケル−クロム薄膜2
による抵抗パターンを形成する。そして、図2(K)お
よび図2(L)の断面図に示すように、抵抗パターン保
護を目的として、上部電極3の一部とダイシング時の切
りしろ(スクライブライン)を除くエリアに、エポキシ
系樹脂等をスクリーン印刷により印刷後、キュアして保
護膜4を形成する。
Next, as shown in the sectional view of FIG. 2 (J), a photosensitive resist 6 is applied again, and the resistance pattern is exposed, developed and baked, and the cerium nitrate-based etching for dissolving the nickel-chromium thin film 2 is performed. Etching with solution, Figure 2
As shown in the plan view of (K), the nickel-chromium thin film 2
To form a resistance pattern. Then, as shown in the cross-sectional views of FIGS. 2 (K) and 2 (L), epoxy is applied to an area excluding a part of the upper electrode 3 and a cut margin (scribe line) during dicing for the purpose of protecting the resistance pattern. After printing a system resin or the like by screen printing, the resin is cured to form the protective film 4.

【0013】保護膜4形成後の基板1は、ダイシングに
より所望のチップ形状に切断し、必要であれば、バレル
加工を行ってチップエッジ部を面取する。
The substrate 1 on which the protective film 4 has been formed is cut into a desired chip shape by dicing, and if necessary, barrel processing is performed to chamfer the chip edge portion.

【0014】次の工程である端部電極5の形成は、図3
(A)の側面図(図2(L)の左側面図、または右側面
図に相当)と図3(B)に示すように、端部電極5の形
成部を除く部分にリフトオフレジスト8によりマスキン
グする。ここで、マスキングの方法には3通りある。そ
の1つはシリコン樹脂等で型取りされた凹版にリフトオ
フレジスト8を埋め込んで基板1の端部に転写し、キュ
アする方法、2つ目は、マスキング部がパターニングさ
れたスクリーン版によりリフトオフレジスト8を印刷、
キュアする方法、3つ目は、微細パターンの形成が可能
なリフトフォトレジスト8を塗布し、露光から現像、ベ
ーク等の一連のフォトリソ技術を活用する方法である。
The next step, which is the formation of the end electrodes 5, is shown in FIG.
As shown in the side view (corresponding to the left side view or the right side view of FIG. 2L) of FIG. 2A and the part of FIG. Mask it. There are three masking methods. One of them is a method of embedding a lift-off resist 8 in an intaglio plate made by molding a silicon resin and transferring it to the end of the substrate 1 to cure it, and the second is a lift-off resist 8 by a screen plate having a masking portion patterned. Print,
The third method is a method of applying a lift photoresist 8 capable of forming a fine pattern and utilizing a series of photolithography techniques such as exposure, development, and baking.

【0015】このようなリフトオフレジスト8の被着を
終えたチップは、図3(B)に示すように、チップ表面
上に形成された上部電極3と端部全面が窓開きされた蒸
着マスク9に取付け、図3(C)に示すように、銅また
は銀でなる薄膜5aをスパッタリング(または蒸着)す
る。なお、この薄膜5aを被着する前に、下地膜とし
て、ニッケル−クロム膜またはクロム膜を形成し、その
後、連続して前記銅または銀等の導電率の高い膜を形成
して基板1との密着性を高め、また、銅または銀等の拡
散を防止する場合もある。また、銅でなる薄膜5aの上
に、耐酸および酸化防止膜として、銅−ニッケル膜等を
形成する場合もある。
As shown in FIG. 3 (B), the chip on which the lift-off resist 8 has been deposited as described above is provided with the upper electrode 3 formed on the surface of the chip and the vapor deposition mask 9 in which the entire surface of the end is opened. Then, as shown in FIG. 3 (C), a thin film 5a made of copper or silver is sputtered (or vapor-deposited). Before depositing the thin film 5a, a nickel-chromium film or a chromium film is formed as a base film, and thereafter, a film having high conductivity such as copper or silver is continuously formed to form the substrate 1. In some cases, the adhesiveness of copper is increased, and diffusion of copper or silver is prevented. Further, a copper-nickel film or the like may be formed on the thin film 5a made of copper as an acid resistant and antioxidant film.

【0016】次に基板1の端部全面および上部電極3に
被着したチップを、リフトオフレジスト8を溶解する溶
液に浸漬するか、あるいは超音波剥離を行い、図3
(D)に示すように、リフトオフレジスト8を除去す
る。上述の方法で作製した端部電極は薄膜5aであるた
め、図3(E)に示すように、バレルメッキによりニッ
ケル膜5bと錫膜5cを形成するか、または図3(F)
に示すように半田メッキ5dが施され、完成する。
Next, the chip adhered to the entire surface of the end portion of the substrate 1 and the upper electrode 3 is immersed in a solution that dissolves the lift-off resist 8 or is ultrasonically peeled off, and FIG.
As shown in (D), the lift-off resist 8 is removed. Since the end electrode manufactured by the above method is the thin film 5a, the nickel film 5b and the tin film 5c are formed by barrel plating as shown in FIG. 3E, or the end electrode is formed as shown in FIG.
Solder plating 5d is applied as shown in FIG.

【0017】前記基板1には、ガラスエポキシ樹脂やフ
ェノール樹脂、あるいは混成集積回路用の基板を用い、
前記同様の工程で端部電極5を形成してもよい。
As the substrate 1, a glass epoxy resin, a phenol resin, or a substrate for a hybrid integrated circuit is used.
The end electrode 5 may be formed in the same process as described above.

【0018】このように、リフトオフ法を用いて端部電
極5を形成することにより、抵抗膜2や上部電極3を上
記実施例のように薄膜プロセスによって形成しても、抵
抗膜2や上部電極3の酸化や組成物質の蒸発の問題がな
く、薄膜プロセスによって抵抗ネットワークを形成する
ことが可能である。従って、電気的特性、信頼性および
安定性における優位性を有する薄膜による電子部品が得
られ、また、フォトリソ技術により、微細パターンが可
能となり、小型化、低背化が達成でき、市場の高精度
化、高信頼性の要求並びに低価格化の要求に対応可能と
なる。
Thus, by forming the end electrodes 5 by using the lift-off method, even if the resistance film 2 and the upper electrode 3 are formed by the thin film process as in the above embodiment, the resistance film 2 and the upper electrode 3 are formed. It is possible to form a resistance network by a thin film process without the problem of oxidation of No. 3 and evaporation of the composition material. Therefore, thin film electronic parts with superiority in electrical characteristics, reliability and stability can be obtained. Moreover, the photolithography technology enables fine patterns, downsizing and height reduction, and high precision in the market. It is possible to meet demands for higher cost, higher reliability, and lower prices.

【0019】また、抵抗膜2や上部電極3に低融点金属
材や可溶体、あるいは、保護膜4としてポリイミド、エ
ポキシ、フェノール等の樹脂を使用する場合、さらには
ガラスエポキシやフェノール等の樹脂基板を用いる場合
においても端部電極5の形成が可能となる。
When a low melting point metal material or a fusible material is used for the resistance film 2 or the upper electrode 3 or a resin such as polyimide, epoxy or phenol is used as the protective film 4, a resin substrate such as glass epoxy or phenol is used. Even when using, the end electrode 5 can be formed.

【0020】また、前述のように、端部電極5の導体膜
5aの下地膜としての基板との密着強度や導体金属の拡
散防止を目的とする膜を形成したり、導体膜5aを覆う
被覆膜として、耐酸性の向上や酸化防止性の向上を目的
とする種々の膜を形成でき、また、従来の印刷、焼き付
けによる場合の接合部のオーミックコンタクトの問題も
解決できる。
Further, as described above, a film for the purpose of forming a film for the purpose of preventing the conductive metal from diffusing or forming a film having a close contact strength with the substrate as a base film of the conductor film 5a of the end electrode 5 or a covering film for covering the conductor film 5a. As a cover film, various films for the purpose of improving acid resistance and oxidation resistance can be formed, and the problem of ohmic contact at the joint portion in the case of conventional printing or baking can be solved.

【0021】図4(A)はコンデンサチップに本発明を
適用した一実施例を示す斜視図、(B)、(C)はそれ
ぞれ(A)のH−H、I−I断面図である。図4におい
て、11はアルミナやチタン酸バリウム等、誘電率等の
目的に応じて材質が選択され誘電体、12は誘電体11
内に内蔵された銅、銀、銀/パラジウムあるいは金等の
金属でなる内部電極、5は端部電極である。誘電体11
と内部電極12は、スクリーン印刷法あるいはシート法
等により積層し、焼成する厚膜プロセス、あるいはフォ
トリソ技術、真空成膜法やメッキによる薄膜プロセスに
より形成される。
FIG. 4A is a perspective view showing an embodiment in which the present invention is applied to a capacitor chip, and FIGS. 4B and 4C are sectional views taken along line HH and II of FIG. In FIG. 4, reference numeral 11 is a dielectric material such as alumina or barium titanate, which is selected in accordance with the purpose such as dielectric constant, and 12 is a dielectric material 11.
Internal electrodes 5 made of a metal such as copper, silver, silver / palladium, or gold incorporated therein are end electrodes. Dielectric 11
The internal electrode 12 and the internal electrode 12 are formed by a thick film process of laminating and firing by a screen printing method or a sheet method, or by a photolithography technique, a vacuum film forming method, or a thin film process by plating.

【0022】端部電極5は、誘電体11でなるチップの
端部に、図3で説明したように、銅や銀等の薄膜をリフ
トオフ法により形成した後、ニッケル膜と錫膜を形成す
るか、あるいは半田メッキを施して形成される。
The end electrode 5 is formed by forming a thin film of copper, silver or the like by a lift-off method, and then forming a nickel film and a tin film on the end of the chip made of the dielectric 11 as described with reference to FIG. Alternatively, it is formed by applying solder plating.

【0023】図5(A)は本発明の他の実施例を示す斜
視図、(B)はそのJ−J断面図であり、磁性材料でな
る基板15上にスパイラル型の薄膜コイル16を図1の
実施例と同様に形成すると共に、リフトオフ法により端
部電極5を形成したものである。
FIG. 5A is a perspective view showing another embodiment of the present invention, and FIG. 5B is a sectional view taken along the line JJ, showing a spiral type thin film coil 16 on a substrate 15 made of a magnetic material. The end electrode 5 is formed by the lift-off method as well as the first embodiment.

【0024】図6(A)は本発明の他の実施例であり、
1個のインダクタ、コンデンサ、抵抗体等を構成するよ
うに、絶縁体(目的により、誘電体や磁性体として構成
あるいは使用される)からなるチップ17の内部または
表面に、インダクタ、コンデンサ、抵抗その他これらの
組合わせからなる1つの機能素子を形成し、前記実施例
の方法により1対の端部電極5を形成したものである。
またこの機能素子は、厚膜プロセスや薄膜プロセスのみ
でなく、金属箔や半導体プロセスを用いて形成したもの
であってもよく、機能素子は能動素子として構成される
ものであってもよい。
FIG. 6A shows another embodiment of the present invention.
An inductor, a capacitor, a resistor, etc. are provided inside or on the surface of the chip 17 made of an insulator (which is constructed or used as a dielectric or a magnetic material depending on the purpose) so as to form one inductor, a capacitor, a resistor or the like. One functional element composed of these combinations is formed, and a pair of end electrodes 5 is formed by the method of the above embodiment.
Further, this functional element may be formed not only by a thick film process or a thin film process but also by using a metal foil or a semiconductor process, and the functional element may be configured as an active element.

【0025】[0025]

【発明の効果】本発明によれば、電子部品の端部電極を
真空成膜法により形成したので、薄膜プロセス、厚膜プ
ロセス、金属箔を用いたプロセス、半導体プロセス等製
造プロセスの如何に係らず、また、樹脂性基板や低融点
材料等、機能素子構成材料の如何を問わず、端部電極の
形成が可能となる。このため、電子部品設計上の自由度
が広がると共に、フォトリソ技術を用いた機能素子の形
成が可能となり、高精度化の要求に応えることができ、
また、従来のような端部電極焼成熱による性能劣化の問
題もなく、高信頼性を保つことができる。また、端部電
極の微細パターン化や多層化が容易となり、電子部品の
小型化、低背化、高密度化、低価格化の要求に応えるこ
とが可能となる。また、端部電極を密着強度の向上、拡
散防止、耐酸性や酸化防止性の向上等、目的に応じた多
層膜の形成が容易に行える。また、チップサイズ、チッ
プ形状、端部電極ピッチに応じて、リフトオフ法による
レジストの形成法を選択することにより、種々の要求に
対応できる。
According to the present invention, since the end electrodes of the electronic component are formed by the vacuum film forming method, it is possible to perform the manufacturing process such as a thin film process, a thick film process, a process using a metal foil, and a semiconductor process. In addition, the end electrodes can be formed regardless of the functional element constituent material such as the resinous substrate and the low melting point material. For this reason, the degree of freedom in designing electronic components is expanded, and it is possible to form functional elements using photolithography technology, and it is possible to meet the demand for higher precision.
Further, it is possible to maintain high reliability without the problem of performance deterioration caused by the heat of burning the end electrodes as in the prior art. Further, it becomes easy to make the end electrodes finely patterned and multilayered, and it becomes possible to meet the demands for downsizing, low profile, high density, and low price of electronic components. Further, it is possible to easily form a multilayer film according to the purpose, such as improving the adhesion strength of the end electrodes, preventing diffusion, improving acid resistance and oxidation resistance. Further, various requirements can be met by selecting the resist forming method by the lift-off method according to the chip size, the chip shape, and the end electrode pitch.

【図面の簡単な説明】[Brief description of drawings]

【図1】(A)は本発明による電子部品の一実施例を示
す斜視図、(B)、(C)はそれぞれ(A)のE−E、
F−F断面図である。
FIG. 1A is a perspective view showing an embodiment of an electronic component according to the present invention, and FIGS. 1B and 1C are EE of FIG.
It is a FF sectional view.

【図2】図1の実施例の製造工程の一部を示す工程図で
ある。
FIG. 2 is a process drawing showing a part of the manufacturing process of the embodiment of FIG.

【図3】図1の実施例の製造工程の残りの工程を示す工
程図である。
FIG. 3 is a process drawing showing the remaining steps of the manufacturing process of the embodiment in FIG.

【図4】(A)は本発明による電子部品の他の実施例を
示す斜視図、(B)、(C)はそれぞれ(A)のH−
H、I−I断面図である。
4A is a perspective view showing another embodiment of the electronic component according to the present invention, and FIGS. 4B and 4C are H- of FIG.
It is H, II sectional drawing.

【図5】(A)は本発明による電子部品の他の実施例を
示す斜視図、(B)は(A)のJ−J断面図である。
5A is a perspective view showing another embodiment of the electronic component according to the present invention, and FIG. 5B is a sectional view taken along line JJ of FIG.

【図6】(A)、(B)、(C)はそれぞれ本発明の他
の実施例を示す斜視図である。
6 (A), (B) and (C) are perspective views showing another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1:誘電体基板、2:抵抗膜、3:上部電極、4保護
膜、5:端部電極、6:感光性レジスト、8:リフトオ
フレジスト、9:マスク、11:誘電体、12:内部電
極、15:磁性材基板、16:スパイラル型コイル、1
7:チップ
1: Dielectric substrate, 2: Resistive film, 3: Upper electrode, 4 Protective film, 5: End electrode, 6: Photosensitive resist, 8: Lift-off resist, 9: Mask, 11: Dielectric, 12: Internal electrode , 15: magnetic material substrate, 16: spiral coil, 1
7: Chip

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】内部または表面の少なくともいずれかに機
能素子を形成したチップまたは基板の端部に、取り出し
電極または内部電極に接続された端部電極を形成する電
子部品において、 前記端部電極が、真空成膜法により形成されたものでな
ることを特徴とする電子部品。
1. An electronic component in which an end electrode connected to a lead-out electrode or an internal electrode is formed at an end of a chip or a substrate having a functional element formed on at least one of the inside and the surface thereof. An electronic component characterized by being formed by a vacuum film forming method.
【請求項2】内部または表面の少なくともいずれかに機
能素子を形成したチップまたは基板の端部に、取り出し
電極または内部電極に接続された端部電極を形成する電
子部品を製造する方法において、 前記チップまたは基板の端面における前記取り出し電極
または内部電極を除くエリアに、凹版印刷法、スクリー
ン印刷法またはフォトリソグラフィによりリフトオフレ
ジストを形成した後、真空成膜法により導電体を着膜
し、その後リフトオフレジストを除去することにより、
端部電極を形成することを特徴とする電子部品の製造方
法。
2. A method of manufacturing an electronic component, wherein an end electrode connected to a take-out electrode or an internal electrode is formed at an end of a chip or a substrate having a functional element formed on at least one of the inside and the surface thereof. After forming a lift-off resist by an intaglio printing method, a screen printing method or photolithography in an area on the end surface of the chip or the substrate excluding the extraction electrodes or internal electrodes, a conductor is deposited by a vacuum film forming method, and then the lift-off resist is formed. By removing
A method for manufacturing an electronic component, which comprises forming an end electrode.
JP7111217A 1995-04-11 1995-04-11 Electronic component and its manufacture Withdrawn JPH08288102A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7111217A JPH08288102A (en) 1995-04-11 1995-04-11 Electronic component and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7111217A JPH08288102A (en) 1995-04-11 1995-04-11 Electronic component and its manufacture

Publications (1)

Publication Number Publication Date
JPH08288102A true JPH08288102A (en) 1996-11-01

Family

ID=14555502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7111217A Withdrawn JPH08288102A (en) 1995-04-11 1995-04-11 Electronic component and its manufacture

Country Status (1)

Country Link
JP (1) JPH08288102A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004087966A (en) * 2002-08-28 2004-03-18 Mitsubishi Electric Corp Dielectric substrate with resistor film, and its manufacturing method
JP2007220985A (en) * 2006-02-17 2007-08-30 Tdk Corp Thin film device
JP2014199571A (en) * 2013-03-29 2014-10-23 大日本印刷株式会社 Manufacturing method of touch panel sensor member

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004087966A (en) * 2002-08-28 2004-03-18 Mitsubishi Electric Corp Dielectric substrate with resistor film, and its manufacturing method
JP2007220985A (en) * 2006-02-17 2007-08-30 Tdk Corp Thin film device
TWI407547B (en) * 2006-02-17 2013-09-01 Tdk Corp Thin-film device
JP2014199571A (en) * 2013-03-29 2014-10-23 大日本印刷株式会社 Manufacturing method of touch panel sensor member

Similar Documents

Publication Publication Date Title
US7663225B2 (en) Method for manufacturing electronic components, mother substrate, and electronic component
US20220028602A1 (en) Inductor component
JP2615151B2 (en) Chip coil and method of manufacturing the same
CA1182583A (en) Thin film discrete decoupling capacitor
US6555913B1 (en) Electronic component having a coil conductor with photosensitive conductive paste
CN108288534B (en) Inductance component
JP2004040084A (en) Plated terminal
JP4317107B2 (en) Electronic device having organic material insulating layer and method for manufacturing the same
KR20010032411A (en) Improved miniature surface mount capacitor and method of making same
JP3000579B2 (en) Manufacturing method of chip coil
JP4687205B2 (en) Electronic components
JPH1197243A (en) Electronic component and its manufacture
JPH08288102A (en) Electronic component and its manufacture
JP2749489B2 (en) Circuit board
JP2001345205A (en) Method of forming thin-film resistor element in printed board, thin-film resistor element and thin-film capacitor element
JPH05267025A (en) Manufacture of chip part and manufacture of electronic part
JP2668375B2 (en) Circuit component electrode manufacturing method
JP3284694B2 (en) Multilayer resistor module
JP3144596B2 (en) Thin film electronic component and method of manufacturing the same
JP2699980B2 (en) Wiring board with a film element inside
JPH06112091A (en) Layered electronic part and manufacture thereof
JPH0265194A (en) Manufacture of printed wiring board with thick film element
JPH06124850A (en) Laminated composite electronic component
JPH0567878A (en) Hybrid circuit board and manufacture thereof
US20220319762A1 (en) Inductor component

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20020702