JPS5890797A - Method of producing electronic part - Google Patents

Method of producing electronic part

Info

Publication number
JPS5890797A
JPS5890797A JP56191122A JP19112281A JPS5890797A JP S5890797 A JPS5890797 A JP S5890797A JP 56191122 A JP56191122 A JP 56191122A JP 19112281 A JP19112281 A JP 19112281A JP S5890797 A JPS5890797 A JP S5890797A
Authority
JP
Japan
Prior art keywords
insulating film
polyimide
wiring
film
based polymer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56191122A
Other languages
Japanese (ja)
Inventor
隆夫 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56191122A priority Critical patent/JPS5890797A/en
Publication of JPS5890797A publication Critical patent/JPS5890797A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electronic Switches (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 この発明は、半導体装置、薄膜サーマルへラド等、及び
これらを複合化した電子部品においてパターンニングし
て形成される導゛・1体、抵抗体、及び絶縁体等に、ポ
リイミド系高分子材料よりなる平坦化絶縁膜を形成する
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to conductors, resistors, insulators, etc. formed by patterning semiconductor devices, thin film thermal conductors, etc., and electronic components that combine these. , relates to a method for forming a planarized insulating film made of a polyimide-based polymer material.

半導体装置、薄膜サーマルヘッド等、及びこれらを複合
化した電子部品の小形化、応答速度の敏速化、信頼性の
向上等の要求から薄膜技術をマイクロエレクトロニクス
へ応用した薄膜電子部品等を開発しようとする試°みが
強くなっている。
In response to demands for miniaturization, faster response speed, and improved reliability of semiconductor devices, thin-film thermal heads, etc., and electronic components that combine these, efforts have been made to develop thin-film electronic components that apply thin-film technology to microelectronics. The attempt to do so is getting stronger.

ここではこれらの薄膜電子部品等の形成によくもちいら
れる多層配線を例に、ポリイミド系高分子材料等による
平坦化絶縁膜の形成方法を説明する。
Here, a method for forming a flattened insulating film using a polyimide-based polymer material or the like will be explained, taking as an example a multilayer wiring often used for forming these thin-film electronic components.

従来のこの種、多層配線の形成方法として第1図、第2
図に示すものがあった。
Conventional methods for forming this type of multilayer wiring are shown in Figures 1 and 2.
There was something shown in the figure.

第1図はマトリクス型二層配線の構成例を示した図であ
り第2図は第1図の■−■線における二層配線の断面構
造図である。
FIG. 1 is a diagram showing an example of the structure of a matrix-type two-layer wiring, and FIG. 2 is a cross-sectional structural diagram of the two-layer wiring taken along the line ■--■ in FIG.

図において、(1)は一層配線、(2)二層配線4(3
)基板、(4)は絶縁膜、(5)は眉間絶縁膜、(6)
は短絡部、(7)はi−1’r11j1部を示してイル
In the figure, (1) is single-layer wiring, (2) double-layer wiring 4 (3
) substrate, (4) is an insulating film, (5) is an insulating film between the eyebrows, (6)
indicates the short circuit part, and (7) indicates the i-1'r11j1 part.

まず第1図、第2図とともに従来法による多層配線の形
成方法を説明する。
First, a conventional method for forming multilayer wiring will be explained with reference to FIGS. 1 and 2.

半導体装置、h膜す−マルヘッド等、及びこれ゛らを複
合化した電子部品等は、例えばステンレススチールある
いはセラミック、ガラス等よりなる導1シ性、又は絶縁
性の基板(3)上に、上述の各機能部、形成力”途中過
程、あるいは各機能部を形成した後に、例えば5i02
、又はSiN等よりなる絶縁膜(4)を設け、その上部
に例えばAI、又はAu  等よりなる一ノー配線(す
を形成した後に、ポリイミド系高分子材料等よりなる層
間絶縁膜(5〕を設け、この上部に再度AI、又はAu
  等よりなる二層配線(2)を形成して、麺@五子部
品等の二ノー配線構造が完成していた。
Semiconductor devices, multi-layer heads, etc., and electronic components made of composites of these are mounted on conductive or insulating substrates (3) made of stainless steel, ceramics, glass, etc., as described above. 5i02 during the process or after forming each functional part.
After forming an insulating film (4) made of , or SiN, etc., and forming a single-no wiring made of, for example, AI or Au, an interlayer insulating film (5) made of a polyimide-based polymer material, etc. is provided. and then put AI or Au again on top of this.
By forming a two-layer wiring (2) consisting of the above components, a two-layer wiring structure such as noodles@goko parts was completed.

従来のものは以上のような構成になっているので、−)
−配線(1)のパターン端部の特に肩の部分において、
短絡(6)、又は断線(7)が発生しやすい傾向を有し
ている。特に一層配線に大きな(温容量が必要等で、こ
の膜厚が増加した場合には、特にこの短絡、断線等の発
生の可能性が増加する。又この短絡、断線等の欠陥を防
止するためにポリイミド系高分子材料等よりなる層間絶
縁膜(5)の膜厚を増加させると、一層配線鳳すの引出
し端子部(図示せず)での、例えばフォトエツチング法
による層間絶縁膜(5)のエツチング、除去が困難とな
り、又微細パターンの形成が不能となる等、種々の欠陥
を有し、集積度が高く、かつ短絡、断線のない良好な多
層配線が得られないといった欠点があった。
The conventional one has the above configuration, so -)
- Especially at the shoulder part of the pattern end of wiring (1),
Short circuit (6) or disconnection (7) tends to occur easily. In particular, when the film thickness increases due to the need for larger wiring (such as thermal capacity), the possibility of occurrence of short circuits, disconnections, etc. increases.Also, to prevent defects such as short circuits, disconnections, etc. When the film thickness of the interlayer insulating film (5) made of a polyimide-based polymer material is increased, the interlayer insulating film (5) formed by, for example, a photoetching method at the lead-out terminal part (not shown) of a single-layer wiring board is increased. It has various defects such as making etching and removal difficult, making it impossible to form fine patterns, etc., and making it impossible to obtain good multilayer wiring with a high degree of integration and no short circuits or disconnections. .

この発明は前述のような従来のものの欠点を除去するた
めになされたもので、層間絶縁膜を二つの1−に分離し
、−Jai1目で一層配線と同一高さの平坦化絶縁膜を
形成し、二層目で所望の膜厚を有する層間絶縁膜を形成
する方法により、半導体装置、薄膜サーマルヘッド等、
及びこれらを複合化した電子部品等に必要な、平坦化さ
れた良好な層間絶縁膜を有する多層配線構造の製造方法
を提供することを目的としている。
This invention was made in order to eliminate the drawbacks of the conventional method as described above, and it separates the interlayer insulating film into two 1- layers, and forms a flattened insulating film with the same height as the wiring in one layer. By forming an interlayer insulating film with a desired thickness as the second layer, semiconductor devices, thin film thermal heads, etc.
The present invention also aims to provide a method for manufacturing a multilayer wiring structure having a good flattened interlayer insulating film, which is necessary for electronic components etc. in which these are combined.

以下この発明の一実施例を第8図により説明する。第8
図−はこの発明の一実施例の断面図で第2図と同じ部分
の請面構造図である。
An embodiment of the present invention will be described below with reference to FIG. 8th
Figure 2 is a cross-sectional view of one embodiment of the present invention, and is a bottom structural view of the same portion as in Figure 2.

)(において、(1)は−ノー配線、(2)二層配線、
(3)基板、(4)は絶縁膜、(8)は平坦化絶縁膜、
(9)は層間絶縁膜を示している。ひき続き、第8図に
よりこの発明の一実施例を説明する。
) (where (1) is -no wiring, (2) two-layer wiring,
(3) substrate, (4) insulating film, (8) planarizing insulating film,
(9) indicates an interlayer insulating film. Next, one embodiment of the present invention will be explained with reference to FIG.

半導体装置、薄膜サーマルヘッド等、及びこれらを各機
能部を複合化したst電子部品は、例えばステンレスス
チール、あるいはセラミック、ガラス等よノりなる4イ
性又は絶縁性の基板(3)上に、上述の各機能部形成の
途中過程、あるいは各機能部を形成した後に、例えばS
iO□、又はSiN等よりなる絶縁膜(4)を設け、そ
の上部に、例えばAI、又はAu等よりなる−1−配線
(1)を形成した後に、ポリイミド系高分子材料等を例
えばスピナー法等で、−1−配線(1)と同じ膜厚にな
るように設置し、フォトエツチング法により一層配線(
1)上部のポリイミド系高分子材料等をエツチング除去
し、一層配線(1)と同一高さを有する平坦化絶縁膜(
8)を形成する。
Semiconductor devices, thin-film thermal heads, etc., and ST electronic components in which these functional parts are combined, are mounted on a four-dimensional or insulating substrate (3) made of, for example, stainless steel, ceramic, glass, etc. During the process of forming each of the functional parts described above, or after forming each functional part, for example, S
After providing an insulating film (4) made of iO□ or SiN, and forming a -1- wiring (1) made of, for example, AI or Au on top of the insulating film (4), a polyimide-based polymer material or the like is formed using, for example, a spinner method. etc., so that the film thickness is the same as that of the -1- wiring (1), and further wiring (
1) Remove the polyimide polymer material on the top by etching and form a flattened insulating film (
8).

この後所望の膜厚を有する11間絶縁膜(9)を例えば
ポリイミド系高分子材料等をもちいてスピナー法等で形
成し、次いで例えばAI、又はAu等よりなる二層配線
(2)を形成して、前述の薄膜電子部品等の二層配線構
造が完成する。
Thereafter, a 11-layer insulating film (9) having a desired thickness is formed using, for example, a polyimide-based polymer material by a spinner method, and then a two-layer wiring (2) made of, for example, AI or Au is formed. In this way, the two-layer wiring structure of the thin film electronic component described above is completed.

この発明による多層配線等にもちいる平坦化絶縁膜は以
上のように構成されているので従来法の例で発生した一
層配線(1)のパターン端部の特に肩の部分において発
生したような一層配線と二1−配線の短絡、二層配線の
断線等がなく、又−1配線に例えば大きな電流容量が必
要でこの膜厚が増加した場合においても、層間絶縁膜を
、平坦化絶縁膜と層間絶縁膜に分離して構成したので、
前記短絡、断線が生じない。また層間絶縁膜を従来例の
ように短絡、断線を防止するために必要以上の膜厚に形
成する必要がなく、シたがって微細パターンの形成が可
能となる等、集積度が高く、かつ短絡、断線のない良好
な多層配線構造が得られる。
The flattening insulating film used for multilayer wiring, etc. according to the present invention is constructed as described above, so that the flattening insulating film used for multilayer wiring, etc. according to the present invention has the structure described above. Even if there is no short circuit between wiring and 21- wiring, disconnection of 2-layer wiring, etc., and even if -1 wiring requires a large current capacity and this film thickness increases, the interlayer insulating film can be replaced with a flattening insulating film. Since it is configured separately with an interlayer insulating film,
The aforementioned short circuit and disconnection do not occur. In addition, there is no need to form the interlayer insulating film thicker than necessary to prevent short circuits and disconnections, as in conventional methods, and it is therefore possible to form fine patterns, allowing for a high degree of integration and short circuits. , a good multilayer wiring structure without disconnection can be obtained.

又この発明による平坦化絶縁膜を例えば半導体装置、薄
膜サーマルヘッド等、及びこれらの各機能部を複合化し
た電子部品等の多層配線部に適用して、高集積度でかつ
短絡、断線の少ないものが得られる効果がある。
Furthermore, the flattened insulating film according to the present invention can be applied to multilayer wiring parts such as semiconductor devices, thin film thermal heads, etc., and electronic parts that combine these functional parts to achieve high integration and less short circuits and disconnections. It has the effect of getting something.

tおI;it記実施例では二層配線の場合を例に説明し
たが、これを発展させた、三層、四層〜十層等のいわゆ
る多1−配緑構造に−も適用できることはg及するまで
もなく、この場合には更に効果が大きい。
In the example described above, the case of two-layer wiring was explained as an example, but it can also be applied to a so-called multi-layer green structure, such as three-layer, four-layer to ten-layer, etc. Needless to say, the effect is even greater in this case.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来法、及びこの発明を説明するためのマト
リクス型二層配線の平面図、第2図は従来法を説明する
ための第1図■−■線における断面構造図、第3図はこ
の発明法を説明するための断面構造図で、第2図と同じ
部分を示したものである。 図において(11は一層配線、(2)は二層配線、(3
)は括板、(4)は絶縁膜、(5)は従来の層間絶縁膜
、(6)は短絡部、(7)は断線部、(8)は平坦化絶
縁膜、(9)は層間絶縁膜である。 なお肉牛、同一符合はそれぞれ同一、又は相当部分であ
る。 代理人  葛 野 信 −(外1名)
FIG. 1 is a plan view of a matrix type two-layer wiring for explaining the conventional method and the present invention, FIG. 2 is a cross-sectional structural diagram taken along the line ■-■ in FIG. 1 for explaining the conventional method, and FIG. The figure is a cross-sectional structural diagram for explaining the method of this invention, and shows the same part as FIG. 2. In the figure (11 is single-layer wiring, (2) is double-layer wiring, (3
) is the connecting plate, (4) is the insulating film, (5) is the conventional interlayer insulating film, (6) is the short circuit part, (7) is the disconnection part, (8) is the flattening insulating film, and (9) is the interlayer insulating film. It is an insulating film. For beef cattle, the same symbols mean the same or equivalent parts. Agent Shin Kuzuno - (1 other person)

Claims (1)

【特許請求の範囲】 (11半薄体装・d1薄膜サーマルヘッド等、及びこ4
1らを複合化した電子部品等の製造に際し、パターンニ
ングして形成される導1体、抵抗体、及び絶11体等の
台形・・兎膜上にポリイミド系高分子材料等を前記各形
成膜とほぼ同一の膜厚に形成した後に、フォトエツチン
グ法等により前記各形成膜上のポリイミドも高分子材料
等を除去し、再変ポリイミド系趙分子材料等を所望・D
膜厚に形成し、前記各形成膜表面、又は上部にポリイミ
ド系高分子材料等よりなる平坦化絶縁膜を形成するよう
にしたことを特徴とする電子部品の製造方法。 (2)平坦化絶i、J Iiがポリイミド系高分子材料
であることを特徴とする特許請求の範囲第1項記載の電
子部品の、快・な方法。
[Claims] (11 semi-thin body, d1 thin film thermal head, etc., and 4
When manufacturing electronic parts etc. that are a composite of 1 and 1, each of the above-mentioned formations of polyimide-based polymer materials, etc. After forming the film to approximately the same thickness as the film, the polyimide on each of the formed films is removed using a photoetching method or the like to form a re-modified polyimide-based molecular material, etc. as desired.
A method for manufacturing an electronic component, characterized in that a flattening insulating film made of a polyimide-based polymer material or the like is formed on the surface or top of each of the formed films. (2) A convenient method for producing an electronic component according to claim 1, wherein the flattening materials i and JIi are polyimide-based polymer materials.
JP56191122A 1981-11-25 1981-11-25 Method of producing electronic part Pending JPS5890797A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56191122A JPS5890797A (en) 1981-11-25 1981-11-25 Method of producing electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56191122A JPS5890797A (en) 1981-11-25 1981-11-25 Method of producing electronic part

Publications (1)

Publication Number Publication Date
JPS5890797A true JPS5890797A (en) 1983-05-30

Family

ID=16269224

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56191122A Pending JPS5890797A (en) 1981-11-25 1981-11-25 Method of producing electronic part

Country Status (1)

Country Link
JP (1) JPS5890797A (en)

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