JP3182159B2 - Method for manufacturing multilayer wiring board - Google Patents

Method for manufacturing multilayer wiring board

Info

Publication number
JP3182159B2
JP3182159B2 JP7139391A JP7139391A JP3182159B2 JP 3182159 B2 JP3182159 B2 JP 3182159B2 JP 7139391 A JP7139391 A JP 7139391A JP 7139391 A JP7139391 A JP 7139391A JP 3182159 B2 JP3182159 B2 JP 3182159B2
Authority
JP
Japan
Prior art keywords
layer
polyimide resin
interlayer insulating
insulating layer
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP7139391A
Other languages
Japanese (ja)
Other versions
JPH04307759A (en
Inventor
武史 宮城
進 君島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP7139391A priority Critical patent/JP3182159B2/en
Publication of JPH04307759A publication Critical patent/JPH04307759A/en
Application granted granted Critical
Publication of JP3182159B2 publication Critical patent/JP3182159B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[発明の目的][Object of the Invention]

【0002】[0002]

【産業上の利用分野】この発明は、金属配線層/ポリイ
ミド樹脂層間絶縁層系の多層配線基板の製造方法に係
り、さらに詳しくは金属配線層間のコンタクトホ−ル部
の構成を改良した多層配線基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a multilayer wiring board based on a metal wiring layer / polyimide resin interlayer insulating layer, and more particularly, to a multilayer wiring having an improved contact hole between metal wiring layers. The present invention relates to a method for manufacturing a substrate.

【0003】[0003]

【従来の技術】近年、ス−パ−コンピュ−タは勿論のこ
と、大型汎用コンピュ−タ、ワ−クステ−ション、パソ
コンなどあらゆるコンピュ−タにおいて、高速化や記憶
容量の大容量化が要求されている。この要求に応えるた
め、半導体デバイスはDRAMに代表されるように大容
量化が進み、またGaAs、ECLなどの超高速素子が
出現している。
2. Description of the Related Art In recent years, not only supercomputers, but also large-sized general-purpose computers, workstations, personal computers, and all other computers have been required to have high speed and large storage capacity. Have been. To meet this demand, semiconductor devices have been increasing in capacity as typified by DRAM, and ultra-high-speed elements such as GaAs and ECL have appeared.

【0004】これらの超高速素子や大容量メモリ−の特
長を十分に引き出し、所要の機能を十分に発揮させるに
は、従来の多層プリント基板に実装する方式に代わる新
しい実装方式が不可欠である。その一つの手段として、
図2に断面的に示すごとく、層間絶縁層1a、1bにポリイ
ミド樹脂を、導体配線層2a、2b、2cに銅を用いた銅配線
層/ポリイミド樹脂層間絶縁層系の多層配線基板に、裸
の半導体チップをフリップ・チップ方式やTAB方式に
よって、高密度実装する方法が開発されている。図2に
示す構成は、コンタクトホ−ル内を埋めず、多層化する
に伴いコンタクトホ−ルの位置をずらしていく方法(ス
テップ・ビア)によるものであり、符号3は導体配線層
2a、2b、2c間を電気的に接続する導電性接続部3a、3bを
形成するコンタクトホール部、4は絶縁性支持基板をそ
れぞれ示す。
In order to fully exploit the features of these ultra-high-speed devices and large-capacity memories, and to fully exhibit the required functions, a new mounting method is indispensable in place of the conventional mounting method on a multilayer printed circuit board. As one of the means,
As shown in cross section in FIG. 2, a polyimide resin is used for the interlayer insulating layers 1a and 1b, and a copper wiring layer using copper for the conductor wiring layers 2a, 2b and 2c, and a multilayer wiring board of a polyimide resin interlayer insulating layer system. A high-density mounting method has been developed for a semiconductor chip by a flip chip method or a TAB method. The configuration shown in FIG. 2 is based on a method (step / via) in which the position of the contact hole is shifted as the number of layers is increased without filling the inside of the contact hole.
Contact hole portions 4 for forming conductive connection portions 3a and 3b for electrically connecting between 2a, 2b and 2c indicate insulating support substrates, respectively.

【0005】ところが、前記した銅/ポリイミド樹脂系
の多層配線基板においては、信号配線の特性インピ−ダ
ンスを一般的に、50〜 100Ω程度に制御する必要性か
ら、ポリイミド樹脂絶縁層(層間絶縁層)1a、1bを、1
層当り20um 程度以上の厚い膜厚が要求される。この厚
いポリイミド樹脂層(膜)1a、1bに、所要のコンタクト
ホ−ル3を形成して、このコンタクトホール部3を介し
て多層的に形成されている配線層2a、2b、2c間を接続し
た場合、コンタクトホ−ル部3による凹凸が原因となっ
て、配線層の切断や特性インピ−ダンスのばらつきが起
こり、高周波特性の劣化を生じる。
However, in the above-mentioned copper / polyimide resin-based multilayer wiring board, the characteristic impedance of the signal wiring is generally required to be controlled to about 50 to 100 Ω, so that a polyimide resin insulating layer (interlayer insulating layer) is required. ) 1a, 1b is 1
A thick film of about 20 um or more per layer is required. A required contact hole 3 is formed on the thick polyimide resin layers (films) 1a and 1b, and the wiring layers 2a, 2b and 2c formed in a multilayer structure are connected via the contact hole 3. In this case, unevenness due to the contact hole 3 causes disconnection of the wiring layer and variation in characteristic impedance, resulting in deterioration of high-frequency characteristics.

【0006】前記のような問題に対応して、図3に断面
的に示すように、コンタクトホ−ル部3の内部を金属5
a、5bで満たして平坦化し、不具合を回避する手段も知
られている。
In order to cope with the above-mentioned problem, as shown in FIG.
There is also known a method for filling and flattening with a and 5b to avoid a problem.

【0007】[0007]

【発明が解決しようとする課題】しかし、前記図3に図
示した構成(いわゆるフィルド・ビア)の場合は、有機
物であるポリイミド樹脂層1a、1bとコンタクトホ−ル3
内に埋め込まれた無機物である金属柱5a、5bとの熱膨脹
率の違いにより、多層配線部の形成工程中や製品の信頼
性試験の際に、コンタクトホ−ル3に埋め込んだ金属柱
5a、5bの側周面とコンタクトホ−ル3内壁面を成すポリ
イミド樹脂層1a、1bとの間で剥離が生じ、その結果、配
線(配線層)2b、2cが切断してしまうという不具合があ
った。
However, in the case of the configuration shown in FIG. 3 (so-called filled via), the polyimide resin layers 1a and 1b, which are organic substances, and the contact holes 3 are used.
Due to the difference in thermal expansion coefficient between the metal pillars 5a and 5b, which are inorganic substances embedded in the inside, the metal pillars embedded in the contact holes 3 during the formation process of the multilayer wiring portion and during the reliability test of the product.
Separation occurs between the side peripheral surfaces of 5a and 5b and the polyimide resin layers 1a and 1b forming the inner wall surface of the contact hole 3, and as a result, the wirings (wiring layers) 2b and 2c are cut off. there were.

【0008】つまり、前記高周波特性の劣化などの問題
を解消する手段、換言すると銅配線層/ポリイミド樹脂
層間絶縁層系の多層配線基板におけるコンタクトホ−ル
3内への金属柱5a、5bの埋め込み方式は、これまでのと
ころ良好な結果が得られず、非常に信頼性の低いもので
あった。
In other words, means for solving the problem of deterioration of the high-frequency characteristics and the like, in other words, embedding of the metal pillars 5a and 5b into the contact holes 3 in the multilayer wiring board of the copper wiring layer / polyimide resin interlayer insulating layer system. The method has so far not yielded good results and has been very unreliable.

【0009】本発明は、上記した点に鑑みなされたもの
で、非常に厚いポリイミド樹脂層(膜)にコンタクトホ
−ルを形成し、このコンタクトホ−ルを介して所要の配
線層間を電気的に接続する構成の多層配線を行った場合
においても、完全な平坦化が実現でき、かつ上記したコ
ンタクトホ−ルに埋め込み配置した金属柱の側周面とコ
ンタクトホ−ル内壁面を成すポリイミド樹脂との間で剥
離も生じる恐れのない多層配線基板の提供を目的とす
る。
SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a contact hole formed on a very thick polyimide resin layer (film), and an electric connection between required wiring layers is formed through the contact hole. Polyimide resin that can achieve complete flattening even when multi-layer wiring with a configuration connecting to the contact hole is formed and forms the inner peripheral wall surface of the contact hole and the side peripheral surface of the metal pillar embedded in the contact hole. It is an object of the present invention to provide a multilayer wiring board which does not cause separation between the wiring board and the wiring board.

【0010】[発明の構成][Structure of the Invention]

【0011】[0011]

【課題を解決するめの手段】本発明に係る多層配線基板
の製造方法は、支持基板の主面上に金属配線層およびポ
リイミド樹脂から成る層間絶縁層を順次形成する工程
と、前記形成される層間絶縁層の中所要の層間絶縁層に
接続用貫通孔を穿設する工程と、前記形成される接続用
貫通孔内に導電性金属柱を貫通・配置して所定の金属配
線層間を接続する工程を具備して成る多層配線基板の製
造方法において、前記接続用貫通孔を導電性金属柱の直
径より大きな径に穿設し、貫通孔内に導電性金属柱を遊
嵌的に貫通・配置して、次層の層間絶縁層を形成すると
きに遊嵌部をポリイミド樹脂で充填することを特徴とす
る。
A method of manufacturing a multilayer wiring board according to the present invention comprises the steps of sequentially forming a metal wiring layer and an interlayer insulating layer made of a polyimide resin on a main surface of a supporting substrate; Forming a connection through-hole in a required interlayer insulating layer in the insulating layer; and connecting and connecting predetermined metal wiring layers by penetrating and arranging conductive metal columns in the formed connection through-hole. In the method for manufacturing a multilayer wiring board, the connection through-hole is formed to have a diameter larger than the diameter of the conductive metal column, and the conductive metal column is freely inserted through and arranged in the through-hole. The loose fitting portion is filled with a polyimide resin when the next interlayer insulating layer is formed.

【0012】すなわち、本発明は配線層間を接続するた
めの導電性金属柱を貫通・配置するコンタクトホ−ルに
埋め込み配置する金属柱の側周面とコンタクトホ−ル内
壁面を成すポリイミド樹脂膜の間に空隙をもたせ、上層
の配線層を形成した後の層間絶縁層を形成するとき、前
記空隙にポリイミド樹脂を充填することを骨子とする。
なお、金属配線層を形成する金属としては、銅、アル
ミニウム、金など通常配線材料として用いられる金属で
構成されるものであればどのようなものでもよい。
That is, the present invention relates to a polyimide resin film forming the inner peripheral wall of the contact hole and the side peripheral surface of the metal pillar embedded and buried in the contact hole penetrating and arranging the conductive metal pillar for connecting the wiring layers. When forming an interlayer insulating layer after forming an upper wiring layer by providing a gap between them, it is essential to fill the gap with a polyimide resin.
The metal forming the metal wiring layer may be any metal as long as it is made of a metal usually used as a wiring material such as copper, aluminum, and gold.

【0013】[0013]

【作用】本発明によれば、接続用貫通孔(コンタクトホ
−ル)に貫通配置した導電性金属柱の側周面とコンタク
トホ−ル内壁面を成すポリイミド樹脂層(層間絶縁層)
上に形成された配線層との間に、熱衝撃のバッファとな
るポリイミド樹脂充填層が形成されるため、多層配線工
程の熱衝撃に対して有効であり、また高い信頼性が得ら
れる。さらに、比較的厚いポリイミド樹脂膜(層間絶縁
層)に接続用貫通孔を穿設(形成)し、多層配線工程を
行った場合においても、完全な平坦化が実現できるの
で、信号配線の特性インピ−ダンスのばらつきは非常に
小さくなり、良好な高周波特性を呈し得る。
According to the present invention, a polyimide resin layer (interlayer insulating layer) forming the inner peripheral wall surface of the contact hole and the side peripheral surface of the conductive metal pillar penetratingly disposed in the through hole (contact hole) for connection.
Since a polyimide resin filled layer serving as a buffer for thermal shock is formed between the wiring layer and the wiring layer formed thereon, it is effective against thermal shock in the multilayer wiring process and high reliability is obtained. Further, even when a through-hole for connection is formed (formed) in a relatively thick polyimide resin film (interlayer insulating layer) and a multilayer wiring process is performed, complete flattening can be realized. The variation in the dance is very small and can exhibit good high-frequency properties.

【0014】[0014]

【実施例】以下、図1を参照して本発明の一実施例を説
明する。
An embodiment of the present invention will be described below with reference to FIG.

【0015】図1は本発明に係る多層配線基板の製造方
法における実施態様を模式的に示す断面図であり、先ず
絶縁性支持基板4として、たとえばアルミナ基板を用意
する。 次いで前記絶縁性支持基板4の主面上に第1層
目の銅配線層(回路パターン)2aを、たとえばスパッタ
法などの薄膜形成法およびフォトリソグラフィで形成す
る。この第1層目の銅配線層2a形成面上に、前記第1層
目の銅配線層2aと次に多層的に形成する第2層目の銅配
線層2bとを絶縁するため第1層目のポリイミド樹脂層
(層間絶縁層)1aを形成する(図1(a) )。しかる後、
この第1層目のポリイミド樹脂層(層間絶縁層)1aに、
たとえば選択的なエッチング法によって、前記第1層目
の銅配線層2aと次に形成する第2層目の銅配線層1bとを
電気的に接続するためにコンタクトホ−ル(接続用貫通
孔)3′を穿設形成する(図1(b))。この際、前記コ
ンタクトホ−ル3′は、このコンタクトホール3′内に
導電性の金属柱5aが遊嵌的に(コンタクトホール3′内
壁面との間に空隙が残るように)、貫通・配置し得る程
度の径に、換言すると第1層目のポリイミド樹脂層(層
間絶縁層)1aの内壁面に接触せずに埋め込み得るように
穿設・形成される。
FIG. 1 is a cross-sectional view schematically showing an embodiment of a method for manufacturing a multilayer wiring board according to the present invention. First, for example, an alumina substrate is prepared as an insulating support substrate 4. Next, a first-layer copper wiring layer (circuit pattern) 2a is formed on the main surface of the insulating support substrate 4 by a thin film forming method such as a sputtering method and photolithography. On the surface on which the first-layer copper wiring layer 2a is to be formed, a first layer for insulating the first-layer copper wiring layer 2a and a second-layer copper wiring layer 2b to be subsequently formed in a multilayer structure is formed. An eye polyimide resin layer (interlayer insulating layer) 1a is formed (FIG. 1 (a)). After a while
The first polyimide resin layer (interlayer insulating layer) 1a
For example, a contact hole (connection through-hole) for electrically connecting the first copper wiring layer 2a and the second copper wiring layer 1b to be formed next by a selective etching method. ) 3 'is formed by drilling (FIG. 1 (b)). At this time, the contact hole 3 'penetrates through the contact hole 3' so that the conductive metal column 5a is loosely fitted (so that a gap remains between the contact hole 3 'and the inner wall surface of the contact hole 3'). It is pierced and formed so that it can be buried without contacting the inner wall surface of the first polyimide resin layer (interlayer insulating layer) 1a, in other words, to a diameter that can be arranged.

【0016】さらに、所要の接続用金属柱5aを電解メッ
キによって形成するための電極膜を、第1層目のポリイ
ミド樹脂層1a面および露出した第1層目の銅配線層2a面
にスパッタし、フォトレジストを塗布する。このフォト
レジストをコンタクトホ−ル3′上部の形状より小さい
パタ−ンを持つガラスマスクを用いてパタ−ン加工し、
導電性の金属柱5aを形成する部分のフォトレジストを除
去してから、第1層目のポリイミド樹脂層1aの上面の高
さまで電解メッキして所要の導電性金属柱5aを形成した
後、フォトレジストの除去および電極膜の除去を行う。
Further, an electrode film for forming a required connection metal pillar 5a by electrolytic plating is sputtered on the first polyimide resin layer 1a surface and the exposed first copper wiring layer 2a surface. , A photoresist is applied. This photoresist is patterned using a glass mask having a pattern smaller than the shape of the upper portion of the contact hole 3 '.
After removing the photoresist at the portion where the conductive metal column 5a is to be formed, the desired conductive metal column 5a is formed by electrolytic plating to the height of the upper surface of the first polyimide resin layer 1a. The removal of the resist and the removal of the electrode film are performed.

【0017】かくして、上記穿設・形成されたコンタク
トホール3′内に、所要の導電性金属柱5aを遊嵌的に貫
通・配置して接続部を構成した後、第2層目の銅配線層
2bを、第1層目のポリイミド樹脂層1a上および導電性の
金属柱5a上面ないし側面に形成する(図1(c) )。次い
で、前記第2層目の銅配線層2bを形成した面上に、前記
第1層目のポリイミド樹脂層1aの形成、コンタクトホ−
ル3′の形成、導電性金属柱5aの遊嵌的な貫通・配置に
よる接続部構成および第2層目の銅配線層2bを形成した
場合と同様にして、第2層目のポリイミド樹脂層(層間
絶縁層)1b、第3層目の銅配線層2cおよび第2層目のポ
リイミド樹脂層(層間絶縁層)1bに対応した導電性金属
柱5bの遊嵌的な貫通・配置などが行われる(図1(d)
)。
Thus, after the required conductive metal pillars 5a are freely penetrated and arranged in the contact holes 3 'formed and formed, a connection portion is formed, and then the copper wiring of the second layer is formed. layer
2b is formed on the first polyimide resin layer 1a and on the upper surface or side surface of the conductive metal column 5a (FIG. 1 (c)). Then, the first polyimide resin layer 1a is formed on the surface on which the second copper wiring layer 2b is formed, and the contact hole is formed.
In the same manner as in the case of forming the connection layer structure by forming the metal layer 3 ', the loosely penetrating and arranging of the conductive metal pillar 5a, and forming the second copper wiring layer 2b. (Interlayer insulating layer) 1b, conductive metal pillars 5b corresponding to the third copper wiring layer 2c and the second polyimide resin layer (interlayer insulating layer) 1b are freely inserted and penetrated. (Figure 1 (d)
).

【0018】さらに、多層化していく工程は、上記のプ
ロセスを繰り返す。このような工程により、前記したポ
リイミド樹脂層(層間絶縁層)1a,1b …に形成したコン
タクトホ−ル3′を埋め込む金属柱5a,5b …の側周面
は、この金属柱5a,5b …と同層のコンタクトホ−ル3′
内壁面を成す各ポリイミド樹脂層(層間絶縁層)1a,1b
…に直接接触することがなくなり、熱的なバッファ層6
が形成される。
Further, the above-described process is repeated for the step of forming a multilayer structure. By such a process, the side peripheral surfaces of the metal pillars 5a, 5b embedded with the contact holes 3 'formed in the polyimide resin layers (interlayer insulating layers) 1a, 1b. Contact hole 3 'in the same layer as
Each polyimide resin layer (interlayer insulating layer) 1a, 1b forming the inner wall
Is no longer in direct contact with the thermal buffer layer 6
Is formed.

【0019】上記では、導電性の金属柱5a,5b の形成に
電解メッキ法を用いたが、無電解メッキ法やMOCVD
による選択的な気相成長法などによってもよい。
In the above description, the electroplating method is used to form the conductive metal columns 5a and 5b.
Or a selective vapor phase growth method using the method described above.

【0020】[0020]

【発明の効果】以上説明したように本発明方法によれ
ば、銅/ポリイミド多層配線基板のコンタクトホ−ル
に、銅配線層間の接続用に金属柱を埋め込んだ構成にお
いて、従来問題となっていた金属柱とポリイミド樹脂絶
縁層(層間絶縁層)との剥離がなくなり、信頼性が飛躍
的に向上するとともに平坦化が実現され、超高速デバイ
スを実装する基板に要求される高周波特性を備えた多層
配線基板を容易に得ることが可能となる。
As described above, according to the method of the present invention, there has been a conventional problem in a structure in which metal pillars are embedded in a contact hole of a copper / polyimide multilayer wiring board for connection between copper wiring layers. The separation between the metal pillars and the polyimide resin insulating layer (interlayer insulating layer) is eliminated, the reliability is dramatically improved and the flattening is realized, and the high-frequency characteristics required for the substrate for mounting ultra-high-speed devices are provided. A multilayer wiring board can be easily obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る多層配線基板の製造方法の実施態
様例を模式的に示したもので、aは第1層目の層間絶縁
層まで形成した状態を示す断面図、bは第1層目の層間
絶縁層にコンタクトホール(接続用貫通孔)穿設形成し
た状態を示す断面図、cは第2層目の銅配線層までを形
成した状態を示す断面図、dは第3層目の銅配線層まで
を形成した状態を示す断面図。
FIG. 1 schematically shows an embodiment of a method for manufacturing a multilayer wiring board according to the present invention, wherein a is a cross-sectional view showing a state in which a first interlayer insulating layer is formed, and b is a first sectional view. FIG. 3C is a cross-sectional view showing a state in which a contact hole (through hole for connection) is formed in a second interlayer insulating layer; FIG. 4C is a cross-sectional view showing a state in which a second copper wiring layer is formed; Sectional drawing which shows the state which formed the copper wiring layer of the eye.

【図2】従来の銅配線層/ポリイミド樹脂絶縁層系の多
層配線基板の要部構成を示す断面図。
FIG. 2 is a cross-sectional view illustrating a configuration of a main part of a conventional multilayer wiring board based on a copper wiring layer / polyimide resin insulating layer.

【図3】従来の銅配線層/ポリイミド樹脂絶縁層系の多
層配線基板の他の要部構成を示す断面図。 1a,1b …層間絶縁層 2a,2b,2c…金属配線層(導体配
線層) 3、3′…コンタクトホール(接続用貫通
孔) 4…絶縁性支持基板 5a,5b …金属柱(充填
金属) 6…バッファ層
FIG. 3 is a cross-sectional view showing another essential configuration of a conventional copper wiring layer / polyimide resin insulating layer-based multilayer wiring board. 1a, 1b: interlayer insulating layer 2a, 2b, 2c: metal wiring layer (conductor wiring layer) 3, 3 ': contact hole (connection through hole) 4: insulating support substrate 5a, 5b: metal column (filled metal) 6 ... Buffer layer

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H05K 3/46 H05K 1/11 H05K 3/40 - 3/42 H01L 21/768 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H05K 3/46 H05K 1/11 H05K 3/40-3/42 H01L 21/768

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 支持基板の主面上に金属配線層およびポ
リイミド樹脂から成る層間絶縁層を順次形成する工程
と、前記形成される層間絶縁層の中所要の層間絶縁層に
接続用貫通孔を穿設する工程と、前記形成される接続用
貫通孔内に導電性金属柱を貫通・配置して所定の金属配
線層間を接続する工程を具備して成る多層配線基板の製
造方法において、前記接続用貫通孔を導電性金属柱の直
径より大きな径に穿設し、貫通孔内に導電性金属柱を遊
嵌的に貫通・配置して、次層の層間絶縁層を形成すると
きに遊嵌部をポリイミド樹脂で充填することを特徴とす
る多層配線基板の製造方法。
1. A step of sequentially forming a metal wiring layer and an interlayer insulating layer made of a polyimide resin on a main surface of a support substrate, and forming a connection through hole in a required interlayer insulating layer in the formed interlayer insulating layer. A method of manufacturing a multi-layer wiring board, comprising: a step of piercing; and a step of penetrating and arranging a conductive metal column in the formed connection through hole to connect predetermined metal wiring layers. The through hole is made larger than the diameter of the conductive metal column, and the conductive metal column is inserted through the through hole in a free-fit manner to form the next interlayer insulating layer. A method for manufacturing a multilayer wiring board, characterized in that a part is filled with a polyimide resin.
JP7139391A 1991-04-04 1991-04-04 Method for manufacturing multilayer wiring board Expired - Fee Related JP3182159B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7139391A JP3182159B2 (en) 1991-04-04 1991-04-04 Method for manufacturing multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7139391A JP3182159B2 (en) 1991-04-04 1991-04-04 Method for manufacturing multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH04307759A JPH04307759A (en) 1992-10-29
JP3182159B2 true JP3182159B2 (en) 2001-07-03

Family

ID=13459230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7139391A Expired - Fee Related JP3182159B2 (en) 1991-04-04 1991-04-04 Method for manufacturing multilayer wiring board

Country Status (1)

Country Link
JP (1) JP3182159B2 (en)

Also Published As

Publication number Publication date
JPH04307759A (en) 1992-10-29

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