JPS6370548A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPS6370548A JPS6370548A JP61216342A JP21634286A JPS6370548A JP S6370548 A JPS6370548 A JP S6370548A JP 61216342 A JP61216342 A JP 61216342A JP 21634286 A JP21634286 A JP 21634286A JP S6370548 A JPS6370548 A JP S6370548A
- Authority
- JP
- Japan
- Prior art keywords
- tie bar
- cut
- resin
- tie
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000011347 resin Substances 0.000 claims abstract description 26
- 229920005989 resin Polymers 0.000 claims abstract description 26
- 238000007789 sealing Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 5
- 238000005452 bending Methods 0.000 abstract description 6
- 230000002950 deficient Effects 0.000 abstract 2
- 230000002146 bilateral effect Effects 0.000 abstract 1
- 230000002035 prolonged effect Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、樹脂封止型半導体装置の組立工程において使
用されるリードフレームに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame used in the assembly process of a resin-sealed semiconductor device.
第４０は、集積回路（、ＩＣ）等に供される従来のリー
ドフレームの形状を示す斜視図である。リードフレーム
は、薄い金属条からエツチング処理又は金型による抜き
により、所定のパターンに形成される。第４図において
、１はアウタリード２間を接続するタイバ、３は樹脂中
に封止されるインナリード、４はチップをのせるダイス
パッドである。The 40th is a perspective view showing the shape of a conventional lead frame used for integrated circuits (ICs) and the like. The lead frame is formed into a predetermined pattern from a thin metal strip by etching or die cutting. In FIG. 4, 1 is a tie bar connecting the outer leads 2, 3 is an inner lead sealed in resin, and 4 is a die pad on which a chip is placed.
第５図は、ダイスパッド４にチップ５が接合され、チッ
プ５とインナリード３との間が電気的接続のために金線
等の細線６で接続された状態を示す斜視図である。この
後、チップ５は、熱硬化型樹脂により封止、成形される
。FIG. 5 is a perspective view showing a state in which the chip 5 is bonded to the die pad 4 and the chip 5 and the inner leads 3 are connected with a thin wire 6 such as a gold wire for electrical connection. Thereafter, the chip 5 is sealed and molded with a thermosetting resin.
成形後の状態を第６図に示す。同図において、７はタイ
バ１とアウタリード２により挾まれた所に成形された樹
脂（以下「ダムバリ」という）、８はパッケージである
。第６図に示すように、タイバ１はアウタリード２の変
形防止のための補強と樹脂封止時の樹脂の流出を防ぐ役
目がある。The state after molding is shown in FIG. In the figure, 7 is a resin (hereinafter referred to as a "dam burr") molded in the area sandwiched between the tie bar 1 and the outer lead 2, and 8 is a package. As shown in FIG. 6, the tie bars 1 serve to reinforce the outer leads 2 to prevent deformation and to prevent resin from flowing out during resin sealing.
この後、第７図に示すように、破線部９の抜き落としく
以下「タイバカット」という）、破線部１０のカット（
リードカット）および破線部１１のカット（ピンチカッ
ト）を行なうことにより、リード部分以外をリードフレ
ームより切り離し、第８図に示すようにリードを曲げる
ことにより最終外形を形成する。After this, as shown in FIG.
By performing a lead cut) and a cut along the broken line portion 11 (pinch cut), parts other than the lead portion are separated from the lead frame, and the final external shape is formed by bending the lead as shown in FIG.
従来のリードフレームにおいては、第７図に示すタイバ
カット時、金属部分であるタイバ１と樹脂からなるダム
バリアを同時に打ち抜くが、第９図、第１０図に示すよ
うに、ダムバリ周辺が残部１２ａ、１２ｂで示すように
樹脂側に残り、実際使用時にトラブルを引き起こす。ま
た、ダムバリア切断時の飛散くずによりリード曲げ時に
パリのかみこみが発生し、外観不良を生じる。タイバ１
と同時にダムバリアも打ち抜くため、樹脂中のフィシ（
シリカ）により刃物の摩耗が激しく、刃物の交換頻度が
多くなるという不具合を有していた。In a conventional lead frame, when cutting the tie bars shown in FIG. 7, the tie bars 1, which are metal parts, and the dam barrier made of resin are punched out at the same time, but as shown in FIGS. 9 and 10, the remaining parts 12a and 12b around the dam burrs are As shown in , it remains on the resin side and causes trouble during actual use. In addition, the scattered debris during cutting of the dam barrier causes biting of the edges during lead bending, resulting in poor appearance. Taiba 1
In order to punch out the dam barrier at the same time, the fissures in the resin (
Silica) caused severe wear on the blades, which caused the blades to have to be replaced more frequently.
本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、外観不良を生ぜず、刃物の寿命
を延ばすことができる半導体装置用リードフレームを得
ることにある。The present invention has been made in view of these points, and its purpose is to obtain a lead frame for a semiconductor device that does not cause poor appearance and can extend the life of a cutter.
このような目的を達成するために本発明は、樹脂封止型
半導体装置の組立工程に使用されるリードフレームにお
いて、封止樹脂より外側のアウタリード間をつなぐタイ
バを設け、このタイバの内側を封止樹脂側面に接近させ
、アウタリード近傍のタイバ内に２個の穴を設け、この
穴と封止樹脂側面との間の最終的にタイバを切り離す位
置にシャーカットを設けるようにしたものである。In order to achieve such an object, the present invention provides a lead frame used in the assembly process of a resin-sealed semiconductor device, in which a tie bar is provided that connects the outer leads outside the sealing resin, and the inside of this tie bar is sealed. Two holes are provided in the tie bar near the outer lead, close to the side surface of the sealing resin, and a shear cut is provided at a position where the tie bar is finally separated between the holes and the side surface of the sealing resin.
本発明においては、パリによる曲げ時のかみこみが゛な
く、外観不良が生じない。また、タイバカ７トの刃は金
属部のみ打ち抜（ので、刃の寿命を延ばすことができる
。In the present invention, there is no biting due to paris during bending, and no appearance defects occur. In addition, only the metal part of the blade is punched out (so the lifespan of the blade can be extended).
第１図は本発明に係わる半導体装置用リードフレームの
一実施例の部分図であり、第２図は第１図のＡ部拡大図
である。第１図、第２図において、２はアウタリード、
１３はタイバ、１３ａおよび１３ｂはタイバ１３の内側
および外側、１４は穴、１５はシャーカット、１６はタ
イバカットパンチの刃でカットされる部分を示す破線部
、１７はダムバリ、１８は封止樹脂としてのパッケージ
である。FIG. 1 is a partial view of one embodiment of a lead frame for a semiconductor device according to the present invention, and FIG. 2 is an enlarged view of section A in FIG. In Figures 1 and 2, 2 is an outer lead;
13 is a tie bar, 13a and 13b are inside and outside of the tie bar 13, 14 is a hole, 15 is a shear cut, 16 is a broken line part indicating the part to be cut with the blade of a tie bar cut punch, 17 is a dam burr, and 18 is a sealing resin It is a package as.
第１図、第２図に示すように、タイバ１３の内側１３ａ
をパフケージ１８に近づけ、フレーム寸法公差等で発生
する封止工程での位置ずれによるタイバ１３のパッケー
ジ１８中への食い・込みのない程度のすきまをあけてお
（。通常このすきまは０．１ｍｍ程度以下なので、ダム
バリ１７として残ったとしても全（問題にならない。ま
た、アウタリード２の近傍のタイバ１３内の穴１４を１
つの接続部に２個設け、内側１３ａに近い部分のタイバ
１３の左右両側を破線部１６で示すタイバカットの幅又
はこれに近い寸法の幅でシャーカットし、アウタリード
２と切り離し、このシャーカット１５でタイバ１３とア
ウタリード２とがすきまない状態で接するようにする。As shown in FIGS. 1 and 2, the inner side 13a of the tie bar 13
Close the puff cage 18 and leave a gap that will prevent the tie bar 13 from digging into the package 18 due to positional deviation during the sealing process caused by frame dimensional tolerances (normally, this gap is 0.1 mm). Even if the dam burr 17 remains, it will not be a problem.Also, if the hole 14 in the tie bar 13 near the outer lead 2 is
The left and right sides of the tie bar 13 near the inner side 13a are shear cut with the width of the tie bar cut indicated by the broken line part 16 or a width close to this, and separated from the outer lead 2. The tie bar 13 and the outer lead 2 are brought into contact with each other without any gap.
上述したようなリードフレームを用いて樹脂封止を行な
うと、樹脂はタイバ１３の内側１３ａで止められ、かつ
、シャーカット１５でタイバ１３とアウタリード２とは
すきまなく接しているため、樹脂の流出はない。次に、
タイバカットの刃で、破線部１６に示すように、タイバ
１３を穴１４を介して切断することにより、タイパ１３
全体がアウタリード２より切り離される。次にリード曲
げを行なう。リードを曲げた状態を第３図に示す。When resin sealing is performed using the lead frame as described above, the resin is stopped at the inner side 13a of the tie bar 13, and the tie bar 13 and the outer lead 2 are in contact with each other at the shear cut 15 without any gaps, so the resin does not leak out. There isn't. next,
The tie bar 13 is cut by cutting the tie bar 13 through the hole 14 as shown by the broken line 16 with a tie bar cutting blade.
The whole is separated from the outer lead 2. Next, bend the leads. Figure 3 shows the state in which the leads are bent.
上述の実施例においては、デュアルインライン型のＩＣ
について説明したが、本発明はこれに限らず、タイバを
有する樹脂封止型の半導体装置全般に適用できると共に
、半導体装置以外でも、タイバに類する樹脂流れ止めを
有し、最終的にはこの樹脂流れ止めを取り除くものにつ
いては応用が可能である。In the above embodiment, a dual in-line type IC is used.
However, the present invention is not limited to this, and can be applied to general resin-sealed semiconductor devices having tie bars. It can be applied to anything that removes the flow stopper.
以上説明したように本発明は、封止樹脂より外側のアウ
タリード間をつなぐタイバを備え、このタイバの内側を
封止樹脂側面に接近させ、アウタリード近傍のタイバ内
に２個の穴を設け、この穴と封止樹脂側面との間の最終
的にタイバを切り離す位置にシャーカットを設けたこと
により、ダムバリ残りがなくなるので実際の使用時にダ
ムバリの落下によるトラブルを防ぐことができ、ダムバ
リを切断しないのでダムバリの飛散による曲げ時のかみ
こみがなく外観不良がなくなり、またパリのかみこみに
よる接触不良が発生しないという効果がある。また、タ
イバカットの刃は金属部のみ打ち抜くため、刃の寿命を
延ばす効果がある。As explained above, the present invention includes a tie bar that connects the outer leads outside the sealing resin, brings the inside of the tie bar close to the side surface of the sealing resin, and provides two holes in the tie bar near the outer lead. By providing a shear cut at the position where the tie bar is finally separated between the hole and the side of the sealing resin, there is no remaining dam burr, which prevents troubles due to the dam burr falling during actual use, and does not cut the dam burr. Therefore, there is no appearance defect due to the scattering of the dam burr during bending, and there is also no contact failure due to the dam burr being bitten. Additionally, since the tie-bar cut blade only punches out the metal part, it has the effect of extending the life of the blade.
第１図は本発明に係わる半導体装置用リードフレームの
一実施例の一部を示す部分平面図、第２図は第１図のＡ
部拡大図、第３図はリード曲げの状態を示す部分斜視図
、第４図および第５図は従来の半導体装置用リードフレ
ームを示す斜視図、第６図は半導体装置を樹脂封止した
状態の従来のリードフレームを示す斜視図、第７図は従
来の半導体装置用リードフレームを示す平面図、第８図
は半導体装置の最終外形を示す斜視図、第９図は従来の
半導体装置用リードフレームにおけるダムバリの残部を
示す部分平面図、第１０図はそのリード曲げの状態を示
す部分斜視図である。
２・・・アウタリード、１３・・・タイバ、１３ａ・・
・内側、１３ｂ・・・外側、１４・・・穴、１５・・・
シャーカット、１６・・・破線部、１７・・・ダムバリ
、１８・・・パッケージ。FIG. 1 is a partial plan view showing a part of an embodiment of a lead frame for a semiconductor device according to the present invention, and FIG.
3 is a partial perspective view showing a lead bent state, FIGS. 4 and 5 are perspective views showing a conventional lead frame for a semiconductor device, and FIG. 6 is a state in which a semiconductor device is sealed with resin. 7 is a plan view showing a conventional lead frame for semiconductor devices, FIG. 8 is a perspective view showing the final external shape of the semiconductor device, and FIG. 9 is a conventional lead frame for semiconductor devices. FIG. 10 is a partial plan view showing the remaining part of the dam burr in the frame, and a partial perspective view showing the bent state of the lead. 2... Outer lead, 13... Tie bar, 13a...
・Inside, 13b...outside, 14...hole, 15...
Shear cut, 16...broken line part, 17...damburi, 18...package.
Claims (1)
フレームにおいて、封止樹脂より外側のアウタリード間
をつなぐタイバを備え、このタイバは、内側が前記封止
樹脂側面に接近し、前記アウタリード近傍に設けられた
２個の穴を有し、この穴と前記封止樹脂側面との間の最
終的にタイバを切り離す位置にシャーカットを有するこ
とを特徴とする半導体装置用リードフレーム。A lead frame used in the assembly process of a resin-encapsulated semiconductor device includes a tie bar that connects outer leads outside the encapsulating resin, and the tie bar has an inner side close to the side surface of the encapsulating resin and a tie bar that connects the outer leads in the vicinity of the outer lead. 1. A lead frame for a semiconductor device, comprising two holes, and a shear cut at a position where the tie bar is finally separated between the holes and the side surface of the sealing resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61216342A JPS6370548A (en) | 1986-09-12 | 1986-09-12 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61216342A JPS6370548A (en) | 1986-09-12 | 1986-09-12 | Lead frame for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6370548A true JPS6370548A (en) | 1988-03-30 |
| JPH0545063B2 JPH0545063B2 (en) | 1993-07-08 |
Family
ID=16687046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61216342A Granted JPS6370548A (en) | 1986-09-12 | 1986-09-12 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6370548A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0298165A (en) * | 1988-10-05 | 1990-04-10 | Goto Seisakusho:Kk | Lead frame for electronic component and manufacture of electronic component using the same |
| JPH03257836A (en) * | 1990-03-07 | 1991-11-18 | Rohm Co Ltd | Mold formation for synthetic resin-sealed electronic component |
| JPH04121755U (en) * | 1991-04-22 | 1992-10-30 | ローム株式会社 | Structure of lead frame for electronic components |
| US5821610A (en) * | 1995-01-18 | 1998-10-13 | Nec Corporation | Leadframe allowing easy removal of tie bars in a resin-sealed semiconductor device |
| US6444905B1 (en) * | 1998-12-24 | 2002-09-03 | Hitachi, Ltd. | Semiconductor device |
| US20130341779A1 (en) * | 2012-06-25 | 2013-12-26 | Mitsubishi Electric Corporation | Method of manufacturing a semiconductor device and semiconductor device |
| CN116690399A (en) * | 2023-08-07 | 2023-09-05 | 烟台一诺电子材料有限公司 | Bonding wire polishing coating integrated device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS525584U (en) * | 1975-06-27 | 1977-01-14 | ||
| JPS533011U (en) * | 1976-06-25 | 1978-01-12 | ||
| JPS5988854A (en) * | 1982-11-12 | 1984-05-22 | Toshiba Corp | Semiconductor device |
| JPS59134857A (en) * | 1983-01-21 | 1984-08-02 | Toshiba Corp | Semiconductor device |
| JPS6123348A (en) * | 1984-07-12 | 1986-01-31 | Nec Corp | Resin sealing type semiconductor device |
-
1986
- 1986-09-12 JP JP61216342A patent/JPS6370548A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS525584U (en) * | 1975-06-27 | 1977-01-14 | ||
| JPS533011U (en) * | 1976-06-25 | 1978-01-12 | ||
| JPS5988854A (en) * | 1982-11-12 | 1984-05-22 | Toshiba Corp | Semiconductor device |
| JPS59134857A (en) * | 1983-01-21 | 1984-08-02 | Toshiba Corp | Semiconductor device |
| JPS6123348A (en) * | 1984-07-12 | 1986-01-31 | Nec Corp | Resin sealing type semiconductor device |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0298165A (en) * | 1988-10-05 | 1990-04-10 | Goto Seisakusho:Kk | Lead frame for electronic component and manufacture of electronic component using the same |
| JPH03257836A (en) * | 1990-03-07 | 1991-11-18 | Rohm Co Ltd | Mold formation for synthetic resin-sealed electronic component |
| JPH04121755U (en) * | 1991-04-22 | 1992-10-30 | ローム株式会社 | Structure of lead frame for electronic components |
| US5821610A (en) * | 1995-01-18 | 1998-10-13 | Nec Corporation | Leadframe allowing easy removal of tie bars in a resin-sealed semiconductor device |
| US6444905B1 (en) * | 1998-12-24 | 2002-09-03 | Hitachi, Ltd. | Semiconductor device |
| US6541702B2 (en) | 1998-12-24 | 2003-04-01 | Hitachi, Ltd. | Semiconductor device |
| US6553657B2 (en) | 1998-12-24 | 2003-04-29 | Hitachi, Ltd. | Semiconductor device |
| US6777262B2 (en) | 1998-12-24 | 2004-08-17 | Renesas Technology Corp. | Method of packaging a semiconductor device having gull-wing leads with thinner end portions |
| US20130341779A1 (en) * | 2012-06-25 | 2013-12-26 | Mitsubishi Electric Corporation | Method of manufacturing a semiconductor device and semiconductor device |
| US8859338B2 (en) * | 2012-06-25 | 2014-10-14 | Mitsubishi Electric Corporation | Method of manufacturing a semiconductor device and semiconductor device |
| DE102013200944B4 (en) * | 2012-06-25 | 2020-10-15 | Mitsubishi Electric Corp. | Method of manufacturing a semiconductor device and semiconductor device |
| CN116690399A (en) * | 2023-08-07 | 2023-09-05 | 烟台一诺电子材料有限公司 | Bonding wire polishing coating integrated device |
| CN116690399B (en) * | 2023-08-07 | 2023-09-26 | 烟台一诺电子材料有限公司 | Bonding wire polishing coating integrated device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0545063B2 (en) | 1993-07-08 |
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