JPS63683A - Interpolation enlargement arithmetic circuit - Google Patents

Abstract

PURPOSE:To obtain an interpolation enlargement arithmetic circuit for outputting enlarged image information in various interpolation enlargement methods by at least one piece of arithmetic processing circuit, by constituting said circuit so that a kind of its arithmetic operation can be controlled by a control circuit without limiting an interpolation enlargement arithmetic operation. CONSTITUTION:An arithmetic designating signal for designating an arithmetic processing is applied to an arithmetic processing circuit 1 from a controlling circuit 2. By this designating signal, the arithmetic circuit 1 executes an interpolation enlargement processing to an input image data Dn for constituting (m)X(n) picture elements, and outputs an interpolation enlarged image data On for constituting MXN images. For instance, when the circuit is constituted in advance so that segmenting of 4X4 picture elements and the arithmetic operation can be executed, an interpolation enlargement arithmetic operation in 2X2 picture elements, 3X3 picture elements, and 4X4 picture elements can be executed optionally, and also, an interpolation enlarging circuit which can execute optionally its arithmetic processing is obtained.

Description

[Detailed Description of the Invention] [Summary] Image enlargement processing is limited by the fabricated arithmetic circuit. The present invention specifies the arithmetic processing of added image information using a control circuit, thereby enabling various arithmetic processing.

[Industrial application field]

The present invention relates to an image processing device, and more particularly to an interpolation and enlargement calculation circuit that interpolates and enlarges image information.

[Traditional technique]

With the development of ICs and even LSIs, it has become possible to store and process large amounts of information, such as image information.

Generally, image information is composed of mxn pixels,
For example, when displaying on a display device capable of displaying with high precision, image information must be enlarged.

For example, in the case of a display device having double the display density on the - side, one dot of image information must be displayed by allocating it to 2×2 dots.7 dots, that is, 4 dots. If one dot is simply assigned to four dots as the same information, the four dots will become one pixel in the displayed image despite the high precision display. In order to prevent this, conventionally, image information is expanded by interpolation.

[Problem that the invention seeks to solve]

Even one image contains a large amount of image information, and a dedicated arithmetic circuit is generally provided when performing enlargement interpolation.

Various methods of enlarging interpolation have been reported, but as described above, only one type of calculation can be performed because the processing is performed by a dedicated calculation circuit.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks of the conventional art, it is an object of the present invention to provide an interpolation and enlargement calculation circuit that makes it possible to obtain enlarged image information using various interpolation and enlargement methods using at least one calculation processing circuit.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

m x n input image data Dn are sequentially added to l, and m
An arithmetic processing circuit that sequentially outputs ×N interpolated enlarged image data On; 2 is a control circuit that applies an arithmetic designation signal to the arithmetic processing circuit 1;

[For production]

The arithmetic processing circuit 1 receives an arithmetic designation signal from the control circuit 2 that designates arithmetic processing. In response to this designation signal, the arithmetic circuit 1 performs interpolation and enlargement processing on the input image data Dn forming mxn pixels, and outputs interpolation enlarged image data On forming an MxN image.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a detailed circuit configuration diagram of an embodiment of the present invention.
It consists of arithmetic circuits 3 to 6 and a control circuit 7. Arithmetic circuit 3
Inputs D+-Da are added to inputs D+-Da and 6, respectively. Further, an arithmetic control signal from the control circuit 7 is applied to the arithmetic circuits 3 to 6.

The embodiment of the present invention shown in FIG. 2 is a circuit that interpolates and expands 3×3 image data to 6×6 image data. FIG. 3(a) is a diagram for explaining image data of 3×3 pixels, and FIG. 3(b) is a diagram for explaining image data of 6×6 pixels.

In the embodiment of the present invention, 2 x 2 pixels out of 3 x 3 pixels in Fig. 3 fa) are used to process 2 x 2 pixel data in Fig. Created by 4(a) to 12(a) are diagrams for explaining 2×2 pixel cutout data to be added to the arithmetic processing circuits 3 to 6, and FIG. 4(b) to FIG. 12 (bl is the It is an explanatory diagram in which 2×2 pixel interpolated enlarged data obtained by arithmetic processing of the cut out data by the above-mentioned arithmetic processing circuits 3 to 6 is stored in a corresponding position.As mentioned above, 3×
The image data of three pixels are adjacent to each other on the top, bottom, left and right, that is, C
1l・C12・C21・C22, C12・C13・C2
1・C23, C13・C23, C21・C22・C31
・C32, C22・C23・C32・C33, C23・
C33, C31/C32, C32/C33, and C33 are sequentially cut out, read out from a hit image memory (not shown), and added to arithmetic processing circuits 3-6. Then, 41x2 (2×2) interpolated enlarged data is obtained from these image data and outputted as 01 to 04. This output 0+~04 is 6×6 pixel image data Sll, S12, S13, S1
4, S21 ・S22 ・S23 ・S24. S
31・332. S33 ・334. S41 ・
S42・S43・S44. S51 ・S52 ・
S53 ・S54゜S61 ・S62 ・363
・S64.571-372 ・S73 ・S74. S
81 ・S82 ・S83 ・384.391・
They correspond to S92, S93, and S94, respectively. still,
In the case of a pixel that does not exist at the right end or bottom end of the 2×2 pixel data, the arithmetic processing circuits 3 to 6 perform calculations using, for example, blank data.

Each of the arithmetic circuits 3 to 6 has 4 pieces of extracted data added to it, and 1 (pixel) image data is obtained from this 4 pieces of data. The control circuit 7 performs calculations to obtain interpolated enlarged data.
It is determined by the calculation control signal from.

FIG. 13 is a detailed circuit diagram of the arithmetic processing circuit 3.

Input data D+=Dt is added correspondingly to arithmetic circuits 8-11. Arithmetic circuits 8 to 11 will be described later, but include multipliers,
It has an adder and a divider.

From the control circuit 7, random access memory (RAM)
12, address signals AD+ to AD3 and data signals DX+ to DX4 are added, and data necessary for calculations, such as addends, multipliers, divisors, etc., are stored. Then, the data specified by the address signals AD+ to AD3 are applied to the arithmetic circuits 8 to 11. Using this constant, the arithmetic circuit is
Perform addition, multiplication, division, etc. The arithmetic circuits 8 to 11 receive selection signals SE + and SE2 from the control circuit 7, and the arithmetic circuits 8 to 11 receive selection signals SE1. The calculation result indicated by SE2 is selected and added to the synthesis circuit 13.

The synthesis circuit 13 is a circuit that performs fixed calculations, for example, 4
The calculation results added from the calculation circuits 8 to 11 are accumulated and outputted as one pixel data of interpolated enlargement. The arithmetic processing circuits 4 to 6 are also similar circuits, and these four circuits each obtain data O+''Ot for one pixel.

FIG. 14 is a detailed circuit diagram of the arithmetic circuit 8. Input data, ie, one piece of data D1 of 2×2 pixels, is applied to a multiplier 14, an adder 15, and a divider 16. Then, the 11-bit data outputted from the random access memory 12 is transferred to the multipliers 14, 14, and 11 through the registers 17, 18, and 19, respectively. It is added to an adder 15 and a divider 16. The multiplier 14 is a circuit that multiplies the input data D1 and the data added from the register 17, the adder 15 is a circuit that adds the input data DI and the data added from the register 18, and the divider 1
6 is a circuit that divides the input data D1 by the contents of the register 19;

The registers 17 to 19 are connected so that data from the random access memory 12 is commonly applied, but since the registers 17 to 19 are connected with a capture clock signal (not shown), the data is output from the random access memory 12. Import the calculated data. By this import, constants in operations such as multiplication, addition, and division described above can be set to different values. These multipliers 14
The results calculated by the adder 151 and the divider 16 are selected by the selector 20 and synthesized by the above-mentioned synthesis circuit 13. The selector 20 sequentially selects, for example, a multiplication result, an addition result, and a division result based on the selection signals SEI and SE2 output from the control circuit 7, and the synthesis circuit 13 selects the result selected using the selection signals SEI and SE2 output from the control circuit 7. Combine the calculated results. Although FIG. 14 shows a detailed circuit of the arithmetic circuit 8, the arithmetic circuits 9, 10, and 11 in FIG. 13 are similar, and four interpolated enlarged data are obtained by these circuits 8-11.

Constants for each of these calculations are stored in advance in the random access memory 12, and address signals AD+ to AD
3 and stored in the respective registers 17 to 19, and further, under the control of the control circuit 7, an operation for one piece of image data is selected and synthesized by the synthesis circuit 13. Therefore, the synthesis circuit 1 obtained by the synthesis circuit 13
The interpolated enlarged data for one dot outputted from 3 is the calculation result taking into consideration the four cut out image data.

This calculation result can be selected with the selector 20, and
Constants in calculations can also be used as target values, so
The interpolated enlarged data obtained from the synthesis circuit 13 is not determined by each circuit, but by various signals output from the control circuit. That is, by changing the constants necessary for the control and calculation of the control circuit, it is possible to obtain enlarged image data using various interpolation and enlargement methods.

Although the image data of each input and each output in FIGS. 2, 13, and 14 is represented by a single line, this represents not 1 bit data but multiple bit data. Further, this processing is controlled by a circuit (not shown) so that it is performed not only for black and white, but also for each of the three primary colors, for example.

In the embodiment of the present invention shown in FIG. 2, 3x3 pixel image data is cut out into 2x2 pixels to obtain 2x2 pixel enlarged data. If the configuration is configured to allow pixel extraction and calculation, 2×
An interpolation and expansion circuit that can arbitrarily perform interpolation and expansion calculations on 2 pixels, 3×3 pixels, and 4×4 pixels, and can also perform the calculation process as desired, is made possible.

〔Effect of the invention〕

As described above, the present invention does not limit the interpolation enlargement operation, and the type of operation can be controlled by the control circuit. An interpolation and expansion calculation circuit that outputs information can be obtained.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a circuit configuration diagram of an embodiment of the present invention, Fig. 3 (a) is a diagram explaining image data of 3 x 3 pixels, Fig. 3 (b) Figure 4(a) is a diagram explaining 6x6 pixel image data, Figure 4(a) is a diagram explaining 2x2 pixel cutting, and Figure 4('b) is a diagram explaining 2x2 pixel interpolation enlargement. , FIG. 5(a) is a diagram explaining the extraction of 2×2 pixels.
Figure (b) is a diagram explaining interpolation expansion of 2 × 2 pixels, Figure 6 (al is a diagram explaining cutting out of 2 × 2 pixels, Figure 6 (
b) is a diagram explaining interpolation enlargement of 2×2 pixels, and Fig. 7(a)
) is a diagram explaining the extraction of 2×2 pixels, and Figure 7 (bl
is a diagram explaining interpolation enlargement of 2 × 2 pixels, Figure 8 + 8) is a diagram explaining extraction of 2 × 2 pixels, and Figure 8 (b) is 2 × 2 pixels.
A diagram explaining the interpolation enlargement of ×2 pixels, Figure 9+a) is 2 ×
A diagram explaining the extraction of two pixels, FIG. 9(b) is 2×2
A diagram explaining the interpolation enlargement of pixels, Figure 10 (a) is 2 × 2
Figure 10 (bl is a diagram explaining interpolation expansion of 2 × 2 pixels, Figure 11 (al is a diagram explaining extraction of 2 × 2 pixels, Figure 11 (bl is a diagram explaining 2 × 2 pixel extraction), Figure 12 (a) is a diagram explaining the interpolation enlargement of ×2 pixels, Figure 12 (a) is a diagram explaining the extraction of 2 × 2 pixels, Figure 12 (mountain) is a diagram explaining the interpolation enlargement of 2 × 2 pixels, Figure 13 14 is a detailed circuit diagram of the arithmetic processing circuit, and FIG. 14 is a detailed circuit diagram of the arithmetic processing circuit. 1... Arithmetic processing circuit, 2... Control circuit. Patent applicant: Fujitsu Limited Fig. 1 Figure 2, (b) Figure 3 (86) (q) (b) Figure 4 (G) (b) Figure 5 ((2) ( b) Fig. 6 (()) (b) Fig. 7 Fig. 8 2x2 end of the sword 2x2 thread - table use ゛Darkness crowns the people Sun Moon TRO I\]hs<C1 T1 times a month (()
) (b) Fig. 9 2x24 rare cut melon 2 x 2# Imenme talent and wide range of talent (, SL morning map Harmful sun and moon figure (0) (b) Fig. 10 Mifu is Tsuki 1Z is also a figure.The name of the moon is 1.
2nd date of death, plot (0) (b) Figure 12 Figure 13 Figure 14

Claims (1)

[Scope of Claims] At least one arithmetic processing circuit (1) that adds image information composed of m×n pixels, performs arithmetic processing, and outputs image information of M×N pixels; 1. An interpolation and expansion calculation circuit comprising: a control circuit (2) for specifying calculation contents of calculation processing in the calculation processing circuit (1).