JP2568179B2 - Interpolation enlargement calculation circuit - Google Patents

Description

DETAILED DESCRIPTION [Overview] In image enlargement interpolation, a large amount of time is required to calculate the entire screen because a plurality of pixel data are sequentially read and calculated. According to the present invention, at least one line of image data is stored in a line buffer, pixel data required for calculation is read out and calculated almost simultaneously, and the obtained image data is stored in an output line buffer almost at the same time to perform calculation processing. Is trying to speed up.

[Industrial applications]

The present invention relates to an image processing device, and more particularly, to an interpolation enlargement calculation circuit that interpolates and enlarges image information.

[Prior art]

Generally, image information is composed of m × n pixels,
For example, when displaying on a display device capable of high precision display, the image information must be enlarged.

For example, in the case of a display device in which one side has a double display density, one dot of image information must be assigned to 2 × 2 dots, that is, 4 dots for display. If one dot is simply assigned to four dots as the same information, the four dots will be one pixel in the display image even though the display is highly accurate. In order to prevent this, conventionally, interpolation enlargement of image information is performed.

There are various methods of interpolation enlargement, but generally, one column of image information composed of m × n pixels is interpolated and enlarged into a plurality of columns of image information composed of M × N pixels, and A method of performing sequential interpolation enlargement, such as enlargement of input m × n pixel information for one column and conversion to image information for a plurality of columns composed of M × N pixels, is often used.

[Problems to be solved by the invention]

In the above-described conventional interpolation enlargement method, in order to obtain the interpolation enlargement information of M × N pixels, the information of m × n pixels must be read and processed in pixel units. Also, the obtained M ×
In order to store the interpolation enlargement information of N pixels in the frame memory or the like, it is necessary to store it in units of pixels.

Therefore, even if the interpolation enlargement calculation process can be performed at high speed, if the process for the entire screen is performed, the process will be slow.

In view of the above-mentioned conventional drawbacks, it is an object of the present invention to provide an interpolation enlargement calculation circuit that performs interpolation enlargement processing of the entire screen at high speed.

[Means for solving problems]

 FIG. 1 is a block diagram of the principle of the present invention.

Reference numeral 1 is a line buffer to which at least one pixel data of image information composed of m × n pixels is added from an input terminal IN, and the data is sequentially shifted to output pixel data of plural dots in parallel. Reference numeral 2 is a line buffer. It is an interpolation enlargement calculation circuit that outputs interpolation enlargement data of a plurality of pixels of image information forming M × N pixels by using the pixel data of a plurality of dots output from the above.

[Action]

At least one image data of image information composed of m × n pixels is sequentially applied to the input terminal IN, and the line buffer 1 sequentially shifts the data. Then, the interpolation enlargement circuit 2 outputs in parallel data to be subjected to interpolation enlargement, for example, data of k × l pixels in a specific range of m × n pixels.
The output data is added to the interpolation enlargement calculation circuit 2 to create and output the interpolation enlargement data. The output interpolation enlarged data is data that constitutes image information composed of M × N pixels, and since image data in a specific range unit is sequentially added, pipeline processing becomes possible.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a circuit configuration diagram of an embodiment of the present invention. The image data forming the m × n pixels are sequentially applied to the input terminal IN in pixel units as the pixels forming the image are scanned one row after the other and one row next. Then, it is input to the shift register 3 of the h stage and the shift register 4 of the two stages, and sequentially shifted by the basic clock applied from the control circuit 6. For example, when m pieces of pixel data are added, m pieces of pixel data, that is, data of one horizontal row forming an image are stored in the shift register 3.

The output of the shift register of the h stage is added to the shift register 5 of the two stages. In the embodiment of the present invention, blank data is added to the final data of one row of image information, that is, the m pieces of image information, and the final image information is processed. As will be described later, for example, one blank pixel data is required when processing 2 × 2. That is, the h-stage shift register is a (m + 1) -stage shift register. Therefore, horizontal 1
When two pieces of pixel data are input after the column data (including blank data) is stored in the shift register 3, the first input pixel data and the next input data are input to the shift register 5. Is stored. Further, the shift register 4 stores the first and second pixel data of the pixel data of the second stage. For example, as shown in FIG. 4 (a), when the pixel data is 3 × 3, three pieces of data C11, C1
After 2, C13 are stored in the h-stage shift register 3, two pieces of data C11, C12 are stored in the two-stage shift register 5 at two clocks, and at the same time, two pieces of data after m pieces are stored.
C21 and C22 are stored in the two-stage shift register 4. That is, the data C11, C12, C21, C22 is stored in the two-stage shift registers 4 and 5.
Is stored. Then, at the next clock, the data C12 and C13 in the two-stage shift register 5 and the data C2 in the two-stage shift register 4
It will be 2, C23. In the embodiment of the present invention, which will be described later, four interpolated enlargements are performed with four combined data, and four interpolated enlargements are performed with four data obtained by shifting pixels to the right. Then, the capturing process is sequentially performed.

The above-mentioned four data are sequentially added to the interpolation enlargement circuit 7. FIG. 3 is a detailed circuit diagram of the interpolation / expansion arithmetic circuit 7, which is composed of four arithmetic circuits 13 to 16 and a control circuit 7. Inputs D _{1 to} D ₄ are added to the arithmetic circuits 13 to 16, respectively. Then, the arithmetic control signals from the control circuit 17 are further applied to the arithmetic circuits 13 to 16.

The embodiment of the present invention shown in FIG. 3 is a circuit for interpolating and expanding 3 × 3 image data into 6 × 6 image data. FIG. 4 (a) is a diagram for explaining image data of 3 × 3 pixels, and FIG. 4 (b) is a diagram for explaining image data of 6 × 6 pixels.

In the embodiment of the present invention, 2 × 2 pixels among the 3 × 3 pixels in FIG. 4 (a) are used and 2 × 2 pixels in FIG. 4 (b) are used.
Data of two pixels are created by the arithmetic processing circuits 13 to 16 shown in FIG. FIGS. 5 (a) to 13 (a) are diagrams for explaining the cutout data of 2 × 2 pixels added to the arithmetic processing circuits 13 to 16, and FIGS. 5 (b) to 13 (b) are It is explanatory drawing which stores the interpolation expansion data of 2x2 pixel obtained by arithmetically processing the cut-out data by the arithmetic processing circuits 13-16 mentioned above in a corresponding position. 3x as described above
The image data of 3 pixels are adjacent vertically and horizontally, that is, C1
1 / C12 / C21 / C22, C12 / C13 / C21 / C23, C13 / C23, C21 /
C22 / C31 / C32, C22 / C23 / C32 / C33, C23 / C33, C31 / C3
2, C32, C33, C33 are sequentially cut out, that is, read from an image memory (not shown), and the h-stage register 3 and the 2-stage register 4,
5 is added to the arithmetic processing circuits 13 to 16. And
From these image data, four (2 × 2) interpolation enlargement data are obtained and output O _{1 to} O ₄ . This output O _{1 to} O ₄ is 6 × 6
Pixel image data S11 ・ S12 ・ S13 ・ S14, S21 ・ S22 ・ S23 ・
S24, S31 / S32, S33 / S34, S41 / S42 / S43 / S44, S51 / S52
・ S53 ・ S54, S61 ・ S62 ・ S63 ・ S64, S71 ・ S72 ・ S73 ・ S74, S
It corresponds to 81, S82, S83, S84, S91, S92, S93, S94 respectively. In addition, in the case of a pixel that does not exist at the right end or the lower end of the data of 2 × 2 pixels, for example, blank data is used and the arithmetic processing circuits 3 to 6 perform the arithmetic operation.

Each of the arithmetic circuits 3 to 6 is added with four pieces of cut out data, and one piece (pixel) from the four pieces of data is added.
Are seeking image data. The calculation for obtaining one interpolation enlarged data from the four image data is determined by the calculation control signal from the control circuit 7.

FIG. 14 is a detailed circuit configuration diagram of the arithmetic processing circuit 3.
Input data D _{1 to} D ₄ are added corresponding to the arithmetic circuits 18 to 21. The arithmetic circuits 18 to 21, which will be described later, are multipliers, adders,
It has a divider.

Random access memory (RAM) 22 from control circuit 7
On the other hand, address signals AD _{1 to} AD ₃ and data signals DX _{1 to} DX ₄ are added, and data necessary for calculation, such as an addend, a multiplier,
A divisor, etc. is stored. Then, the data having the content designated by the address signals AD _{1 to} AD ₃ is added to the arithmetic circuits 18 to 21. The arithmetic circuits 18 to 21 perform addition, multiplication, division, etc. using this constant. The arithmetic circuits 18 to 21 are selected signals SE from the control circuit 17.
₁ and SE ₂ are added, and the arithmetic circuits 18 to 21 use the selection signal S
The calculation result designated by E ₁ and SE ₂ is selected and added to the synthesis circuit 23. The synthesizing circuit 23 is a circuit for performing a fixed operation, for example, accumulates the operation results added from the four operation circuits 18 to 21 and outputs the result as one pixel data for interpolation enlargement. The arithmetic processing circuits 14 to 16 are also similar circuits, and the data O _{1 to} O ₄ of each one pixel are obtained by these four circuits, respectively.

FIG. 15 is a detailed circuit configuration diagram of the arithmetic circuit 18. Input data, that is, one data D _{1 of} 2 × 2 pixels is a multiplier
It is added to 24, adder 25, and divider 26. Then, one piece of data output from the random access memory 22 is added to the multiplier 24, the adder 25, and the divider 26 via the registers 27, 28, and 29, respectively. The multiplier 24 is a circuit for multiplying the data applied from the input data D ₁ and the register 27, the adder 25 is a circuit for adding the data applied from the input data D ₁ and the register 28, divider 26 is input data D ₁ register 29 It is a circuit that divides by the contents of.

The registers 27 to 29 are connected so that the data from the random access memory 22 are commonly added, but the register 27 to 29 has an input clock signal (not shown). Capture the calculated data. By this capture, the constants in the above-mentioned operations such as multiplication, addition, and division can have different values. These multipliers 24, adders 2
5. The result calculated by the divider 26 is selected by the selector 30 and combined by the combining circuit 23 described above. Selector 30
Is the selection signal SE _1, SE _2, for example, by sequentially multiplication result output from the control circuit 17, the addition result, and select the division result, the combining circuit 23 selects the signal SE ₁ output from the control circuit 17, SE ₂
The operation result selected by is combined. FIG. 14 shows a detailed circuit of the arithmetic circuit 18, but the arithmetic circuits 19, 20, 21 of FIG.
The same applies to the above, and these circuits 18 to 21 obtain four pieces of interpolation enlarged data.

The constants in each of these operations are stored in advance in the random access memory 22, and are stored in the respective registers 27 to 29 selected by the address signals AD _{1 to} AD ₃ ,
Further, under the control of the control circuit 17, an operation for one piece of image data is selected and combined by the combining circuit 23. Therefore, the interpolated enlarged data for one dot obtained by the synthesizing circuit 23, that is, output from the synthesizing circuit 23 is a calculation result in consideration of the cut out four image data. This calculation result can be selected by the selector 30 and the constant in the calculation can be set to a target value. Therefore, the interpolation enlarged data obtained from the synthesizing circuit 23 is not determined by each circuit but from the control circuit. It is determined by various signals output. That is, enlarged image data can be obtained by various interpolation enlarging methods by changing the constants required for control and calculation of the control circuit.

 It returns to FIG. 2 and is explained again.

By the operation described above, the interpolation / magnification calculation circuit 7 outputs four interpolation / magnification data from the four cut-out pixel data. Then, the data is added to the selection circuit 8. In the embodiment of the present invention, the result of interpolation expansion is data of 4 pixels.
O _{1 to} O ₄ , but the columns in which the results are stored are different between the data O ₁ and O ₂ and the data O ₃ and O ₄ . The selection circuit 8 selects this.
It is the selection circuit 9 to which the output of is added. The data O ₁ and O ₂ are transferred to the upper line buffer 10 and the data by the two selection circuits.
O ₃ and O ₄ join the lower line buffer 11. That joined by one of the image data, selection data O ₁ of the data O ₁ ~ O ₄ interpolated enlarged by the interpolation enlargement arithmetic circuit 7 is first circuit 8
Is selected by the line buffer 10 by the selection circuit 9.
Is output to Next, the selection circuit 8 selects the data O ₂ and the selection circuit 9 outputs it to the line buffer 10. When the next data O ₃ and O ₄ are selected by the selection circuit 8, they are output to the line buffer 11 by the selection circuit 9.

When the data for one column is processed by the interpolation / magnification calculation circuit 7, the line buffer 10 and the line buffer 11 store the interpolation / magnification data of each column. The output of the line buffers 10 and 11 is added to the selection circuit 12, and the data for one column is selected, read out and output in column units to an enlarged image memory (not shown). For example, when obtaining 6 × 6 interpolated enlarged image data, 6 data are output in units of one column. As described above, the selection circuits 8, 9 and 12 perform a selection operation according to the control signal of the control circuit 6, and the line buffers 10 and 11 receive data from the control circuit 6 by a clock and select data by the output clock. Output to 12.

On the other hand, when calculating the next column, the h-stage shift register 3 outputs the next column. For example, the data C1 shown in FIG.
After 1, C12, C13 are stored and the above-mentioned processing is performed, C21, C22, C23 are stored in the h-stage shift register 3. As a result, one column of expanded interpolation is performed as in the above-described operation. By repeating this operation, the expansion interpolation processing is sequentially performed. As shown in FIGS. 5 to 13, since the right end and the lower end of the 3 × 3 image are processed using blank data, one data is acquired after three data in one column are fetched. The control circuit 6 accesses an image memory (not shown) so as to fetch blank data.

Further, the writing by the selection circuit 12 in units of one column is similarly stored in the enlarged image memory (not shown) by the control circuit 6. That is, in the interpolation enlargement processing as shown in FIG. 4, two columns are written with six pixel data as one column. At the time of this writing, the above-mentioned interpolation enlargement processing is stopped.

The image data of each input and each output in FIGS. 2, 3, 14, and 15 is represented by one line.
It represents a plurality of bit data, not bit data. This processing is not limited to black and white, but is controlled by a circuit (not shown) so that it is performed for each of the three primary colors.

In the embodiment of the present invention shown in FIG. 2, the image data of 3 × 3 pixels is cut out by 2 × 2 pixels to obtain the enlarged data of 2 × 2 pixels.
If it is configured so that pixel extraction and calculation can be performed, 2
It is possible to provide an interpolation enlarging circuit which can arbitrarily perform interpolation enlarging calculation in × 2 pixels, 3 × 3 pixels, and 4 × 4 pixels, and can further perform the arithmetic processing.

〔The invention's effect〕

As described above, according to the present invention, the data required for performing the interpolation enlargement process is sequentially taken into the register and a plurality of data sets are added to the interpolation enlargement circuit in one clock. Thus, it is possible to obtain an interpolation enlargement calculation circuit that performs the interpolation enlargement process of the entire screen at high speed.

[Brief description of drawings]

 1 is a block diagram of the principle of the present invention, FIG. 2 is a circuit configuration diagram of an embodiment of the present invention, FIG. 3 is a circuit configuration diagram of an interpolation enlargement circuit, and FIG. 4 (a) is an image of 3 × 3 pixels. FIG. 4 (b) is a diagram for explaining data, FIG. 4 (b) is a diagram for explaining image data of 6 × 6 pixels, FIG. 5 (a) is a diagram for explaining cutting out of 2 × 2 pixels, and FIG. 6A and 6B are diagrams illustrating interpolation enlargement of 2 × 2 pixels, FIG. 6A is a diagram illustrating clipping of 2 × 2 pixels, and FIG. 6B is a diagram illustrating interpolation enlargement of 2 × 2 pixels. FIG. 7 (a) is a diagram illustrating clipping of 2 × 2 pixels, FIG. 7 (b) is a diagram illustrating interpolation enlargement of 2 × 2 pixels, and FIG. 8 (a) is a segmenting of 2 × 2 pixels. FIG. 8 (b) is a diagram illustrating interpolation enlargement of 2 × 2 pixels, FIG. 9 (a) is a diagram illustrating clipping of 2 × 2 pixels, and FIG. 9 (b) is 2 ×. 2 pixel interpolation FIG. 10 (a) is a diagram for explaining clipping of 2 × 2 pixels, FIG. 10 (b) is a diagram for explaining interpolation enlargement of 2 × 2 pixels, and FIG. FIG. 11 (b) is a diagram for explaining clipping of 2 × 2 pixels, FIG. 11 (b) is a diagram for explaining interpolation expansion of 2 × 2 pixels, and FIG. 12 (a) is a diagram for explaining clipping of 2 × 2 pixels. FIG. 13B is a diagram for explaining interpolation enlargement of 2 × 2 pixels, FIG. 13A is a diagram for explaining cutout of 2 × 2 pixels, and FIG. 13B is a diagram for explaining interpolation enlargement of 2 × 2 pixels. FIG. 14 is a detailed circuit configuration diagram of an arithmetic processing circuit, and FIG. 15 is a detailed circuit configuration diagram of an arithmetic circuit. 1 ... Line buffer, 2 ... Interpolation enlargement circuit.

Claims (1)

(57) [Claims] 1. An input line buffer for storing input image data of at least one line of image information composed of m × n pixels, and a plurality of arbitrarily determined data are stored and selected and designated to be arbitrarily selected. A storage unit that outputs defined data, a multiplier that multiplies the input image data and the arbitrarily defined data, an adder that adds the input image data and the arbitrarily defined data, and the input image data and the A plurality of dividers each of which divides arbitrarily determined data, and a plurality of selecting means for selecting and outputting one of the outputs of the multiplier, the adder, and the divider. A plurality of arithmetic processing means having arithmetic means, a synthesis circuit for synthesizing data output from the plurality of arithmetic means to obtain interpolated enlarged data, and a control means for instructing the selecting means to select. Cage, straight An interpolation enlargement calculation circuit for processing the input image data input directly and the input image data inputted via the input line buffer in parallel by the calculation processing means to output interpolation enlargement data; A plurality of output line buffers for storing the interpolation enlargement data output from a circuit, wherein data belonging to the same row among the interpolation enlargement data are stored in the same output line buffer. .