JPS6367259U - - Google Patents
Info
- Publication number
- JPS6367259U JPS6367259U JP1986160173U JP16017386U JPS6367259U JP S6367259 U JPS6367259 U JP S6367259U JP 1986160173 U JP1986160173 U JP 1986160173U JP 16017386 U JP16017386 U JP 16017386U JP S6367259 U JPS6367259 U JP S6367259U
- Authority
- JP
- Japan
- Prior art keywords
- recesses
- semiconductor chip
- lead frame
- narrow
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案のリードフレームの一実施例を
示す平面図である。第２図ａは該実施例に用いる
半導体チツプの平面図、ｂは側面図である。第３
図及び第４図は実施例を説明するための図である
。第５図は第１図におけるＣ―Ｃ断面図、第６図
は同じくＡ―Ａ断面図、第７図は同じくＢ―Ｂ断
面図である。第８図は従来例を示す図である。 １……リードフレーム、１１……ダイパツド部
、２……半導体チツプ、１２……凹部、１３……
幅狭部。
示す平面図である。第２図ａは該実施例に用いる
半導体チツプの平面図、ｂは側面図である。第３
図及び第４図は実施例を説明するための図である
。第５図は第１図におけるＣ―Ｃ断面図、第６図
は同じくＡ―Ａ断面図、第７図は同じくＢ―Ｂ断
面図である。第８図は従来例を示す図である。 １……リードフレーム、１１……ダイパツド部
、２……半導体チツプ、１２……凹部、１３……
幅狭部。
Claims (1)
- 【実用新案登録請求の範囲】 半導体チツプを載置するパツド部を支持する部
材に複数の凹部が形成され、 該部材の凹部が形成される部分の少なくとも一
部が幅狭に形成されたことを特徴とするリードフ
レーム。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986160173U JPH06833Y2 (ja) | 1986-10-21 | 1986-10-21 | 透明樹脂で封止される光半導体装置の高耐湿性リ−ドフレ−ム |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986160173U JPH06833Y2 (ja) | 1986-10-21 | 1986-10-21 | 透明樹脂で封止される光半導体装置の高耐湿性リ−ドフレ−ム |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6367259U true JPS6367259U (ja) | 1988-05-06 |
| JPH06833Y2 JPH06833Y2 (ja) | 1994-01-05 |
Family
ID=31085307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986160173U Expired - Lifetime JPH06833Y2 (ja) | 1986-10-21 | 1986-10-21 | 透明樹脂で封止される光半導体装置の高耐湿性リ−ドフレ−ム |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06833Y2 (ja) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4918591U (ja) * | 1972-05-19 | 1974-02-16 | ||
| JPS558924U (ja) * | 1978-06-30 | 1980-01-21 |
-
1986
- 1986-10-21 JP JP1986160173U patent/JPH06833Y2/ja not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4918591U (ja) * | 1972-05-19 | 1974-02-16 | ||
| JPS558924U (ja) * | 1978-06-30 | 1980-01-21 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06833Y2 (ja) | 1994-01-05 |