JPS6366950A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having no possibility of a short circuit due to a hillock and high reliability and the high degree of integration by forming a groove along the side end of an aluminum alloy wiring layer in the aluminum alloy wiring layer or shaping irregular notches at the side end of the aluminum alloy wiring layer. CONSTITUTION:In a semiconductor device with an aluminum alloy wiring layer 3, the side end of which is brought near to another wiring layer and wiring width of which extends over 5mum or more, a groove 4 is formed along said side end in said aluminum alloy wiring layer 3, or irregular notches 4a are shaped at said side end. Accordingly, the same structure as a wiring layer in thin width is shaped at the side end oppositely faced to the adjacent wiring layer, and the formation of hillocks 3a at the side end due to the movement of aluminum at the time of annealing can be prevented, thus simply acquiring the semiconductor device, in which a short-circuit failure is not generated and which has the aluminum alloy wiring layer having high density.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an ultra-highly integrated semiconductor device in which the minimum wiring spacing of aluminum alloy wiring layers is 2 μm or less.

[Conventional technology]

FIG.
c Int-egrated C1rcuits, J.
^11ison, McGraw-Hi11.1975゜Japanese translation "Integrated Circuits", McGraw-Hill Kogakusha) It is a plan view showing the conventional semiconductor device shown in Chapter 1, and Fig. 4 is a cross section taken along the line A-A in Fig. 3. It is a diagram. In FIGS. 3 and 4, 1 is a semiconductor substrate, 2 is an insulating film, and 3 is a wiring layer made of aluminum alloy (hereinafter referred to as "aluminum alloy wiring layer").

In a conventional semiconductor device, after forming transistors, capacitors, resistors, etc. necessary for an integrated circuit configuration on a semiconductor substrate 1 (these are not shown because they are unnecessary for explanation of the present invention), wiring is performed. A base insulating film 2 is formed, and contact holes (not shown) are formed in necessary parts. After that, aluminum alloy wiring N3 of 0.5 to 165
The aluminum alloy wiring N3 is formed to have a thickness of μm and is patterned into a predetermined planar shape by photolithography.

The pitch and spacing of the aluminum alloy wiring layers 3 are important factors that determine the degree of integration of an integrated circuit, and the minimum processing dimensions achievable at the highest level of the technology at the time have been adopted. As a result, both the width and spacing of interconnects have now become less than 2 μm. Another factor that determines the width of wiring is current density. Due to the physical phenomenon called electro-migration, the current density flowing through the wiring must not exceed 1 x 10'A/cm. Due to this restriction, power lines, ground lines, etc. It is now necessary to increase the wiring width to 5 μm or more.

[Problem that the invention seeks to solve]

In conventional semiconductor devices, an aluminum alloy wiring layer is constructed as described above, but as a result of rearrangement of atoms that occurs during annealing, this aluminum alloy wiring layer has a third layer.
As shown in FIG. 4, there is a property that protrusions 3a called hillocks are formed in some places in the wiring layer. According to the inventor's experiments, this protrusion 3a is sometimes 2 μm thick.
Moreover, it often appears on both sides of wide interconnects with a width of 5 μm or more, but is rarely seen in thin interconnects with a width of 2 μm or less.

If the height of the protrusions 3a as described above exceeds the spacing between the wires, for example, as schematically shown in FIG. produce defects.

For this reason, in conventional semiconductor devices, even if there is a technology to reduce the wiring spacing to 2 μm or less, there is a problem in that it is necessary to maintain a spacing of 2 μm or more on both sides of wide wiring such as power supply lines and ground lines. was there.

The present invention has been made in view of these points, and its object is to provide a highly reliable and highly integrated semiconductor device that is free from the possibility of short circuits due to hillocks.

[Means for solving problems]

In order to achieve such an object, the present invention provides a semiconductor device having an aluminum alloy wiring layer whose side edges are close to other wiring layers and whose wiring width is 5 μm or more. A groove is formed, or an uneven cut is formed at the side edge of the aluminum alloy wiring layer.

[Effect]

In the present invention, hillocks do not occur at the side edges.

〔Example〕

An embodiment of a semiconductor device according to the present invention is shown in FIG.

In Figure 1, 3 is an aluminum alloy wiring layer, 3a is a hillock that has occurred in the aluminum alloy wiring layer 3, and 4 is a wide aluminum alloy wiring layer 3 provided corresponding to a portion adjacent to other wiring layers. It's a groove.

In the conventional example, in a wide wiring layer having a width of 5 μm or more, hillocks occurred at both side edges. However, in this device, at least in a portion of such a wide wiring layer where adjacent wiring layers are close to each other, a groove 4 as shown in FIG. 1 is provided in a part of the adjacent wiring layer. Therefore, the side end facing the adjacent wiring layer has a structure similar to that of a narrow wiring layer, and there is no possibility of hillocks and short circuits occurring between the adjacent wiring layer. If the width of the groove 4 is wide, the actual area loss will be large, but
In reality, the grooves 4 do not need to be completely separated like in a normal aluminum wiring layer, but are simply made to make it difficult for large movements of aluminum that would cause hillocks to occur during annealing. Therefore, it has been confirmed that the width can be much smaller than the minimum dimension as an integrated circuit pattern. Therefore, the area loss due to providing the groove 4 is extremely small.

In addition, in the above embodiment, the case where the grooves 4 are provided integrally over the necessary length is shown, but these may be provided in several areas, or some of the grooves may be provided separately. Needless to say, the aluminum alloy wiring layer 3 may be formed so as to form an opening.

Further, in the above embodiment, grooves are provided parallel to the side edges of a wide wiring layer, but for the purpose of preventing movement of aluminum that would cause hillocks, grooves are provided in parallel to the side edges of a wide wiring layer. As shown in Embodiment 2, the same effect can be obtained even if a notch 4a is vertically formed at the side edge of a wide wiring layer. In the case of this second embodiment as well, the width of the cuts 4a may be much smaller than the normal spacing between wiring layers, since the cuts 4a may bridge each other to some extent.

〔Effect of the invention〕

As explained above, the present invention prevents aluminum from moving during annealing by forming grooves along the side edges of an aluminum alloy wiring layer with a width of 5 μm or more, or by forming uneven cuts on the side edges. Since the formation of hillocks at the side edges can be prevented, it is possible to easily obtain a semiconductor device having a high-density aluminum alloy wiring layer without short-circuit failures.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing one embodiment of a semiconductor device according to the present invention, FIG. 2 is a plan view showing the second embodiment, FIG. 3 is a plan view showing a conventional semiconductor device, and FIG. is A in Figure 3.
-A cross-sectional view. 3... Aluminum alloy wiring layer, 3a... Hillock, 4... Groove, 4a... Notch.

Claims (2)

[Claims] (1) In a semiconductor device having an aluminum alloy wiring layer whose side edges are close to other wiring layers and whose wiring width is 5 μm or more,
A semiconductor device characterized in that a groove is formed in the aluminum alloy wiring layer along the side edge. (2) In a semiconductor device having an aluminum alloy wiring layer whose side edges are close to other wiring layers and whose wiring width is 5 μm or more,
A semiconductor device characterized in that an uneven cut is formed on the side edge.