JPH0416021B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit device having a multilayer wiring structure with an extremely high degree of integration.

(Prior Art) As the scale of semiconductor integrated circuit devices has become larger and larger, it has become common today to adopt a multilayer wiring structure. In a semiconductor integrated circuit device having this multilayer wiring structure, the wirings are usually electrically connected to each other through connection conductor portions formed in openings in an interlayer insulating film. At this time, the conductor film thickness of the lower layer wiring is made thinner than that of the upper layer wiring conductor to prevent sudden steps from forming in the upper layer wiring conductor during the manufacturing stage, but it also reduces the reliability of the wiring due to electromigration. Therefore, it is necessary to have a wiring cross-sectional area larger than a predetermined value corresponding to the current value. As a result, when the current value is almost the same, the lower the wiring, the wider the conductor width, and in the case of a multilayer wiring structure with three or more layers, the ratio between the bottom layer and the top layer can reach 4 to 5 times. There is. Furthermore, in order to flatten the wiring, the openings in the interlayer insulating film are formed in simple rectangular patterns at positions slightly offset from each other so that the connection conductor parts do not overlap each other.

(Problem to be solved by the invention) However, the scale of the accumulation is not larger than that, and 2
Multilayering is fine for a while, but when a multilayer structure with three or more layers is required and the amount of current flowing increases, the current density in the lower wiring conductor and the connecting conductor increases with the interlayer insulating film. It becomes strongly controlled by the aperture pattern that is formed. In other words, on a multilayer scale of about two layers, the difference in film thickness between two wirings is not that large, and therefore there is not much difference in conductor width, so even with the conventional hole pattern, the current density in the connecting conductor part is not that large. Moreover, each wiring current can flow almost to the full width of the conductor. However, when the scale is three or more layers and the difference in conductor width becomes large, in the conventional rectangular pattern, the shape of the opening becomes smaller as the conductor width becomes smaller toward the upper layer. As a result, the positions are difficult to form with respect to each other. Therefore, in the vicinity of each connection conductor, current no longer flows through the conductor width of the lower layer wiring, and the current path is stretched in the horizontal direction, increasing the ineffective area of the prepared conductor width. . Then, the current density of each wiring conductor in the vicinity of the connecting conductor portion is significantly increased. This increase in current density becomes more pronounced in the lower layer as the wiring width ratio increases, and the current tends to concentrate near the center of the wiring conductor, leaving the periphery unused. The effect of widening the wiring conductor is significantly reduced. Furthermore, this results in increased wiring resistance at such portions.

(Object of the Invention) In view of the above-mentioned circumstances, an object of the present invention is to suppress an increase in wiring resistance of a multilayer wiring conductor in the vicinity of a connecting conductor portion, and to solve the problem of electromigration. An object of the present invention is to provide a semiconductor integrated circuit device having the following features.

(Structure of the Invention) A semiconductor integrated circuit device of the present invention includes a semiconductor substrate, a multilayer wiring conductor layer formed on the semiconductor substrate via an interlayer insulating film, and a lower layer opening pattern of the interlayer insulating film having an upper layer opening. connection conductor portions between the multilayer wiring conductors formed so as to respectively surround the patterns.

(Means for Solving the Problems) That is, according to the present invention, the openings of each connection conductor formed in the interlayer insulating film are formed such that the lower layer opening pattern surrounds the upper layer opening pattern. It has a shape. Here, the lower layer hole pattern may be shaped to completely surround the upper layer hole pattern, or it may be surrounded by a U-shaped pattern from three sides so as to cross the current path from the upper layer wiring conductor layer. In some cases, it may be surrounded by a set shape of a plurality of divided patterns.

(Function) According to this lower layer aperture pattern, near each connection conductor portion, the current component that crosses the wiring conductor is more widely dispersed in the conductor, and almost all of the width of the conductor including the peripheral portion is effectively utilized. The present invention will be described in detail below with reference to the drawings.

(Embodiment) FIG. 1 is a plan view of the vicinity of a connecting conductor portion showing an embodiment of the present invention. In this example, the first layer, the second layer
wiring conductor layers 1, 2, and 3 formed in the first layer and the third layer, and a lower layer opening pattern 4 formed in an interlayer insulating film that insulates between the first and second wiring conductor layers.
and an upper layer opening pattern 5 formed in an interlayer insulating film that insulates between the second and third wiring conductor layers. Here, among the three wiring conductor layers, the first layer is formed to be the widest, and the second and third wiring conductor layers are formed in order of thick film, thick film, etc.
Formed narrowly. In addition, lower layer opening pattern 4
The upper layer opening pattern 5 is shaped like a U so that the current path flowing from each wiring conductor layer of the second layer and the third layer to the lower layer wiring conductor layer is crossed in each region.
It is formed so as to surround it from three sides.

According to this embodiment, the conventionally existing current path that stretches in the lateral direction is weakened in the vicinity of each connecting conductor, and instead a current path A-A' appears that crosses each conductor layer and extends toward the periphery. Therefore, the current component flowing through the periphery of each wiring conductor layer near each connection conductor is increased compared to the conventional case, so that the current density of each wiring conductor near each connection conductor can be significantly reduced. This current path uniformization effect is more effective as the number of wiring layers involved in the current path increases, and since the current can flow to the full width of the conductor by utilizing the periphery of the wiring conductor layer, it is possible to prevent electromigration from occurring. The intended effect of widening the wiring conductor can be fully utilized, and an increase in wiring resistance can be suppressed.

FIG. 2 is a plan view of the vicinity of a connecting conductor using a conventional rectangular opening pattern, showing how the current takes a path B-B' which is stretched in the lateral direction. In the conventional aperture pattern, since the lower aperture pattern 4 is not surrounded by the upper aperture pattern 5, a large amount of current flows along the path B-B' near the center of the wiring conductor layer, especially in the first layer and The current density in the vicinity of each connection conductor in each wiring conductor layer 1 and 2 of the second layer is significantly increased, causing electromigration.

FIG. 3 and FIG. 4 are plan views of the vicinity of the connecting conductor portion, respectively, showing other embodiments of the present invention.
Here, FIG. 3 shows an embodiment for a four-layer wiring structure, in which a fourth wiring conductor layer 6 and a second lower layer opening pattern 7 are newly provided. In this embodiment, there are two lower layer hole patterns, so the one provided between the first and second wiring conductor layers is the first lower layer hole pattern 4, and the second layer hole pattern is the one provided between the first and second wiring conductor layers.
The pattern provided between the layer and the third layer is distinguished from each other as a second lower layer aperture pattern 7. Further, in this case, the second lower layer hole pattern 7 has a relationship with the upper layer hole pattern of the first lower layer hole pattern 4, and all the lower layer hole patterns completely surround all the upper layer hole patterns. It is formed so as to surround it.

According to this embodiment, the current density in the vicinity of each connection conductor portion is more significantly reduced despite the increase in the number of wiring conductors because the current flows approximately radially between the connection conductor portions.

Furthermore, in FIG. 4, all of the aperture patterns are in the form of a collection of a plurality of divided patterns. This embodiment is suitable when the width of each wiring conductor is relatively wide.

(Effects of the Invention) As explained in detail above, according to the present invention,
It can significantly reduce the wiring current density in the connecting conductor part in a multilayer wiring structure, prevent the occurrence of electromigration, and suppress the increase in wiring resistance, significantly improving the reliability of wiring in multilayer wiring semiconductor integrated circuits. It has the effect of improving.

[Brief explanation of drawings]

FIG. 1 is a plan view of the vicinity of the connecting conductor section showing an embodiment of the present invention, FIG. 2 is a plan view of the vicinity of the connecting conductor section using a conventional dog-shaped hole pattern, and FIGS. 3 and 4 are, respectively. FIG. 7 is a plan view of the vicinity of a connecting conductor portion showing another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... First layer wiring conductor layer, 2... Second layer wiring conductor layer, 3... Third layer wiring conductor layer, 6... Fourth layer wiring conductor layer, 4, 7... Lower layer opening pattern, 5...
Upper layer opening pattern, A-A', B-B'...current path.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate, a multilayer wiring conductor layer formed on the semiconductor substrate via an interlayer insulating film, and a lower hole pattern of the interlayer insulating film formed so as to surround the upper layer hole pattern, respectively. and a connection conductor between the multilayer wiring conductors. 2. The lower layer opening pattern is formed to surround the upper layer opening pattern from three sides in a U-shape so as to cross a current path flowing from the upper wiring conductor layer to the lower wiring conductor layer. A semiconductor integrated circuit device according to claim 1. 3. The semiconductor integrated circuit device according to claim 1, wherein the lower layer opening pattern is formed to entirely surround the upper layer opening pattern. 4. The semiconductor integrated circuit device according to claim 1, wherein at least one of the lower layer opening patterns is formed of a set shape of a plurality of divided patterns.