JPS6365663A - Multilayer-structured capacitor - Google Patents

Abstract

PURPOSE:To realize a capacitor large in capacity and small in parasitic capacity per unit area by a method wherein a multiplicity of capacitors is built into a multilayer structure. CONSTITUTION:Unnecessary portions are removed from an SiN film by etching in an RIE unit with a photoresist serving as a mask. Next, the upper electrode 4 and lower electrode 2 of a first-layer capacitor are built by lift-off following a process of formation of a Ti/Au film by electron beam evaporation. An SiN film is deposited to serve as an insulating film 5 for a second-layer capacitor, and then etching is accomplished for patterning. Next, by a method similar to the one used for the formation of the lower electrode 2 for the first-layer capacitor, a Ti/Au film is formed by electron beam evaporation and then subjected to lift-off for the construction of the upper-layer electrode 6 of the second-layer capacitor. An SiN film is formed by deposition to serve as an insulating film 7 for a third-layer capacitor and then patterned by etching. In the last process for the completion of this three-layer structure, the upper electrode 8 of a third-layer capacitor is built in a process of forming a Ti/Au film by electron beam evaporation which is followed by lift-off.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to the structure of a metal/insulating film/metal (hereinafter referred to as MIM) structure capacitor among capacitors built on a semiconductor integrated circuit. This is related to the improvement of

<Conventional technology and its problems> Conventionally, in integrated circuits, as the degree of integration has improved, the area of the capacitor has been reduced, but due to circuit operation conditions, the capacitance is limited to a certain extent. It cannot be made smaller.

FIG. 3(a) is a diagram schematically showing an example of the structure of a conventional MIM structure capacitor, in which 11 is a semiconductor substrate, 12 is a metal layer for a lower electrode, 13 is an insulating film, and 14 is a metal layer for an upper electrode. be. Conventionally, a SiN or 5i02 film has been used as the insulating film 13 for this MIM structure capacitor, but in order to secure a certain capacity, the insulating film must be made thinner to ensure a sufficient yield. I'm starting to feel like I can't take it anymore.

Furthermore, the conventional M I M shown in FIG. 3(a) above
Compared to structural capacitors, the trench type or well type structure capacitor shown in FIG. 4(a), which can reduce the surface area occupied by the wafer (in addition to the M I M structure shown in the figure, there is also an M I S structure), Recently, research and development has been carried out toward practical application.

However, the problem with capacitor characteristics is not simply improving capacitance per unit area. A capacitor formed on a semiconductor substrate has parasitic capacitance between the substrate and the capacitor electrode.

This parasitic capacitance causes various problems for integrated circuits operating at high speed, such as a reduction in operating speed, an increase in noise figure, and phase rotation.

11g3 A simple equivalent circuit of the conventional MIM capacitor shown in FIG. 3(a) is shown in FIG. 3(b). Here, when the area of the lower electrode is Ss and the proportionality coefficient is k, the parasitic capacitance C5 is expressed by the following equation.

Similarly, FIG. 4(b) shows a simple equivalent circuit of the well-structured capacitor shown in FIG. 4(a). Here, if the total areas of the bottom and side surfaces of the lower electrode are S8I and 882, respectively, and the parasitic capacitances of the bottom and side surfaces are C5□ and C5□, respectively,
The total parasitic capacitance C8' is expressed by the following equation.

On the other hand, if the material and film thickness of the insulating film are the same in Fig. 3(a) and Fig. 4(a) above, Ss in S8, + S3□---(3) Therefore,
From the above equations (1), (2) and (3), Cs'? Cs′
...(4). Therefore, even in the well-structured capacitor shown in FIG. 4(a), the problem of parasitic capacitance remains unsolved.

The present invention was devised in view of the above points, and an object of the present invention is to provide a capacitor having a large capacitance per unit area and a small parasitic capacitance.

<Means and operations for solving the problems> In order to achieve the above object, the multilayer structure capacitor of the present invention includes a substrate, a second electrode metal layer formed on the substrate, A plurality of capacitors are arranged in a multilayer structure, including at least a second insulating film deposited to a predetermined thickness on the second electrode metal layer, and a third electrode metal layer formed on the second insulating film. It is configured to be

FIG. 1(a) is a diagram schematically showing an example of a three-layered multilayer capacitor obtained according to the present invention. In the figure, 1 is a semiconductor substrate, 2 is a first layer capacitor a first electrode metal layer as a lower electrode; 3 a first insulating film deposited to a predetermined thickness as an insulating film of a first layer capacitor;
4 is a second electrode metal layer serving as the upper electrode of the first layer capacitor and the lower electrode of the second layer capacitor; 5 is a second insulating film deposited to a predetermined thickness as an insulating film of the second layer capacitor; 6 is a third electrode metal layer serving as the upper electrode of the second layer capacitor and the lower electrode of the third layer capacitor; 7 is a third insulating film deposited to a predetermined thickness as an insulating film of the third layer capacitor; 8 is the fourth layer as the upper electrode of the third layer capacitor.
This is the electrode metal layer.

As is clear from FIG. 1(a), the present invention is characterized in that the upper electrode of the lower layer capacitor also serves as the lower electrode of the upper layer capacitor.

FIG. 1(b) is a diagram showing a simple equivalent circuit of the multilayer structure capacitor shown in FIG. 1(a). The capacitance f of the first layer, second layer, and third layer capacitor of the entire multilayer structure capacitor is f! When k is respectively C1lt CI2 + Cls and the parasitic capacitance "f: C53", the total capacitance C, // is expressed by the following equation.

Cr' = C++ + CI2 + Cl3 ・ ・
(5) Furthermore, if the electrode areas of the first, second, and third layer capacitors are equal and Sll, CI'=3.CI+ (6). Here, the capacitor shown in FIG. 3(a) and the capacitor shown in FIG.
Considering the case where the total capacitance of the capacitors shown in a) is equal, from the above equation (6), C]=3.CI+ (7). Therefore, when the material and thickness of the insulating film are the same, the following relationship holds true between the electrode areas of both capacitors.

58=3.Sl (8) As a result, from the relationship in equation (8) above, the following is derived. Furthermore, equation (9) is expressed generally. 1st
The parasitic capacitance C1n of a multilayer structure capacitor consisting of n layers as typified by figure (a) is expressed by three
Figure (a) The parasitic capacitance C3 of a general capacitor represented by VC and the relationship shown in the following equation, n
Ru.

Cln=straight above 00. . .

As a result of the above, in the case of the multilayer structure capacitor of the present invention, the capacitance per unit area increases in proportion to the increase in the number of layers, and even when considering the parasitic capacitance generated between the substrate and the substrate, as expressed by the equation 00, will decrease.

<Example> Hereinafter, an example of the present invention will be described in detail together with its manufacturing process with reference to the drawings.

FIGS. 2(a) to 2(c) are diagrams each schematically showing the manufacturing process of a three-layer structure capacitor as an embodiment of the present invention.

When carrying out the present invention, semi-insulating Ga is used as the substrate 1.
Using As, as the lower electrode 2 of the first layer capacitor, Ti/Au was electron beam evaporated (0.1 μm/0.3 ttm') L as shown in Fig. 2(a), and this was lifted off. form. Next, as the insulating film 3 of the first layer capacitor, a SiN film with a thickness of 0.2 μm was deposited on the entire surface using the SiH4NH3 based Ganu plasma CVD method, and as shown in FIG. 2(b), unnecessary parts were removed. The SiN film is etched using an RIE apparatus using a photoresist as a mask. Next, as shown in FIG. 2(c), the upper electrode 4 of the first layer capacitor is formed in the same manner as the lower electrode 2.
i/Au is formed by electron beam evaporation and lift-off. The upper electrode 4 of this first layer capacitor is
Since it is shared with the lower electrode of the second layer capacitor, immediately next,
As the insulating film 5 of the second layer capacitor, a SiN film of 0.2
Deposit, etch and pattern. Next, the first
Similarly to the formation of the lower electrode 2 of the layer capacitor, the upper electrode 6 of the second layer capacitor is formed as shown in FIG. 2(e).
Ti/Aufe is formed by electron beam evaporation and lift-off. Since the upper electrode 6 of the second layer capacitor is shared with the lower electrode of the third layer capacitor, the insulating film 7 of the third layer capacitor is then formed by plasma CVD as shown in FIG. 2(f). Using this method, a SiN film is deposited to a thickness of 0.2 μm, and patterned by etching. In this example, since a three-layer structure is used, the upper electrode 8 of the third layer capacitor is finally formed by electron beam evaporation of Ti/Au and lift-off as shown in FIG. 2 Q). . Through the above steps, a three-layer structure capacitor as an embodiment of the present invention is obtained.

<Effects of the Invention> As described above, according to the present invention, by forming a capacitor into a multilayer structure, the capacitance per unit area can be improved, and at the same time, the parasitic capacitance generated between the capacitor and the substrate can be reduced. This has the effect of improving the characteristics of integrated circuits aimed at high-speed operation.

[Brief explanation of the drawing]

FIG. 1(a) is a diagram schematically showing the cross-sectional structure of one embodiment of the multilayer structure capacitor of the present invention, and FIG.
A diagram showing the equivalent circuit of the capacitor shown in a), Fig. 2(a)
) to (g) are diagrams each showing an example of the manufacturing process for producing the multilayer structure capacitor of the present invention, and FIG. 3(a)
is a schematic diagram showing an example of the cross-sectional structure of a conventional MIM structure capacitor, FIG. 3(b) is a diagram showing this circuit, and FIG.
FIG. 4(a) is a schematic diagram showing an example of the cross-sectional structure of a well-structured capacitor, and FIG. 4(b) is a diagram showing this equivalent monovalent circuit. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Lower electrode of first layer capacitor, 3... Insulating film of first layer capacitor, 4.
... Upper electrode of the first layer capacitor and lower electrode of the second layer capacitor, 5... Insulating film of the second layer capacitor, 6
... Upper electrode of the second layer capacitor and lower electrode of the third layer capacitor, 7... Insulating film of the third layer capacitor,
8... Upper electrode of third layer capacitor. Agent Patent Attorney Takeshi Sugiyama (1 person) (a) (b) (a) (b) (C) Hen 2 Zu (?L) (a) Ci' (b)

Claims (1)

[Claims] 1. A substrate; a first electrode metal layer formed on the substrate; a first insulating film deposited to a predetermined thickness on the first electrode metal layer; a second electrode metal layer formed on the first insulating film; a second insulating film deposited to a predetermined thickness on the second electrode metal layer; and a second electrode metal layer formed on the second insulating film. A multilayer structure capacitor comprising at least a third electrode metal layer.