JPH10125860A - Plane spiral inductor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plane spiral inductor which can realize reduction of size without generating deterioration of resolution or increase of wiring resistance in a photolithography process. SOLUTION: The intersection part of a wiring 13 of a first layer and a wiring 15 of a second layer is in the inside of a recessed part 23 formed on an insulating film on a semiconductor substrate. Thereby the film thickness of a resist pattern turning to a mask of gold plating constituting the wiring 15 does not become thinner than other parts in the intersection part. Even if the gold plating is grown as far as the film thickness nearly equal to the resist pattern, the gold plating dose not protrude to the upper part of the resist pattern and grow in the side direction, and shortcircutting between wirings is not generated. Thereby it is made unnecessary that the wiring 15 of a second layer is thinned and the space between the wirings 15 is increased, and the size of an element can be reduced without increasing the loss due to wiring resistance. Since it is unnecessary that the film of the resist pattern is made thicker than the conventional case, resolution in a photolithography process is not deteriorated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar spiral inductor which is formed in a spiral shape on a planar substrate to constitute an inductance element, and more particularly to a planar spiral inductor having a hollow portion at an intersection of upper and lower layer wirings and its manufacture. About the method.

[0002]

2. Description of the Related Art Generally, a semiconductor integrated circuit device (hereinafter referred to as I
Called C. A so-called planar spiral inductor is an example of the inductance function element built in the above. This element has a structure in which a planar spiral (spiral) wiring is formed on an IC substrate, and an end on the center side of the spiral wiring is drawn out of the spiral wiring region by another layer wiring. MMIC (Monolith
In a high-frequency IC such as an IC (Microwave Integrated Circuit), a structure is adopted in which a hollow portion is provided at the intersection of both wirings in order to reduce the parasitic capacitance between the upper and lower wirings and increase the speed.

Conventionally, this type of planar spiral inductor has a structure as shown in FIGS. 8 and 9, for example. Here, FIG. 8 illustrates a planar structure, and FIG. 9 illustrates a cross-sectional structure taken along line XX ′ in FIG. As shown in these drawings, an insulating film 102 is formed on a semiconductor substrate 101, and a first linearly patterned first insulating film 102 is formed thereon.
The wiring 103 of the layer is formed. The wiring 103 is covered with an interlayer insulating film 104, and a second-layer wiring 105 patterned in a spiral shape is formed thereon. One end of the wiring 103 is connected to the spiral center side end of the wiring 105 through the contact hole 106, and the other end is connected to a circuit element in an IC (not shown). The spiral outermost end of the wiring 105 is also connected to a not-shown circuit element in the IC.

[0004] As shown in FIG.
05 and the wiring 10 at the intersection region
A hollow portion 107 is formed between the wiring 103 and the wiring 103 so that the wiring 105 does not directly sandwich the interlayer insulating film 104 between the wiring 103 and the wiring 103.
5 can be reduced.

Next, a manufacturing process of a conventional planar spiral inductor having such a structure will be described with reference to FIGS. Each figure in FIG. 10 corresponds to X in FIG.
-X 'section is shown.

[0006] First, as shown in FIG.
Semiconductor substrate 1 by D (Chemical Vapor Deposition) method
First, an insulating film 102 is formed, and a first wiring layer is deposited thereon. Then, the first wiring layer is linearly patterned by a photolithography step and an etching step to form the wiring 103.

Next, as shown in FIG. 1B, after an interlayer insulating film 104 is formed on the entire surface by a CVD method, a contact hole 106 (FIG. 7) is formed by a photolithography step and an etching step.

Next, as shown in FIG. 1C, after a resist film is formed on the interlayer insulating film 104, this is patterned by a photolithography process, and the interlayer insulating film on the first wiring 103 is formed. A resist pattern 109 for forming a hollow portion is formed so as to cover the film 104.

Next, as shown in FIG. 11A, a base layer 11 serving as a base for a second wiring layer formed in a later step.
0 is formed on the entire surface by vapor deposition.

Next, as shown in FIG. 1B, after forming a thick resist film of 4 μm or more on the entire surface, a resist pattern as a mask for plating the second-layer wiring is formed by a photolithography process. 111 is formed. This drawing shows a section taken along the line YY 'in FIG.

Next, as shown in FIG. 1C, the underlying layer 110 is plated and grown by gold plating, and the second layer wiring 1 is selectively formed in the opening region of the resist pattern 111.
05 is formed. This figure also shows Y- in FIG.
It shows a Y ′ cross section.

Next, as shown in FIG. 12, the resist pattern 109 and the resist pattern 111 are peeled off, and the underlying layer 11 in a region other than the second layer wiring 105 is removed.
0 is removed by etching. This drawing shows a section taken along line XX 'in FIG.

By the above process, the formation of the planar spiral inductor is completed. Here, the first layer wiring 1
03 and the second layer wiring 105, the hollow portion 10 is formed by removing the resist pattern 109.
7 are formed, and wiring 103 and wiring 105 are formed in this portion.
Does not directly sandwich the interlayer insulating film 104, thereby reducing the parasitic capacitance between wirings. The wiring 1 of the second layer
05 is required to be formed as thick as possible (4 μm or more) in order to reduce loss due to resistance, and therefore, a thick film is formed by plating.

[0014]

As described above, conventionally, in forming the second-layer wiring 105, a plating process is indispensable because it is necessary to increase the film thickness in order to reduce loss due to resistance. For this reason, as described above, the resist pattern 111 having a thickness of 4 μm or more is formed, and gold is selectively plated and grown in the opening using the resist pattern 111 as a plating mask to form the thick wiring 105. .

Here, the film thickness of the wiring 105 is limited by the thickness of the resist pattern 111, and in particular, depends on the film thickness at the intersection of the first-layer wiring 103 and the second-layer wiring 105. I do. This is because the film thickness of the resist pattern 111 is the thinnest at the intersection of both wirings, and is therefore approximately the same as the film thickness of the resist pattern 111 (4 to 5 μm).
m), the gold plating also grows laterally beyond the resist pattern 111 at the intersection, and in some cases, the adjacent wirings 105 are short-circuited as shown in FIG. It is because.

In order to prevent such a short circuit between the wirings, a method of securing a sufficiently large space between the wirings 105, the thickness of the gold plating (that is, the thickness of the wiring 105).
, Or a method of forming the resist pattern 111 to be thicker to prevent the lateral growth of gold plating.

However, in the method (1), there is a problem in downsizing the planar spiral inductor.
Since the thickness of the wiring 105 is reduced, loss is increased due to an increase in resistance. Further, in the method (1), the resolution in the photolithography process is deteriorated, which causes a problem in forming a resist pattern.

The present invention has been made in view of the above problems, and has as its object to provide a planar spiral inductor capable of realizing size reduction without a problem of resolution in a photolithography process and an increase in wiring resistance, and a manufacturing method thereof. It is to provide a method.

[0019]

According to a first aspect of the present invention, there is provided a planar spiral inductor formed on a first wiring formed on an insulating layer on a substrate and on an interlayer insulating film covering the first wiring. Spiral second wiring, the first wiring and the second wiring
And a hollow portion formed between the two wirings at the intersection with the first wiring, and the intersection between the first wiring and the second wiring is
It is configured to be located inside a recess formed in the substrate or the insulating layer.

According to a second aspect of the present invention, there is provided a method for manufacturing a planar spiral inductor, comprising the steps of: forming a concave portion on a part of a substrate surface; forming an insulating layer on the substrate so as to cover the concave portion; Forming a first wiring extending along the concave portion on the insulating layer, forming an interlayer insulating film so as to cover the first wiring, and forming an interlayer at an intersection with the first wiring. Forming a spiral second wiring on the interlayer insulating film so as to form a hollow portion for separating the insulating film from the insulating film.

According to a third aspect of the present invention, there is provided a method for manufacturing a planar spiral inductor, comprising: forming an insulating layer on a substrate; forming a recess in a part of the insulating layer; Forming a first wiring extending along the concave portion, forming an interlayer insulating film so as to cover the first wiring, and separating the interlayer insulating film at an intersection with the first wiring Forming a spiral second wiring on the interlayer insulating film so that a hollow portion is formed.

In the planar spiral inductor according to the present invention, since the intersection of the first wiring and the second wiring is located inside the recess formed in the substrate or the insulating layer,
The resist film as a plating mask used for forming the second wiring does not become thinner at the intersection than the others. Therefore, when the plating step is performed, the plating does not grow over the plating mask in the lateral direction, and short-circuiting between adjacent wirings can be prevented. Similarly,
In the method for manufacturing a planar spiral inductor according to the present invention, since the intersection of the first wiring and the second wiring is formed inside the concave portion formed in the substrate or the insulating layer, the horizontal wiring during the plating step is performed. It is possible to prevent the plating growth in the direction, and to prevent the occurrence of a short circuit between adjacent wirings.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a structure of a planar spiral inductor according to an embodiment of the present invention. here,
FIG. 1 shows a planar structure, and FIG. 2 shows a cross section taken along line AA 'in FIG. As shown in these figures, an insulating film 12 is formed on a semiconductor substrate 11, and a concave portion 23 having a predetermined depth and width is formed in the insulating film 12. The insulating film 12 at the center of the recess 23
On the top, a first-layer wiring 1 that is linearly patterned
3 are formed. The wiring 13 is covered with an interlayer insulating film 14 together with the other parts, and further, an underlying layer 20 and a second-layer wiring 15 patterned in a spiral shape are formed thereon. One end of the wiring 13
The wiring 15 is connected to the spiral center side end of the wiring 15 through the contact hole 16, and the other end is connected to an IC circuit element (not shown). The spiral outermost end of the wiring 15 is also connected to a not-shown circuit element in the IC.

As shown in FIG. 2, as shown in FIG.
Are all located within the concave portion 23, and a hollow portion 17 is formed between the interlayer insulating film 14 and the wiring 15 in this intersection region. With such a structure,
The wiring 15 does not directly sandwich the interlayer insulating film 14 between the wiring 15 and the wiring 13, so that the parasitic capacitance between the wiring 13 and the wiring 15 can be reduced.

The depth of the concave portion 23 is substantially equal to the sum of the thickness of the first-layer wiring 13 and the interlayer insulating film 14 and the thickness of the hollow portion 17. In the step of depositing the base layer 20 serving as the base of the plating process for the first step, the top of the hollow portion forming resist pattern formed on the first-layer wiring 13 does not project from the recess 23. Therefore, the depth of the concave portion 23 may be greater than the sum of the thickness of the first-layer wiring 13 and the interlayer insulating film 14 and the thickness of the hollow portion 17.

Next, a manufacturing process of the planar spiral inductor having such a structure will be described with reference to FIGS. 4 (c) shows a section taken along line BB 'in FIG. 1, and the other section shows a section taken along line AA'.

First, as shown in FIG.
A silicon nitride film (Si ₃ N ₄ ) or a silicon oxide film (SiO ₂ )
₂ ) An insulating film 12 is formed. This insulating film 12
Has a thickness of, for example, about 1.8 μm.

Next, as shown in FIG. 3, a first step is performed in a subsequent step by a photolithography step and an etching step.
A concave portion 23 is formed in a portion of the insulating film 12 where a wiring layer is formed. Here, the depth of the concave portion 23 is deeper than the sum of the thickness of the first-layer wiring 13 and the interlayer insulating film 14 and the thickness of the hollow portion 17 (resist pattern 19) formed in each of the subsequent steps. Preferably, the thickness is, for example, about 1.5 μm. The width of the recess 23 is, for example, about 10 μm.

Next, as shown in FIG. 2B, after the first wiring layer is deposited on the insulating film 12, the first wiring layer is formed by a photolithography step and an etching step. Are linearly patterned to form a first layer wiring 1
Form 3 This wiring 13 is made of, for example, titanium (T
i), a layered structure of platinum (Pt) and gold (Au), and the film thickness is, for example, about 500 nm.

Next, as shown in FIG. 1C, after an interlayer insulating film 14 made of a silicon nitride film, a silicon oxide film, or the like is formed on the entire surface by a CVD method, a spiral is formed by a photolithography step and an etching step. A contact hole 16 (FIG. 1) is formed at the center where the structure is formed.

Next, as shown in FIG. 4A, after a resist film is formed on the interlayer insulating film 14, the resist film is patterned by a photolithography process to form an interlayer insulating film on the first wiring 13. A resist pattern 19 for forming a hollow portion is formed so as to cover the film 14.

Next, as shown in FIG. 4B, a base layer 20 serving as a base of a second wiring layer formed in a later step is formed on the entire surface by vapor deposition. The underlayer 20 has a laminated structure of, for example, titanium (Ti) and gold (Au), and its film thickness is, for example, about 20 nm and about 200 nm, respectively.

Next, as shown in FIG. 4C, after forming a thick resist film of 4 to 5 μm on the entire surface, a resist pattern 21 as a plating mask for the second-layer wiring is formed by a photolithography process. To form

Next, as shown in FIG. 5, the underlayer 20 is plated and grown by gold plating, and the second-layer wiring 15 is selectively formed in the opening region of the resist pattern 21. This wiring 15 is used to reduce loss due to resistance.
The thickness is about 4 to 5 μm. After that, as shown in the figure, the resist pattern 19 and the resist pattern 21 are peeled off, and the underlying layer 20 in a region other than the second-layer wiring 15 is removed by etching.

With the above process, the formation of the planar spiral inductor is completed. Here, the first layer wiring 1
A hollow portion 17 is formed by removing the resist pattern 19 at the intersection of the third layer and the second-layer wiring 15, and the wiring 13 and the wiring 15 can directly sandwich the interlayer insulating film 14 at this portion. Therefore, the parasitic capacitance between wirings is reduced.

Since the intersection of the first-layer wiring 13 and the second-layer wiring 15 is inside the recess 23, the thickness of the resist pattern 21 serving as a mask for gold plating is reduced to the intersection. Does not become thinner than others. For this reason, even if the thickness of the gold plating (that is, the second-layer wiring 15) is grown to the same thickness as the resist pattern 21, the gold plating protrudes above the resist pattern 21 and extends in the lateral direction. Will not grow. Therefore, it is not necessary to particularly reduce the thickness of the second-layer wiring 15 or to particularly increase the space between the wirings 15, and to reduce the element size without increasing loss due to wiring resistance. Can be. In addition, the thickness of the resist pattern 21 does not need to be larger than the conventional thickness (4 to 5 μm), so that the resolution in the photolithography process is not affected.

Next, another embodiment of the present invention will be described.

FIG. 6 shows a sectional structure of a planar spiral inductor according to another embodiment of the present invention, corresponding to FIG. 2 in the above embodiment. In this figure, the same components as those of FIG. 2 are denoted by the same reference numerals, and the description will be appropriately omitted.

In the above embodiment, the concave portion 2 is formed in the insulating film 12.
In this embodiment, the recess 24 is formed in the semiconductor substrate 11, while the recess 3 is formed. With this concave portion 24,
The thickness of the resist pattern 21 at the intersection of the first-layer wiring 13 and the second-layer wiring 15 is prevented from being reduced. Other configurations are the same as those in FIG.

Next, a manufacturing process of the planar spiral inductor having such a structure will be described. In this embodiment, first, as shown in FIG.
Then, a concave portion 24 is formed by a photolithography process and an etching process. The depth of the recess 24 is substantially the same as the depth of the recess 23 in the above embodiment. Next, as shown in the figure, the first-layer wiring 13 is formed on the insulating film 12 at the bottom of the concave portion 24. Since the subsequent steps are the same as those in the above-described embodiment (FIGS. 3 to 5), the description thereof is omitted.

In the present embodiment, even if the thickness of the gold plating (that is, the second-layer wiring 15) is grown to a thickness similar to that of the resist pattern 21, the gold plating is Does not protrude above the top of the wiring and does not grow in the horizontal direction. Therefore, it is possible to prevent the occurrence of a short circuit between the wirings without particularly reducing the thickness of the second-layer wiring 15 or increasing the space between the wirings 15. it can. Therefore, it is possible to prevent an increase in loss due to wiring resistance, to reduce the element size, to eliminate the resolution problem in the photolithography process, and the like.

As described above, the present invention has been described with reference to some embodiments. However, the present invention is not limited to these embodiments, and can be variously modified within an equivalent range. For example, the semiconductor substrate 11 is not limited to a GaAs substrate, but may be a silicon substrate. The wiring of the second layer is not limited to gold plating, but may be another plating (for example, copper, nickel, silver, zinc, tin, or chromium).

[0044]

As described above, according to the planar spiral inductor and the method of manufacturing the same according to the present invention, the intersection between the first wiring and the second wiring is formed in the recess formed in the substrate or the insulating layer. Since it is located inside, the resist film as a plating mask used for forming the second wiring does not become thinner at the intersection than at the other portions. Therefore, the plating does not grow over the plating mask in the lateral direction when performing the plating step, and short-circuiting between adjacent wirings can be prevented. Therefore,
There is no need to make the thickness of the second wiring particularly thin or to make the space between the wirings particularly large, and it is possible to reduce the element size without increasing the loss due to the wiring resistance. Further, since the growth of the plating in the lateral direction can be prevented without excessively increasing the thickness of the resist film used for forming the second wiring, there is an effect that the resolution in the photolithography process is improved.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a structure of a planar spiral inductor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a main part structure of the planar spiral inductor illustrated in FIG.

FIG. 3 is a fragmentary cross-sectional view showing a part of a manufacturing process of the planar spiral inductor.

FIG. 4 is a fragmentary cross-sectional view showing a manufacturing step following FIG. 3;

5 is a fragmentary cross-sectional view showing a manufacturing step following FIG. 4;

FIG. 6 is a cross-sectional view illustrating a main structure of a planar spiral inductor according to another embodiment of the present invention.

FIG. 7 is a sectional view illustrating a part of a manufacturing process of the planar spiral inductor illustrated in FIG.

FIG. 8 is a plan view illustrating a structure of a conventional planar spiral inductor.

FIG. 9 is a cross-sectional view illustrating a main structure of a conventional planar spiral inductor.

FIG. 10 is a fragmentary cross-sectional view showing a part of a manufacturing process of a conventional planar spiral inductor.

11 is a fragmentary cross-sectional view showing a manufacturing step following FIG. 10;

12 is a fragmentary cross-sectional view showing a manufacturing step following FIG. 11;

FIG. 13 is a plan view showing a short-circuit state between wires in a conventional planar spiral inductor.

[Explanation of symbols]

11: semiconductor substrate, 12: insulating film, 13: (first layer) wiring, 14: interlayer insulating film, 15: (second layer) wiring, 17: hollow portion, 19: resist pattern (hollow portion) 20) Underlayer, 21 ... Resist pattern (plating growth mask), 23, 24 ... recess

Claims (3)

[Claims] A first wiring formed on an insulating layer on the substrate; a second spiral wiring formed on an interlayer insulating film covering the first wiring; And a hollow portion formed between the two wirings at the intersection of the first wiring and the second wiring, and the intersection of the first wiring and the second wiring is formed on the substrate or the insulating layer. A planar spiral inductor, wherein the planar spiral inductor is located inside a concave portion. 2. a step of forming a recess in a part of the surface of the substrate; a step of forming an insulating layer on the substrate so as to cover the recess as well; Forming a first wiring extending along the first wiring; forming an interlayer insulating film so as to cover the first wiring; and intersecting the first wiring with the interlayer insulating film at an intersection with the first wiring. Forming a spiral second wiring on the interlayer insulating film so as to form a hollow portion for isolating the planar spiral inductor. A step of forming an insulating layer on the substrate; a step of forming a recess in a part of the insulating layer; and a first wiring extending along the recess on the insulating layer in the recess. Forming an interlayer insulating film so as to cover the first wiring; and forming a hollow portion at an intersection with the first wiring to separate the interlayer insulating film from the first wiring. Forming a spiral second wiring on the interlayer insulating film in the above manner.