JPS6365373U

JPS6365373U -

Info

Publication number: JPS6365373U
Application number: JP16044886U
Authority: JP
Priority date: 1986-10-20
Filing date: 1986-10-20
Publication date: 1988-04-30

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すブロツク図
、第２図は第１図のアドレスカウンタコントロー
ル回路の例を示す図、第３図は第１図の回路の動
作を説明するのに示したタイミングチヤート、第
４図はこの考案回路によるアドレス指定動作を説
明するのに示した説明図、第５図は、この考案回
路による表示状態を説明するのに示した説明図、
第６図はキヤラクタ発生回路を備えたテレビジヨ
ン受像機の例を示す図、第７図は従来のキヤラク
タ発生回路を示す図、第８図は第７図の回路の動
作を説明するのに示したタイミングチヤート、第
９図は従来のキヤラクタ発生回路のアドレス指定
動作の例を示す説明図、第１０図、第１１図は従
来のキヤラクタ発生回路による表示例を示す図で
ある。３１…水平カウンタ、３２…表示タイミング発
生回路、３３…クロツク発生回路、３５…アドレ
スデコーダ、３６…キヤラクタメモリ、３７…キ
ヤラクタ出力回路、３８…アドレスカウンタコン
トロール回路。 FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is a diagram showing an example of the address counter control circuit of FIG. 1, and FIG. 3 is a diagram for explaining the operation of the circuit of FIG. 1. FIG. 4 is an explanatory diagram for explaining the addressing operation by this devised circuit; FIG. 5 is an explanatory diagram for explaining the display state by this devised circuit;
FIG. 6 is a diagram showing an example of a television receiver equipped with a character generating circuit, FIG. 7 is a diagram showing a conventional character generating circuit, and FIG. 8 is a diagram used to explain the operation of the circuit in FIG. FIG. 9 is an explanatory diagram showing an example of addressing operation of a conventional character generating circuit, and FIGS. 10 and 11 are diagrams showing examples of display by the conventional character generating circuit. 31...Horizontal counter, 32...Display timing generation circuit, 33...Clock generation circuit, 35...Address decoder, 36...Character memory, 37...Character output circuit, 38...Address counter control circuit.

Claims

[Claims for Utility Model Registration] A memory that stores character data such as characters and symbols, an address decoder that specifies the address of this memory, and outputs the character data read from the memory as display data. A character generation circuit comprising: an output circuit; and display timing control means for controlling a time point at which address data is output from the address decoder and supplying a timing signal to the output circuit to control display timing of a character; In response to the horizontal frequency being switched between the first frequency and a second frequency that is twice the horizontal frequency, the timing control means switches the address generation speed of the address decoder according to the first frequency and a second frequency that is twice the frequency. A character generation circuit characterized in that it is equipped with means for generating the same address twice.