JPS6365268B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to an image data compression circuit used in an image processing system, and more particularly to compression of line image data in automatic design of wiring patterns and the like.

(B) Technical background Automatic design systems have been used for the design of printed wiring patterns for a long time, but the proportion of printed wiring pattern design in the design of computers and other devices has recently been increasing.
Therefore, much importance is placed on shortening the design time and reducing the number of design man-hours.

On the other hand, image processing occupies a large proportion in the automatic design of printed wiring patterns, and therefore compression of image data related to printed wiring patterns is used as a particularly effective means to shorten the design time and reduce the number of design man-hours. .

(C) Prior art and problems Printed wiring patterns are usually drawn along grid lines a that are orthogonal to each other with a constant pitch p, as illustrated in FIG. As shown in FIG. 2, image data compression is basically performed for each divided image of a square whose center is a grid line intersection point b as shown by dotted lines and whose length on one side is p.

On the other hand, in conventional image data compression circuits, there are those in which the size of the divided images to be compressed, that is, the length of the sides, are constant, and there are those in which this is arbitrary. However, the former cannot handle grid lines with different pitches,
In the latter case, the circuit configuration is complicated, and both methods require time for compression processing.

(D) Purpose of the Invention The purpose of the present invention is to eliminate the problems in the conventional example described above, that is, to provide an image data compression circuit that can make the size of divided images to be compressed arbitrary and shorten the processing time. There is a particular thing.

(E) Structure of the Invention The image data compression circuit according to the present invention reads and binarizes a line image drawn on grid lines of a predetermined pitch by pixel scanning at a pitch of 1/Q of the predetermined pitch. Target data.

The structure of the invention includes a first area signal generation unit that generates a timing signal indicating m areas set by dividing a divided image area cut out into squares in units of intersections in the main scanning direction with the intersections of grid lines as the center. m according to the state in the m regions generated by the circuit and the first region signal generation circuit of the Q-bit image data obtained by raster scanning the divided image region.
A first compression circuit compresses data into bit data, and a second compression circuit generates a timing signal indicating two areas set by dividing the divided image area in the sub-scanning direction.
of the area signal generating circuit and the state in the two areas generated by the second area signal generating circuit of the Q times of main scanning data obtained from the first compression circuit. a second compression circuit that compresses data into 2-bit data representing the presence or absence of a line image; a storage circuit that stores the data compressed by the second compression circuit; and a 90-degree rotation of the cut out divided image data. It consists of a rotation circuit and a switching circuit that switches between the cut out divided image data and the 90 degree rotated image data.

Then, regarding the one divided image data,
The first time uses the original image data and compresses it into 2-bit data that represents the presence or absence of a line image in the vertical direction, and the second time uses an image rotated 90 degrees to represent the presence or absence of a line image in the left and right directions. The image data of Q×Q bits in each divided image area is compressed to 4 bits.

(F) Embodiments of the Invention The contents of the present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 3 is a diagram showing the configuration of an embodiment of the present invention.

In the figure, 1 is a control circuit that controls each component.

2 is a line image drawn on grid lines of a predetermined pitch, expressed as binary data for each pixel, and stored in an image memory (not shown) on the host computer side, as illustrated in FIG. As shown by the dotted lines in FIG. 2, each divided image is divided into rectangles and cut out in units of grid line intersections, and each divided image is raster scanned and read, and is input from the image data bus CB. This is a switching circuit that switches the video signal S' obtained from the video buffer 6 and supplies it to the first compression circuit 3, which will be described later.

7 are area signals H1, H2, H3, H4, corresponding to areas A, B, C, and D set in the main scanning direction X in the divided image area shown in FIG. 4, as shown in FIG. This is a first area signal generation circuit that generates H5 and H6.

3 is the first one of the video signals supplied from the switching circuit 2 for each main scan of the divided image unit.
1 bit each (total 6 bits) according to the values in the six area signals H1, H2, H3, H4, H5, and H6 passed from the area signal generation circuit 7 of
The detailed operation will be described later.

Reference numeral 8 designates a second area signal generation circuit that generates area signals V1 and V2 as shown in FIG. 6 corresponding to areas E and F set in the sub-scanning direction Y of the divided image shown in FIG.

4 is an area signal V in the sub-scanning direction passed from the second area signal generation circuit 8 of 6-bit data obtained in each main scan in the first compression circuit 3.
This is a second compression circuit that compresses data into 2-bit data representing the presence or absence of a line image in the direction perpendicular to the main scanning direction according to the values in V1 and V2, and its detailed operation will be described later.

Reference numeral 5 denotes a buffer for temporarily storing data obtained in the second compression circuit 4.

A video buffer 6 temporarily stores the video signal of the divided image sent from the image data bus CB, rotates it by 90 degrees on the plane of the divided image, and sends out a read video signal S' in response to a request.

FIG. 7 shows the first compression circuit 3 in this embodiment.
The detailed circuit configuration is shown below. This circuit includes area signals H1, H2, and
When H3, H4, H5, and H6 and the video signals of the divided images are input, and the video signal for each scan is "1" in all pixels in areas A, A+B, D, and C+D, K1, respectively
Outputs "1" to K2, K5 and K6. Further, when there is "1" in at least one pixel in areas B and C, "1" is output to K3 and K4, respectively. This compresses the image data within one scanning line into 6-bit data of K1, K2, K3, K4, K5 and K6.

Taking the output K2 as an example, an area signal representing the area (A+B) is input to one input of the gate ○A, an inverted output of the video signal is input to the other input, and the AND is performed. The output is ORed by gate ○i, and register ○c is set by the area timing signal. In the case of a black pixel, the input of gate ○A is ``0'', and the AND cannot be obtained, so the output of gate ○A becomes ``1'', and the output of gate ○B becomes ``0'', which is set in register ○C. Ru. If there is even one white pixel in the area (A+B), the input of gate ○A will be "1", AND will be taken, the output of gate ○A will be "0", and the output of gate ○I will be "1". , this is set in register ○C, and its output "0" is fed back to gate ○I,
The output of gate ○a is always "1", and the state of register ○u is maintained. Finally, the state of the image in area (A+B) is set in register E by the end signal of one scanning line, and its inverted output becomes K2. That is, K2 is a signal that becomes "1" when all pixels in the area (A+B) are black, and becomes "0" when there is at least one white pixel.

In the case of output K3, the area signal representing area B is input to one input of gate ○O, and the video signal representing area B is input to the other input, and if there is even one black pixel in area B, register ○ ", and is set in the register ○ key by the scan end signal, and becomes the output of K3.

FIG. 8 shows the second compression circuit 4 in this embodiment.
The detailed circuit configuration is shown below. This circuit contains 6-bit data K1, K2, K3, K4, K5 and K6 obtained for each main scan in the first compression circuit 3.
Then, area signals V1 and V2 generated by the second area signal generation circuit 8 are input. In this circuit,
6-bit data K1, K2, K3, K4, K5
and K6, count the number of scanning lines that satisfy the following conditions. Condition calculations are performed using two inverters, two AND gates, and three OR gates.

L=(K3·2+K1)+(K6+5·K4) Region E (region signal V1) and region F (region signal V2) generated by the second region signal generation circuit 8 are used as the regions to be counted. This is performed using an AND gate that receives the condition signal L and the area signal V1 or V2 as input.

When the sub-transmission of the divided image area is completed, the value of the counter for each area is compared with the threshold value stored in the register in advance, and if the value of the counter is larger than the threshold value, it is determined that the value is established and the output is set to ``1''. ”.

If the result in area E is valid, it is determined that a line image exists in the upper direction, that is, in the direction shown in FIG. It is determined that the line image exists in the direction shown in . Thereby, the video signal S can be compressed into 2-bit data representing the presence or absence of a line image in the vertical (up and down) direction.

The operation of this embodiment will be summarized below.

(1) Select the video signal S side by the switching circuit 2, and input the video signal for reading the divided image area from the image data bus.

(2) The video signal is input to the first compression circuit 2, and at the same time, it is also input to the video buffer 6 and rotated by 90 degrees.

(3) In the first compression circuit 2, one main scanning video signal is processed in accordance with the state of the values in the six regions generated by the first region signal generation circuit 7 of the video signal for each main scanning. is compressed into 6-bit data.

(4) The second compression circuit 4 calculates the number of scanning lines in which the 6-bit data for each main scan inputted from the first compression circuit 3 satisfies a predetermined condition, and generates a second area signal. Count each two areas where the circuit 8 occurs, and if this is greater than the threshold, it is "1"
is output and stored in the buffer 5. As a result, the video signal S is compressed into 2-bit data representing the presence or absence of a line image in the vertical (up and down) direction.

(5) Next, the switching circuit 2 is switched to the video buffer 6 side, the image rotated by 90 degrees is scanned, and the read video signal S' is inputted to the first compression circuit.

(6) First compression circuit 3 and second compression circuit 4
operates in the same manner as (3) to (4), and the second compression circuit 5
outputs a 2-bit output to the buffer 5.
The video signal S' is obtained by scanning the divided image data in the Y direction, and this 2-bit data is
This is data indicating the presence or absence of a line image in the horizontal (left and right) direction (direction shown by or in FIG. 9).

(7) The 4-bit data stored in the buffer 5 can express any of the 16 types shown in FIG. 9 depending on the combination.

(8) By the operations (1) to (7), compression of one divided image data is completed, and the next divided image data can be compressed in the same manner.

(G) Effects of the Invention As explained above, according to the present invention, a line image drawn on grid lines of a predetermined pitch is divided into arbitrary sizes according to the pitch of the grid lines, and a pipeline process is performed to divide the line image drawn on grid lines of a predetermined pitch. Each divided image can be compressed into 4-bit data at extremely high speed.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a line image, FIG. 2 is a diagram showing an example of division of a line image, FIG. 3 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 4 is a diagram showing an embodiment of the present invention. FIGS. 5 and 6 are diagrams showing area signals in an embodiment of the present invention. FIG. 7 is a circuit diagram of the compression circuit of FIG. 1, and FIG. A circuit configuration diagram of a compression circuit. FIG. 9 is a diagram showing the correspondence between divided images and compressed data according to an embodiment of the present invention. In the drawing, 1 is a control circuit, 2 is a switching circuit,
3 is a first compression circuit, 4 is a second compression circuit, 5 is a buffer, 6 is a video buffer, 7 is a first area signal generation circuit, and 8 is a second area signal generation circuit.

Claims (1)

[Claims] 1. A line image drawn on grid lines of a predetermined pitch is read and binarized by pixel scanning of 1/Q of the predetermined pitch, and the amount of image data obtained is compressed. an image data compression circuit, which generates a timing signal indicating m areas set by dividing a divided image area cut out into squares in units of intersections in the main scanning direction with the intersections of the grid lines as the center; a region signal generation circuit, and a Q obtained by raster scanning the divided image region.
a first compression circuit that compresses the bit image data into m bit data according to the state in the m areas generated by the first area signal generation circuit; a second region signal generation circuit that generates a timing signal indicating two regions set by the first compression circuit; and a second region signal generation circuit that generates a timing signal indicating the two regions set by the first compression circuit. a second compression circuit that compresses into 2-bit data representing the presence or absence of a line image in the direction perpendicular to the main scanning direction according to the state in the two areas; and a memory that stores the data compressed by the second compression circuit. a rotation circuit that rotates the cut out divided image data by 90 degrees; and a switching circuit that switches between the cut out divided image data and the image data rotated by 90 degrees; The first time uses the original image data and compresses it into 2-bit data that represents the presence or absence of a line image in the vertical direction, and the second time uses an image rotated 90 degrees to represent the presence or absence of a line image in the left and right directions. An image data compression circuit characterized in that it is configured to compress image data of Q×Q bits in each divided image area to 4 bits by compressing the image data to 2 bits.