JPH0681244B2 - Image signal reduction processing circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image signal reduction process used when an image signal is reduced in the sub-scanning line direction in an apparatus that handles an image signal, such as a facsimile apparatus. It is about circuits.

[Technical Background of the Invention and Problems Thereof] For example, in a facsimile apparatus or the like, as shown in FIG. 1, a document 1 is fed in a direction of an arrow 2 and a photoelectric conversion element (not shown) at a constant interval 3 (for example, , CCD: Charge
Main scanning is performed by a Coupled Device) to capture an image signal. In this case, the constant interval 3 is usually determined on the basis that the line density in the sub-scanning direction is 7.7 lines per 1 mm (7.7 / mm).

The image signal thus obtained is used to determine the line density in the sub-scanning direction 7.
When transmitting at 7 / mm, the compressed image signal obtained by performing the coding compression for each line is transmitted.

However, if you want to shorten the communication time, or if you need to reduce the size of the original depending on the size of the recording paper of the receiver before sending it, for example, change the linear density in the sub-scanning direction from 7.7 / mm to 3.
Need to convert to 85 / mm. As a method of such conversion, conventionally, a method of extracting an image signal every other line or a logical sum of the image signal 4A of the 2n-th line and the image signal 4B of the 2n + 1-th line is created as shown in FIG. This is the reduced image signal 5
Is known.

However, according to the former method, when a slender line is drawn on the original in the sub-scanning direction, the slender line may disappear. Further, as is apparent from FIG. 2, the latter method uses the black bit as the reduced image signal when at least one bit of the original image signal for which the logical sum is formed is the black bit, so that the reduced image signal is used. There was a drawback that the signal became dark in general and white was crushed.

[Object of the Invention]

The present invention has been made to eliminate the above-mentioned drawbacks of the conventional method. The purpose of the present invention is to reduce the original image signal so that elongated lines disappear in the sub-scanning direction or the reduced image signal becomes blackish. It is an object of the present invention to provide a reduction processing circuit for an image signal that can obtain a reduced image signal that is more faithful to the original image signal than before.

[Outline of Invention]

Therefore, according to the present invention, in the image signal reduction processing circuit that obtains a reduced image signal by erasing a given original image signal for every plural lines, one line before or after the one line image signal to be erased Each bit of the image signal of No. 1 and the corresponding bit of the image signal of one line to be erased are compared, and if there is a change, the erased 1
The reduced image signal is obtained by leaving the bit of the image signal of the line and leaving the bit of the image signal of the one line before or after the image signal of the one line to be erased as for the bit that has not changed. Achieved the purpose. This also makes it possible to obtain a reduced image signal that is more faithful to the original image signal than before. However, in order to obtain a reduced image signal that is more faithful to the original image signal, in addition to the above configuration, as a result of the above comparison, if the bit at the same position of each line of the given image signal has changed a predetermined number of times continuously. In this case, the reduced image signal is obtained by leaving a bit of the image signal of one line before or after the image signal of one line to be erased.

Example of Invention

The configuration of the present invention will be described below with reference to the drawings. FIG. 3 is a diagram for explaining a case where one line is erased every two lines according to the present invention.

In this figure, 6 indicates an original image signal and 7 indicates a reduced image signal. If the first line of the original image signal 6 is the leading line, the image signal of this line is unconditionally left as the image signal of the leading line (first line) in the reduced image signal 7. Next, the even line is set as the line to be erased and the odd line is set as the line to be left, but the even line and the preceding odd line are compared, and a change is made between each corresponding bit (from the black bit to the white bit, or , The change from the white bit to the black bit), leave the bit of the even line,
If there is no change between each corresponding bit, the bits of the odd line after the even line are left.
That is, the second line, the fourth line, the sixth line, ... Are even lines and indicate the lines to be erased, and the third line, the fifth line.
The line, the seventh line, ... Are odd lines and indicate the remaining lines. In this case, when erasing the second line,
An exclusive OR (hereinafter referred to as EX-OR) of the second line and the first line, which is the preceding line, is created, and the resulting bit is "1" -that is, there is a change. −
In the case, the bit of the second line is left, and the bit of the above result is "0" -that is, when there is no change-, the bit of the third line is left and the bit in the reduced image signal 7 is left. Image signal of 2 lines.

Further, when erasing the fourth line, an EX-OR is made between the third line, which is the preceding line, and the fourth line. If the resulting bit is "1", the fourth line is erased. If the bit is left and the result bit is "0", the bit of the fifth line is left and is used as the image signal of the third line in the reduced image signal 7.

Hereinafter, when erasing the sixth line and erasing the not-illustrated eighth line, ..., 2n−2 line, the same process is performed, and the fourth line and the fifth line of the reduced image signal 7 are processed. .., line n. The 2nth line of the original image signal 6 will be erased.

Even if the image signal is reduced as described above, even if the line is an elongated line in the sub-scanning direction, each bit of the line formed by the elongated line is left due to a change from each bit of the previous line, and the logical Since the method does not depend on the sum, the reduced image signal 7 does not become blackish. But,
As shown in FIG. 4, in the case of the original image signal 8 consisting of each line in which the bit at the same position changes three times in succession, the reduced image signal 9 is obtained by performing the reduction as shown in FIG. ,
It is no longer true to the original image signal 8. Therefore, in the present invention, in such a case, the line to be originally left is left as it is. That is, in FIG. 4, the odd lines are the remaining lines and the even lines are the erasing lines. Therefore,
The first line, which is the first line, is directly used, and then the second line is further compared, and the fifth line is directly used as the first line, the second line, the third line, ... Of the reduced image signal 10, respectively. This makes it possible to obtain a reduced image signal 10 that is more faithful to the original image signal 8 even in the above case.

FIG. 5 shows an image signal reducing apparatus of a facsimile apparatus to which the method of the present invention is applied. In the figure, 11 is a document, and the document 11 is fed in the direction of arrow X. Reference numeral 18 denotes a light source, and the light emitted from the light source 18 is reflected on the original 11 and forms an image on the photoelectric conversion element 12. This light is photoelectrically converted by the photoelectric conversion element 12 into an electric signal, which is sent to the binarization circuit 13. The image signal that has been binarized by the binarization circuit 13 and converted into black bits and white bits is an image signal processing unit 14
Is sent to the image signal line buffer 15 and stored in the image signal line buffer 15 under the control of the image signal conversion control unit 17. The image signal stored in the image signal line buffer 15 is read by the image signal conversion control unit 17, subjected to the above-described reduction processing, sent to the image signal writing buffer 16, and stored therein. It The stored image signal is subjected to appropriate encoding / compression processing and transmitted.

FIG. 6 shows a block diagram of a concrete example of the image signal processing unit 14 of FIG. In the figure, # 1 to # 6 denote image signal line buffers, and the original image signal a is sequentially input to the image signal line buffers # 1, # 2, # 4, and # 5. The image signal line buffer # 3 is an EX of the image signals of the image signal line buffers # 1 and # 2.
The image signal line buffer # 6 stores the signal generated by EX-OR of the image signals of the image signal line buffers # 4 and # 5.

Reference numeral 19A denotes an input address counter, and 19B denotes an output address counter. Addresses are supplied to the image signal line buffers # 1 to # 6 in synchronization with the input clock b of the original image signal a supplied from a control circuit (not shown). give. Here, the address counter 19A is actually composed of two, and at the same time, the image signal line buffers # 3 (# 6) and # 5.
(# 2) Addresses can be output. Further, the output address counter 19B is actually composed of four,
Each of the image signal line buffers # 1 (# 4) and # 2 (#
5), corresponding bits of # 4 (# 1) and # 6 (# 3) can be designated at the same time.

The output of the image signal line buffer # 1 is the EX-OR gate 21.
A is given to the A terminal of the selector 20B and the C0 terminal of the selector 20C. The output of the image signal line buffer # 2 is given to the EX-OR gate 21A and the B terminal of the selector 20A. The image signal line buffer # 3 takes in the output of the EX-OR gate 21A, and the output of the image signal line buffer # 3 is the EX-OR gate 21A.
Given to D. The output of the image signal line buffer # 4 is E
It is given to the X-OR gate 21B and the A terminal of the selector 20A.
The output of the image signal line buffer # 5 is the EX-OR gate 21.
B, given to the B terminal of select 20B. The image signal line buffer # 6 takes in the output of the EX-OR gate 21B, and the output of the image signal line buffer # 6 is given to the EX-OR gate 21C. Further, the output of the EX-OR gate 21A is given to the EX-OR gate 21C and the AND gate 22A, and the other input terminal of the AND gate 22A has the EX-OR gate 2A.
Output of 1C is given. Further, the output of the EX-OR gate 21B is given to the EX-OR gate 21D and is given to the AND gate 22B, and the other input terminal of the AND gate 22B
The output of EX-OR gate 21D is provided. And gate 22
The outputs of A and 22B are given to the S terminals of the selectors 20A and 20B, respectively, and the signals given to the S terminals of the selectors 20A and 20B are
If it is high level, it is from B terminal, and if it is low level, it is A terminal.
Image signals respectively input from the terminals are output from the Y terminals. The outputs from the Y terminals of the selectors 20A and 20B are given to the C1 terminal and the C2 terminal of the selector 20C, respectively. Selector 20C
The image signal input from the C0 to C2 terminals is output from the Y terminal under the control of whether the signal supplied from the control circuit (not shown) to the A and B terminals is low level or high level.

The relationship between the signals applied to the A and B terminals of the selector 20C and the selected input terminals is as shown in the table below.

The reduced image signal c output from the selector 20C is stored in the address of the image signal write buffer 16 output from the write address counter 19C. The write address counter 19C also outputs an address in synchronization with the input clock b of the original image signal a supplied from a control circuit (not shown). In the above configuration, the components corresponding to the image signal conversion control unit 17 in FIG. 5 are the image signal line buffers # 1 to # 6 and the image signal write buffer 16 from the configuration in FIG.
Except for and.

In this embodiment, the operation will be described on the assumption that the image signals for two lines are written and then output to the image signal writing buffer 16 is started.

The original image signal a is transferred to the address of the image signal line buffer # 1 output from the input address counter 19A in synchronization with the input clock b supplied to the input address counter 19A.
The data is stored bit by bit and further sequentially in the image signal line buffers # 2 and # 4. In this way, the image signal line buffer #
When the original image signals are stored in 1 and # 2, the output address counter 19B gives an address to the image signal line buffer # 1 and sequentially reads the image signals. At this time, the control circuit (not shown) outputs high-level signals to the A and B terminals of the selector 20C, for example, and outputs the image signal input from the terminal C0 from the Y terminal. As a result, the original image signal of the first line stored in the image signal line buffer # 1 is directly output as the reduced image signal c to the image signal write buffer 16 and is stored in the address output by the write address counter 19C. Even while such an image signal is being read out, the image signal is stored in the image signal line buffer # 4 and thereafter by the input address counter 19A.

Next, the output address counter 19B outputs an address in order to read the corresponding bits of the image signal line buffers # 1, # 2, # 4, # 6. Then, the output from the EX-OR gate 21A is stored in the image signal line buffer # 3 by the input address counter 19A and at the same time the EX-OR gate 21A is stored.
21C, given to AND gate 22A. On the other hand, the initial image signal line buffers # 1 to # 6 have white bits (low level).
If the signal of is stored in all bits, EX-
A low level signal is supplied from the image signal line buffer # 6 to the other terminal of the OR gate 21C.
-The output of the OR gate 21C becomes high level. For this reason,
The AND gate 22A is controlled by the output of the EX-OR gate 21A and changes its output. The selector 20A outputs the image signal of the B terminal from the Y terminal when the input signal of the S terminal is high level, and outputs the image signal of the A terminal from the Y terminal when the input signal of the S terminal is low level. . Therefore, from the Y terminal of the selector 20A, a bit in the image signal line buffer # 2 and a corresponding bit in the image signal line buffer # 1 are compared and changed as in the case described with reference to FIG. When there is, the bit of the image signal line buffer # 2 is output, and when there is no change, the corresponding bit of the image signal line buffer # 4 is output. On the other hand, a control circuit (not shown) supplies a high level signal to the A terminal of the selector 20C and a low level signal to the B terminal. Then, the selector 20C outputs the image signal input from the C1 terminal from the Y terminal. The reduced image signal c reduced in this way is stored in the address of the image signal write buffer 16 output from the write address counter 19C.

Next, the output address counter 19B outputs an address in order to read the corresponding bits of the image signal line buffers # 4, # 5, # 1 and # 6. Image signal line buffer #
It is assumed that the new image signal is already stored in 1 or at least the bit to be read is already new. Then, the output from the EX-OR gate 21B is stored in the image signal line buffer # 6 by the input address counter 19A, and the output from the EX-OR gate 21D,
Given to AND gate 22B. In addition, EX-OR gate 21D
Since the corresponding bit of the image signal line buffer # 3 is given to the other input terminal of, the output of the EX-OR gate 21D becomes low level when the bit at the same position changes continuously for 3 lines, and 2 lines If it changes up to, it becomes high level.

If it is a change of up to two lines now, AND gate
22B is controlled by the output of the EX-OR gate 21B to change its output. The selector 20B outputs the image signal of the B terminal from the Y terminal when the input signal of the S terminal is high level, and when the input signal of the S terminal is low level,
The image signal from the A terminal is output from the Y terminal. Therefore, from the Y terminal of the selector 20B, as in the case described with reference to FIG. 3, the bit corresponding to the bit of the image signal line buffer # 5 is compared with the corresponding bit of the image signal line buffer # 4, and when there is a change. The bit of the image signal line buffer # 5 is output, and when there is no change, the corresponding bit of the image signal line buffer # 1 is output.

In addition, the bits at the same position of the sequentially input original image signal are 3
If the line changes continuously, EX-OR gate 21
Since the output of D becomes low level, the output of the AND gate 22B becomes low level regardless of the output of the EX-OR gate 21B. Therefore, a low-level signal is applied to the S terminal of the selector 20B, so that the image signal input from the A terminal is output from the Y terminal. As a result, the corresponding bit of the image signal line buffer # 1 is output from the Y terminal of the selector 20B, as in the case described with reference to FIG.

On the other hand, the control circuit (not shown) supplies a low level signal to the A terminal and a high level signal to the B terminal of the selector 20C. Then, the selector 20C outputs the image signal input from the C2 terminal from the Y terminal. The reduced image signal c thus reduced is stored in the address of the image signal write buffer 16 output from the write address counter 19C.

Hereinafter, the original image signal a input in the same manner is reduced.
However, the control circuit (not shown) changes the signals applied to the A and B terminals of the selector 20C, but does not apply a low level signal to both terminals.

In this way, in this embodiment, when the image signal is reduced, it is compared whether or not the bits at the same position change a predetermined number of times in succession, and based on the comparison result, one line is set for every two lines. Since it is erased, the reduced image signal c that is true to the original image signal a
Can be obtained.

In the above embodiment, the line before the line to be erased and the line to be erased are compared, but the line after the erase and the line to be erased may be compared. In this case, a method of unconditionally erasing the first line of the original image signal and leaving the last line unconditionally may be used together.

Further, although the description of the embodiment and the above-mentioned description is about the case where two lines are reduced to one line, it is generally applicable to the case where one line is erased every n lines.

Further, in the above embodiment, even a special case as described in FIG. 4 is assumed. However, in general, an original image signal as shown in FIG. 4 is rarely obtained over several lines in one original, and in some cases it is not necessary to consider such a case. Therefore, the image signal line buffers # 3, # 6, EX-OR gate 21C, and
21D, AND gates 22A and 22B are removed, and EX-OR gate 2
The output of 1A is given to the S terminal of the selector 20A, and the EX-OR gate 21B
A circuit in which the output of the above is given to the S terminal of the selector 20B can be considered. In this case, the input address counters 19A and 19B do not need the address output function to the image signal line buffers # 3 and # 6.

With this configuration, the first line of the original image signal is left as it is, and then, when there is a change in the bit based on the EX-OR of the image signals stored in the image signal line buffers # 1 and # 2, The bit of the signal line buffer # 2 is left, and when there is no change in the bit, the bit of the image signal line buffer # 4 is left. Furthermore, image signal line buffers # 4, #
Based on the EX-OR of the image signal stored in 5, when the bit changes, the bit of the image signal line buffer # 5 remains, and when there is no bit change, the bit of the image signal line buffer # 1 remains. Be done. The same operation is performed thereafter, and the reduced image signal as described with reference to FIG. 3 is obtained. Also by this, a long line in the sub-scanning direction does not disappear and the reduced image signal does not become blackish, and a reduced image signal more faithful to the original image signal than before can be obtained.

Furthermore, in the embodiment, the image signal obtained by photoelectric conversion is described, but it can be applied to the case of reducing the image signal sent from another system, and its application range is extremely wide.

〔The invention's effect〕

As described above, according to the present invention, whether or not the bit at the same position changes a predetermined number of times continuously is compared, and the image signal is reduced based on the comparison result. A long line in the sub-scanning direction of the original image signal does not disappear, the reduced image signal does not become dark, and a reduced image signal more faithful to the original image signal than before can be obtained.

[Brief description of drawings]

FIG. 1 is a plan view showing scanning of an original, FIG. 2 is a view for explaining a conventional image signal reduction method, FIG. 3 is a view for explaining a configuration of the present invention, and FIG. 3 is a diagram for explaining the configuration of the present invention which is an improvement of FIG. 3, FIG. 5 is a block diagram of a main part of a facsimile apparatus to which the present invention is applied, and FIG. 6 is a block diagram of a reduction processing circuit according to the present invention. . 11 …… Original, 12 …… Photoelectric conversion element, 13 …… Binarization circuit,
14 ... Image signal processing unit, 15 ... Image signal line buffer, 16
…… Image signal writing buffer, 17 …… Image signal conversion control unit,
# 1 to # 6 ... Image signal line buffer, 19A ... Input address counter, 19B ... Output address counter, 19C ...
Write address counter, 20A to 20C Selector, 21
A-21C …… EX-OR gate, 22A, 22B …… AND gate

Claims (2)

[Claims] 1. A reduction processing circuit for an image signal, which obtains a reduced image signal by erasing a given original image signal for each one of a plurality of lines, in one line before or after the one line image signal to be erased. Comparing means for comparing each bit of the image signal and the corresponding bit of the one-line image signal to be erased, and as a result of comparison by the comparing means, the bit at the same position does not change continuously a predetermined number of times. For the changed bit, the bit of the image signal of the one line to be erased is left, and for the bit that has not changed, the one before or after the bit of the image signal of the one line that is erased is not used for the comparison. When the bit of the image signal of the line is left and the bit of the same position is changed a predetermined number of times as a result of the comparison by the comparing means, it is used for the comparison of the image signal of the one line to be erased. Reduction processing circuit of the field signal, characterized by comprising a control means for controlling to leave bits before or one line of the image signal after that are not even. 2. When erasing one line every two lines to obtain a reduced image signal, the control means sets the even line image signal as a line to be erased and unconditionally leaves the leading line. The image signal reduction processing circuit according to claim (1).