JPH06225119A - Picture processor - Google Patents

Abstract

PURPOSE:To obtain a picture processor with simple configuration by discriminating a specific color part in the discrimination area of a read original and editing a picture depending on the result of discrimination. CONSTITUTION:Picture data V read from an original by an original read section 1 are serially transferred to a density discrimination section 2 and a filter processing section 3. The density discrimination section 2 compares threshold levels THH, THL set by a control section 6 with the picture data V and outputs '1' to the filter processing section 3 in the case of only THL<V<THH. An output from the filter processing section 3 is binarized by a binarization processing section 4. A control signal generating section 5 generates a control signal by the operation from the output result of the filter processing section 3 and an output section 7 outputs the binary picture data according to the output result of the control signal generating section 5 and applies marker processing to, e.g. an original, then only the right parts from the marker are converted into white pixels to be outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus for performing image processing suitable for facsimile machines and the like.

[0002]

2. Description of the Related Art In a conventional image processing apparatus such as Facsimile, as shown in FIG. 30, an original 100 is illuminated by a light source 101 such as a fluorescent lamp, and the reflected light is converted into an electric signal by a photoelectric conversion device 102 such as a CCD. Instead, correction / A / D conversion device 103 performs correction processing such as shading correction and analog / digital conversion processing to obtain multi-valued image data output.

When binary image data is required for an output image such as facsimile, the binarization circuit 104 binarizes this multi-valued image data with a certain threshold value to obtain an output image. For example, when the multi-valued image data represents the density of a document, a portion having a density equal to or higher than the threshold appears as black, and a portion smaller than the threshold is output as white. Then, the multi-value output image or the binary output image is transmitted page by page or printed out on recording paper.

In the above cases, it is conceivable that there is a part of the document to be transmitted by facsimile which does not need or need to be transmitted, and the document may be edited and transmitted. In that case, in general, cut out the necessary part and paste it on other paper before sending the original, or
I had to hide the part I didn't want to send and then scan the original before sending.

On the other hand, as shown in FIG. 31, a necessary portion in a document is surrounded by a marker such as a highlighter pen, the marker portion is detected by a color scanner, and based on the result, editing such as deletion of image data is performed as shown in FIG. There is a way to do. Also, enter the area you want to edit in advance in the input device in the device,
There is also an apparatus having a function of editing the input result.

[0006]

However, when cutting and pasting originals to perform editing work, extra work is required in addition to sending, and it is necessary to make a separate copy of the originals to be saved. . On the other hand, in the case of using the color scanner for the reading unit to determine the marker portion, the cost increases as compared with the case of using a monochrome monochrome scanner. Further, when inputting an area to be edited in advance to an input device in the apparatus, an input device for specifying the area is required in addition to the image processing apparatus, resulting in problems such as increased cost and complication of the apparatus.

In order to solve the above problem, a method of judging the marker portion in the original from the density of the read image data and editing the image according to the judgment result can be considered, but the marker portion written for other than the purpose of editing is also possible. However, there is a problem in that it may be judged as an editing target portion and unnecessary editing may be performed.

[0008]

The present invention has been made for the purpose of solving the above-mentioned problems, and has the following structure as one means for solving the above-mentioned problems. That is, a reading unit that reads a document and outputs the reading result as image data for each pixel, a binarizing unit that binarizes the image data read by the reading unit, and a document in the document based on the image data from the reading unit. Determination means for determining the specific color portion, setting means for setting the determination area for the specific color of the determination means, counting means for counting the number of pixels determined to be the specific color portion in the setting area by the setting means,
And a conversion unit that converts the output image data of the line or the next line into white pixels when the count result of the count unit is equal to or larger than a predetermined value.

Alternatively, in place of the above-mentioned conversion means, there is provided control means for controlling so that an image is not output on the next line when the count result of the counting means is a predetermined value or more.
Further, a reading unit that reads the document and outputs the reading result as image data for each pixel, and a binarizing unit that binarizes the image data read by the reading unit,
Judging means for judging the specific color portion in the original from the image data from the reading means, setting means for setting the judgment area of the specific color of the judging means, and the specific color portion is judged within the setting area by the setting means. Counting means for counting the number of pixels, and when the counting result of the counting means is equal to or larger than a predetermined value, the binarizing result is output from the binarizing means on the corresponding line or the next line, and the counting means When the count result is less than the predetermined value, the conversion output unit that converts the output image data into white pixels and outputs the white pixels in the corresponding line or the next line is provided.

Further, in place of the conversion output means, when the counting result of the counting means is equal to or more than a predetermined value, the binarizing result of the binarizing means is output on the next line, and the counting means outputs the binarizing result. When the count result of <1> is less than a predetermined value, control means is provided so as not to output an image on the next line.

[0011]

With the above structure, an image in which a desired area can be surely deleted or edited with a simple structure by judging the specific color portion in the judgment area of the read document and editing the image based on the judgment result. It is possible to provide a processing device.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described in detail below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing the construction of the first embodiment according to the present invention. In the figure, 1 is a document reading unit that reads a document and outputs multivalued data corresponding to the read density, 2 is a density determination unit that determines the density of the multivalued image data output from the document reading unit 1, and 3 is a density. A filter processing unit that performs a filtering process on the determination result, a binarization processing unit 4 that performs binarization processing of multi-valued image data, and a control 5 that generates a control signal for the output processing unit from the output result of the filter processing unit. A signal generation unit, 6 is a control unit that controls the operation of the device, 7 is an output processing unit that performs output processing of the binarization processing result, and 8 is a synchronization signal generation unit that generates a synchronization signal of the device.

FIG. 2 shows a timing chart showing the relationship between the synchronizing signal and the image data in the first embodiment having the above construction. In FIG. 2, the image clock signal C
The LK, line sync signal, and page sync signal are output from the sync signal generator 8 to each component. The document reading unit 1 outputs the image data V in synchronization with this image clock signal.

The page synchronization signal is a signal indicating the beginning of the document, and the rising edge of this signal is the beginning of the first line of the read document. The line synchronization signal is a signal representing the beginning of each line, and the rising edge of this signal is the beginning of the line. FIG. 3 shows a detailed configuration example of the density determination unit 2 shown in FIG. In FIG. 3, 2-1 and 2-2 are comparators, V is multi-valued image data sent from the document reading unit 1, THH and THL are density threshold values, which are set by the control unit 6. In this embodiment, THH> THL is set. The comparator 2-1 outputs 1 when THH> V, and the comparator 2-2 outputs 1 when THL <V.
That is, the density determination unit 2 outputs 1 when THL <V <THH.

FIG. 4 shows an example of density histograms of a felt-tip pen (red), a highlighter pen and a character portion. In FIG. 4, the vertical axis of the graph is the density value of the multi-valued image data when one pixel is 6 bits (0 to 63) and represents the number of pixels within a certain area. From Figure 4, the felt-tip pen part has a density of 4
The maximum number of pixels is around 0 to 50, the density is around 20 in the highlight pen portion, and the density is around 62 and 63 in the character portion.

From the above results, it is shown that it is possible to separate the character portion and the marker portion according to the density. In this embodiment, in consideration of the above points, the filter processing unit 3 of this embodiment has a configuration shown in FIG. That is,
In this embodiment, the filter processing section 3 constitutes a 3 × 3 pixel matrix.

In FIG. 5, LB1 and LB2 are line buffers capable of storing image data for one line,
R1 to R9 are registers for accumulating a 3 × 3 pixel matrix pattern. The operation of the filter processing unit 3 of this embodiment will be described below with reference to FIG. In the figure,
(1) is the rising timing of the image transfer clock CLK, (2) is the line synchronization signal, (3) is the density determination result N output from the density determination unit 2, and (1) to M9 of the filter processing unit 3. Outputs of the registers R1 to R9, (5) is multi-valued image data V output from the document reading unit 1,
(6) is multi-valued image data VD output from the register 3
Is.

The density determination result N is the image transfer clock CL.
It is transferred serially in synchronization with K (1), and is transferred to the register R1.
And the line buffer LB1. Image data V
Are input to the line buffer LB1 in synchronization with CLK (1). The density determination result N output from the line buffer LB1 in synchronization with CLK (1) is stored in the register R4.
Is input to the line buffer LB2.

The image data V and the density determination result N are 1
It is output from the line buffer LB1 with a delay of the line, and the density determination result is output from the line buffer LB2 with a delay of two lines. The image data and density determination results input to the registers R1, R4, R7 in synchronization with the transfer of the image data V are stored in the registers R2, R5, R8, and the image data and density input in the registers R2, R5, R8. The judgment result is sequentially shifted in the registers R3, R6 and R9,
A 3 × 3 pixel matrix is constructed.

The broken line output to the binarization processing unit 4 shown in FIG. 5 represents the image data VD, and the solid line output to the judgment area setting unit 9 represents the density judgment result. In the filter processing unit 3, as shown in the circuit example of FIG. 5, when all of M1 to M9 from the registers R1 to R9 are "1", "1" is set.
Is output, and if even one of M1 to M9 has "0", "0" is output. By this filter processing, the density determination unit 2 prevents erroneous determination of the intermediate density portion of the edge portion of the character or figure and the highlighter portion.

FIG. 7 shows a detailed configuration of the binarization processing unit 4. The example shown in FIG. 7 is a circuit example of the simple binarization process. In FIG. 7, reference numeral 4-1 is a comparator that compares the multi-valued image data VD with the binarization threshold TH. The threshold value TH is set in the register 4-2 by the control unit 6. The comparator 4-1 outputs 1 when VD ≧ TH.

FIG. 8 shows a detailed configuration of the control signal generator 5. The configuration of FIG. 8 is a circuit diagram in the case of controlling to output the control signal of the next line to the output processing unit 7 when the number of pixels determined to be the marker by the determination region setting unit 4 is a certain number. In FIG. 8, reference numeral 5-1 is a counter, which counts when the EN input is 1 in synchronization with the rising edge of the clock. When the LD input is 0, the initial value is loaded in synchronization with the rising edge of the clock. Although the counter 5-1 is a hexadecimal counter in the present embodiment, the present invention is not limited to this.

Reference numeral 5-2 is a D flip-flop which, when the G input is 0, outputs the value of the D input to the Q output in synchronization with the rising edge of the clock. The operation of the control signal generator 5 of the present embodiment having the above configuration will be described below with reference to the timing chart shown in FIG. In addition, in FIG. 9, 1 line 1
An example in which a control signal is generated when the number of pixels is 0 and the filter processing result is 3 or more pixels and 1 is shown.

In FIG. 9, (1) shows the rising timing of the image clock CLK, (2) shows the line synchronization signal,
(3) is the output of the filter processing unit 3, (4) is the output of the determination area setting unit 9, (5) is the RCO output of the counter 5-1.
(6) is the Q output of the D flip-flop 5-2.
If the marker portion is present on the Nth line, the output (3) of the filter processing unit becomes 1. While in the judgment area and while the filter processing result (3) is 1, the counter 5-1 performs a counting operation in synchronization with the image clock (1). When the filter processing result is equal to or more than the set value in the judgment area, the RCO signal (5) of the counter 5-1 becomes 1 and thereafter, the counting operation is not performed until the end of the line, and the higher order is held.

When the line synchronizing signal (2) becomes 0, the output (6) of the D flip-flop 5-2 becomes 1 at the rising edge of the clock (1), and this output is output during the (N + 1) th line. The initial value is loaded in the counter 5-1. If the control signal of the next line is output instead of the control signal of the next line, the RC of the counter 5-1 is output instead of the output of the D flip-flop 5-2.
The O output may be output as a control signal.

Thereafter, the same operation is repeated while reading the original. FIG. 10 is a diagram showing a detailed configuration of the output processing unit 7. In FIG. 10, 7-1 is a D flip flop. With the configuration of FIG. 10, when the output signal of the control signal generator 5 becomes 1, white pixels are output from the D flip-flop 7-1 in synchronization with the clock, and conversely, the control signal generator 5
When the output is 0, the binarization result from the binarization processing unit 4 is output from the D flip-flop 7-1 in synchronization with the clock.

FIG. 11 shows the detailed structure of the judgment area setting section 9. In the present embodiment, the determination area is set by the determination area setting unit 9 to prevent erroneous determination of the marker portion written for purposes other than the editing purpose. In FIG. 11, reference numeral 9-1 is a counter, and when LD is 0, the initial value 0 is loaded in synchronization with the rising edge of the clock. 9-
2, 9-3 are registers, 9-4 and 9-5 are counters 9.
A comparator for comparing the output of -1 with the output of the register 9-2 or the register 9-3, and outputting 1 when they are equal, 9
-6 is a JK flip flop.

The operation of the judgment area setting section 9 will be described below with reference to the timing chart of FIG. In the figure, an example is shown in which the third pixel from the beginning of the line is the start of the determination area and the tenth pixel is the end of the determination area. In FIG. 12, (1) is an image clock, (2) is a line synchronization signal, (3) is an output value of the counter 9-1, (4) is a set value of the register 9-2, and (5) is a register 9-. Set value of 3,
(6) is the output of the comparator 9-4, (7) is the output of the comparator 9-5, and (8) is the output of the JK flip-flop 9-6.

The set values in the registers 9-2 and 9-3 are the start and end values of the judgment area, and the values may be stored in the ROM or the like for each size of the read document or each position in the document. . When the line synchronizing signal (2) becomes 0, the output (8) of the JK flip-flop becomes 0, and the initial value 0 is set in the counter 9-1 in synchronization with the image clock (1).

When the line synchronizing signal (2) is 1, the counting operation is performed in synchronization with the clock (1). Counter 9-
When the output (3) of 1 and the set value (4) of the register 9-2 become equal, the output (6) of the comparator 9-4 becomes 1, and the Q output (8) of the JK flip-flop is synchronized with the image clock (1). ) Becomes 1. When the output (3) of the counter 9-1 and the set value (5) of the register 9-3 become equal, the output (7) of the comparator 9-5 becomes 1, and the JK flip-flop is synchronized with the image clock (1). Q output (8) becomes zero. The section where the Q output (8) of the JK flip-flop is 1 is the range of the judgment area.

Next, the overall operation of this embodiment having the above configuration will be described. The image data read from the document by the document reading unit 1 is processed by the image processing unit (detailed configuration of the document reading unit 1 is shown in FIG.
C processing or the like is performed, analog / digital conversion is performed, the image data V is serially transferred, and the image data V is sent to the density determination unit 2 and the filter processing unit 3.

The density determination unit 2 compares the threshold values THH and THL set by the control unit 6 with the image data V, and THL
Only when <V <THH, 1 is output to the filter processing unit 3. The output of R5 of the filter processing unit 3 is sent to the binarization processing unit 4, where the binarization processing is performed. The control signal generator 5 generates a control signal by the above operation from the output result of the filter processor 3. In the output unit 7, the control signal generation unit 5
The binary image data is output according to the output result of.

In this embodiment, in order to perform the processing for converting the line into the white pixel as described above, if the marker processing is performed at the middle left end of the document as shown in FIG. 13, the marker is displayed as shown in FIG. The white pixels are output to all the lines drawn with, and the other part is an image to which the binarized result is output. On the other hand, in the case where there is a marker portion near the center of the document as shown in FIG. 15, if the determination area is set to this range as shown by the broken line in the figure, only the portion to the right of the marker is white as shown in FIG. It is also possible to convert into pixels and output.

Further, in the present embodiment, it is not the case where no pixel is included in the marker portion (the pixel output as black by the binarization processing is not included) as shown in FIG. When the pixel is included in the marker portion, the pixel and the subsequent pixels in the line are converted into white pixels. This reduces restrictions on marking and facilitates designation. For example, as shown in FIG. 17, when the marker processing is performed on the portion including the pixel in the substantially central portion in the middle of the document, only the portion on the right side of the pixel in the line including the pixel in the marker portion is white as shown in FIG. It becomes a pixel, and the left side of the marker remains unchanged. Note that FIG.
In the figure, 151 indicates a pixel output as black by the binarization process, 152 is a marker part, and 153 is a pixel judged to be a marker part by the filter process.

In the above description, an example in which only the marker-processed line is converted into white pixels and output is described. However, control is performed so that the next line is converted into white pixels instead of the line. Is also good. In this case, if the designation is made as shown in FIG. 17, the line next to the line containing the pixels existing in the marker portion is sequentially converted to white pixels as shown in FIG.

In the case of the facsimile machine, for example, the output image for which the desired image trimming has been completed in this way is temporarily stored in the image memory and sent to the line via the line control unit etc. Will be sent to. (Second Embodiment) A second embodiment according to the present invention will be described below. In the second embodiment, edge enhancement processing or smoothing processing is performed in addition to the processing of the first embodiment.

FIG. 20 is a block diagram showing the configuration of the second embodiment according to the present invention. In the figure, the first shown in FIG.
The same components as those in the embodiment of FIG. In the figure, 9 is a judgment area setting unit, 10 is a register, and 1 is a register.
Reference numeral 1 is an edge enhancement processing unit, 12 is a filter processing unit that performs a filtering process on the density determination result, and 13 is an output processing unit.

The operation of the second embodiment having the above configuration will be described below, focusing on the differences from the first embodiment. The image data read by the document reading unit 1 and the density determination result from the density determination unit 2 are input to the register 10.
The register 10 is normally provided to configure a pixel matrix when performing edge enhancement processing or smoothing processing, and the configuration of the register 10 in this embodiment is shown in FIG.
In the configuration of the line buffers LB1 and LB2 of the filter processing unit 3 in the first embodiment shown in FIG. 1, the registers R1 to R9 may be configured to add one bit of the determination result to the number of bits of the image data. It can be realized additionally. Further, the filter processing unit 12 can be configured to include an AND circuit after each register unit output of the filter processing unit 3 in the first embodiment shown in FIG. The outputs of R2, R4, R5, R6, and R8 of the register 10 are input to the edge enhancement processing unit 11.

FIG. 21 shows the detailed construction of the edge emphasizing processor 11 of the second embodiment. The edge enhancement processing unit 11 of the second embodiment performs edge enhancement by the Laplacian filter shown in FIG. Inputs A, B, C, D and X in the figure are outputs of R2, R4, R6, R8 and R5 of the register 10, respectively. 11-1 is an adder that performs the operation of A + B + C + D, 11-2 is a multiplier that performs the operation of 4 × X, 11-3 is a subtraction that performs the (operation result of 11-2)-(the operation result of 11-1) , 11-4 is a constant multiple (α
Multiplier 11-5 is an adder for adding the calculation result of 11-4 to the pixel of interest X.

The edge-enhanced data from the edge enhancement processing unit 11 is sent to the binarization processing unit 4, where the binarization processing is performed, and the result is input to the output processing unit 7. FIG. 23
FIG. 7 is a diagram showing a detailed configuration of the output processing unit 7 in the second embodiment, and 7-1 is a D flip flop. In the figure, when the output signal of the control signal generator 5 becomes 1, the image output clock is not output. When the output of the control signal generator 5 is 0, the binarization result is synchronized with the image output clock by D
The output is from the flip-flop.

Since the second embodiment has such a configuration, for example, in the case of the original shown in FIG. 13, the image information of the marker portion is deleted, so that the output shown in FIG. 24 is obtained and the marker is pulled. Only the part that is not output is output. In this case, since the drawing is reduced in the sub-scanning direction, when the recording paper is roll paper, the reduced amount of paper is enough. There is also a merit that the communication time is shortened as compared with the case of transmitting one page of the original. Further, the edge emphasizing process does not affect the density determining unit 2, the control signal generating unit 5 and the like and does not hinder the editing operation, and the edge of the character can be clearly reproduced by this process.

In the case of a facsimile machine, for example, this output image is stored in the image memory and sent to the line by the line control unit. (Third Embodiment) FIG. 25 is a diagram showing the detailed construction of the output processing section 15 in the third embodiment of the present invention. In addition,
The entire apparatus may have the same configuration as that of the above-described first embodiment or second embodiment except for the output processing unit.
Further, the control signal generator 5 is configured to be able to output the control signal of the line or the next line when there is a pixel determined to be the marker portion, as in the case of the first embodiment.

Next, the operation of the third embodiment having the output processing section 15 shown in FIG. 25 will be described. In the following description, the parts different from the above-mentioned first and second embodiments will be mainly described. In the output processing unit 15 shown in FIG. 25, when the output signal of the control signal generation unit 5 becomes 1, the D flip-flop 7-1 outputs the binarization processing result in synchronization with the clock, and the control signal generation unit 5 outputs the binary signal. When the output is 0, white pixels are output.

With the above arrangement, in the third embodiment, when the document shown in FIG. 13 is processed, the output is as shown in FIG. 26, and the line in which the marker is drawn is binarized. The result is output, and the others are converted into white pixels and output. Also in the third embodiment, as in the case of the first embodiment, editing is possible even when there is a marker portion at an arbitrary position in the document. For example, when the document shown in FIG. 15 is processed, the output thereof is, as shown in FIG. 27, a result opposite to that of the output example of FIG. 16 which is the process in the first embodiment.

In the case of facsimile equipment, for example, this output image is stored in the image memory and sent to the line by the line control unit. (Fourth Embodiment) FIG. 28 is a diagram showing the detailed structure of the output processing unit 16 in the fourth embodiment of the present invention. The entire apparatus may have the same configuration as that of the above-described first embodiment or second embodiment except for the output processing unit 16. Further, the control signal generation unit 5 is configured to be able to output the control signal of the line or the next line when there is a pixel determined to be the marker portion as in the case of the second embodiment. There is.

The operation of the fourth embodiment will be described focusing on the parts different from those of the first and second embodiments.
In the output processing unit 16 shown in FIG. 28, when the output signal of the control signal generation unit 5 becomes 1, the D flip-flop 7-1 outputs 2 in synchronization with the clock signal from the synchronization signal generation unit 8.
The binarization processing result from the binarization processing unit 4 is output. On the other hand, when the output of the control signal generator 5 is 0, the output image clock is not output, and the binarization result of the binarization processor is not output.

In this way, in the output processing section 16,
When the output signal of the control signal generator 5 is 1 and the output signal of the binarization processor 4 is 1, the binarization processing result is output in synchronization with the clock from the synchronization signal generator 8, and the control signal generator When the output signal of 5 is 0, a white pixel is output. FIG.
When the original document No. 2 is processed in the fourth embodiment, the output is as shown in FIG. 29, and the result opposite to that in FIG. 24 in the second embodiment is obtained, and the marker is drawn. The image is output only for the line.

In the case of the fourth embodiment as well, as in the case of the second embodiment, the drawing is reduced in the sub-scanning direction, so when the recording paper is roll paper, the paper is reduced by the reduced amount. There is also a merit that the communication time is shortened as compared with the case of transmitting one page of the original. This output image is stored in an image memory in the case of the facsimile machine, for example, and is sent to the line by the line control unit.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0050]

As described above, according to the present invention, the specific color portion in the determination area of the read document is determined, and the image is edited based on the determination result. It is possible to provide an image processing device capable of deleting and editing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment according to the present invention.

FIG. 2 is a timing chart showing a relationship between a synchronization signal and image data in the first embodiment.

FIG. 3 is a diagram illustrating a detailed configuration example of a density determination unit illustrated in FIG.

FIG. 4 is a density histogram of a felt-tip pen (red) drawing portion, a highlighter pen drawing portion, and a character portion.

5 is a diagram showing a detailed configuration example of a filter processing unit shown in FIG.

FIG. 6 is a timing chart showing the operation of the filter processing unit.

FIG. 7 is a diagram illustrating a detailed configuration example of a binarization processing unit illustrated in FIG.

FIG. 8 is a diagram showing a detailed configuration example of a control signal generator shown in FIG. 1.

FIG. 9 is a timing chart showing the operation of the control signal generator.

10 is a diagram showing a detailed configuration example of an output processing unit shown in FIG.

11 is a block diagram showing a detailed configuration example of a determination area setting unit shown in FIG.

FIG. 12 is a timing chart showing the operation of the determination area setting unit.

FIG. 13 is a diagram showing an example of marking on a document in this embodiment.

FIG. 14 is a diagram showing an output image after the processing of the present embodiment is performed on the marker document shown in FIG.

FIG. 15 is a diagram showing an example of marking on a document according to the present embodiment.

16 is a diagram showing an output image after the processing of the present embodiment is performed on the marker document shown in FIG.

FIG. 17 is a diagram showing an example of marking on a document in this embodiment.

FIG. 18 is a diagram showing an output image after the process of the present embodiment is performed on the marker document shown in FIG.

FIG. 19 is a diagram showing another output image after the process of the present embodiment is performed on the marker document shown in FIG.

FIG. 20 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

21 is a block diagram showing a detailed configuration example of the edge enhancement processing unit shown in FIG. 20. FIG.

FIG. 22 is a diagram showing a configuration example of a Laplacian filter in the second embodiment.

23 is a diagram illustrating a detailed configuration example of an output processing unit in FIG.

FIG. 24 is a diagram showing an output image after the process of the second embodiment is performed on the marker document shown in FIG. 13;

FIG. 25 is a diagram illustrating a detailed configuration example of an output processing unit according to a third embodiment of the present invention.

FIG. 26 is a diagram showing an output image after the process of the third embodiment is performed on the marker document shown in FIG. 13;

27 is a diagram showing an output image after the processing of the third embodiment is performed on the marker document shown in FIG.

FIG. 28 is a diagram showing a detailed configuration example of an output processing unit according to the fourth embodiment of the present invention.

FIG. 29 is a diagram showing an output image after the process of the fourth embodiment is performed on the marker document shown in FIG. 13.

FIG. 30 is a block diagram showing the configuration of a conventional image processing apparatus.

FIG. 31 is a diagram showing an example of marking on a document in a conventional example.

32 is a diagram showing an output image after the conventional image processing is performed on the marker document shown in FIG. 31.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Document reading section 2 Density determination section 3,12 Filter processing section 4 Operation section 5,104 Binarization processing section 6 Control section 7, 15, 16 Output processing section 8 Sync signal generating section 9 Judgment area setting section 10 Register 11 Edge Enhancement processing unit 100 Original document 101 Light source 102 Photoelectric conversion device 103 Correction / A / D conversion device

Claims (6)

[Claims] 1. A reading unit for reading an original and outputting the read result as image data for each pixel, a binarizing unit for binarizing the image data read by the reading unit, and an image from the reading unit. The determination means for determining the specific color portion in the original from the data, the setting means for setting the determination area for the specific color of the determination means, and the number of pixels determined to be the specific color portion in the setting area by the setting means are set. An image processing apparatus comprising: a counting unit that counts; and a conversion unit that converts output image data of the line or the next line into white pixels when the count result of the counting unit is a predetermined value or more. 2. A reading unit for reading an original and outputting the read result as image data for each pixel, a binarizing unit for binarizing the image data read by the reading unit, and an image from the reading unit. The determination means for determining the specific color portion in the original from the data, the setting means for setting the determination area for the specific color of the determination means, and the number of pixels determined to be the specific color portion in the setting area by the setting means are set. An image processing apparatus comprising: a counting unit that counts; and a control unit that controls so that an image is not output on the next line when the count result of the counting unit is a predetermined value or more. 3. A reading unit for reading an original and outputting the read result as image data for each pixel, a binarizing unit for binarizing the image data read by the reading unit, and an image from the reading unit. The determination means for determining the specific color portion in the original from the data, the setting means for setting the determination area for the specific color of the determination means, and the number of pixels determined to be the specific color portion in the setting area by the setting means are set. Counting means for counting, and if the counting result in the counting means is equal to or more than a predetermined value, the binarizing result from the binarizing means is output in the corresponding line or the next line, and the counting result in the counting means Is less than a predetermined value, a conversion output unit that converts the output image data into white pixels and outputs the white pixels in the corresponding line or the next line is provided. An image processing device. 4. A reading unit for reading a document and outputting the read result as image data for each pixel, a binarizing unit for binarizing the image data read by the reading unit, and an image from the reading unit. The determination means for determining the specific color portion in the original from the data, the setting means for setting the determination area for the specific color of the determination means, and the number of pixels determined to be the specific color portion in the setting area by the setting means are set. Counting means for counting, and if the counting result in the counting means is equal to or larger than a predetermined value, the binarizing result from the binarizing means is output in the next line, and the counting result in the counting means is a predetermined value. An image processing apparatus comprising: a control unit that controls not to output an image on the next line when the number is smaller. 5. The image processing apparatus according to claim 1, wherein the determination unit determines the specific color portion in the document based on the density of the image data or the brightness data. 6. The counting means includes means for performing filter processing on the output result of the judging means, and means for counting the number of pixels judged to be a specific color portion by the filter processing. The image processing device according to any one of 4 above.