JPS5813066A - Picture size contracting system - Google Patents

Abstract

PURPOSE:To prevent shortage of information in the course of contracting operation of pictures and to reproduce the greater part of necessary information, by obtaining the OR of a picture element to be extracted and the adjacent picture element and using the OR as the picture information of the adjacent picture element. CONSTITUTION:A binary-coded picture signal 1 is supplied to a picture contracting circuit together with a picture signal clock 3 which indicates a reading timing. The picture signal clock 3 is extracted at the rate of one pulse per three pulses by a ternary ring counter 9 and becomes a contracted picture signal clock. In the same way, a phase advancing clock 5 supplied to an input terminal 6 also becomes a contracted phase advancing clock by another ternary ring counter 11 and is supplied to a flip-flop 7. In this way, a positive logical signal 15 is outputted from the Q-terminal of the flip-flop 7 and a contracted picture signal 16 is obtained at an OR circuit 8. The contracted picture signal 16 is outputted synchronously to the contracted picture signal clock 12.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image reduction method for reducing a winter image read by a reading device.The present invention relates to an image reduction method for reducing a winter image read by a reading device. , this may be transmitted to the recording device side. Conventionally, in such cases, one pixel was extracted every few pixels in both the main scanning direction and the sub-scanning direction, and a reduced image was created using the remaining pixels.0 Figure 1 shows an image reduction method like this. As an example, the principle of a method of removing pixels at a ratio of 1 to 3 pixels is shown. In this method, from Aa to C as shown in Figure i.
When reading an image made up of 14 pixels with 49 pixels in the G mode, first, in the first main scanning line consisting of pixels from Aa to Ag, 'pixels Ac and A'f are scanned.
remove it.

Next, in the second main scanning line, pixels Be and B
Remove f. The following pixel lines are reduced in the same way ′
Jkp will be formed. Pixels removed in this manner for each main and E-in are indicated with a square mark. Of the pixel lines created by this operation, the pixels Ca-Cg and 'FaxFg of the third and fifth lines are removed in the next reduction operation in the sub-scanning direction. Pixels that are discarded in units of pixel lines are marked with *. When the above operations are completed, a reduced image made of 25 pixels as shown in the same figure is obtained.

However, in such a small image 6d method, if the necessary information exists in the pixel or pixel line to be extracted, the lI! The drawback is that all of this information is lost in the process of reducing the Ii1 image, resulting in pixel distortion.

there were.

The present invention has been made in view of these circumstances, and it is an object of the present invention to provide an image reduction method that makes it possible to reproduce most of the necessary information in the removed pixels and pixel lines.

In the present invention, the above-mentioned object is achieved by calculating the logical sum of the pixel to be extracted and the adjacent pixel (9) and using this as the image information of the adjacent pixel described above.

The present invention will be described in detail below with reference to Examples.

In this embodiment, an example in which 3 pixels are changed to 2 pixels in the main scanning direction and 4 pixel lines are changed to 3 pixel lines in the sub-scanning direction will be described.

FIG. 2 shows an image reduction circuit in the main scanning direction. This circuit inputs the binarized image signal 1 t61
Signal 1 force 4 children 2'! '') It is equipped with three input terminals: an image signal clock input terminal 4 for inputting 0, 1, and 13, and a phase advance clock input terminal 6 for inputting a phase advance clock 5 whose phase is slightly ahead of that of the image signal clock 3. The image signal l input from the image signal input terminal 2 is supplied to the D terminal of the flip-flop circuit 7 and one input terminal of the OR circuit 8. The image signal clock 3 or the advanced phase clock 5 input from the advanced phase clock input terminal 6 is supplied to ternary ring counters 9 and 11 provided correspondingly. The output side of the counter 9 is connected to an image signal clock output terminal 13 that outputs a reduced image signal clock 12, and is connected to the other 3
The output side of the ring counter 11 is the C of the flip-flop circuit 7 which inputs the flip-flop input clock 14.
Connected to the KL terminal. The positive logic signal 15 output from the Q terminal of this flip-flop circuit 7 is output from the OR circuit 8.
1', whose output side outputs the reduced image signal 16.

It is connected to the image signal output terminal 17.

The operation of this image reduction circuit will be explained with reference to the chart shown in FIG. FIG. 3a shows the image signal l after being read by the image sensor and subjected to binarization processing. The image signal 1 is supplied to the image reduction circuit together with an image signal clock 3 indicating the timing at which each pixel should be read. Of these, the image signal clock 3 supplied to the clock input terminal 4 is
The pulse waveform is extracted by the ternary ring counter 9 at a rate of 1 pulse for every 3 pulses, and the reduced image signal clock 12
(Figure 3C). Similarly, the pulse waveform of the phase advance clock 5 (FIG. 3 d) supplied to the phase advance clock input terminal 6 is extracted by the ternary ring counter 11 at a rate of 1 pulse for every 3 pulses, and the flip-frog human clock 14
becomes.

Now, when the image signal 1 for the pixel 1a arrives at time t1a, this image signal 1 is supplied to the D terminal for data input of the flip-flop circuit 7, and the flip-flop circuit 7 is supplied to the flip-flop circuit 7 at time t2a. Set by input clock 14. At the same time, a positive logic signal 15 for the pixel 1a is output from the Q terminal of the 7-lip-flop circuit 7. At this point, the OR circuit 8 is supplied with the image signal 1 for the pixel la, so the image signal output terminal 17 outputs a reduced image signal 16 representing the pixel 1a. This reduced image signal 16 is output in synchronization with the reduced image signal clock 12 that occurs at time t3a, which is slightly later than times t and a.

At the next time t1b, the painting stage number 1 regarding the painting xtb
When the pixel 1b arrives, the data for this pixel 1b is set in the flip-flop circuit 7 at times t and b slightly later. At the same time, the pixel 1b is output from the Q terminal of the 7-lip-flop circuit 7.

At this point, the pixel 1b is supplied to the OR circuit 8, so the pixel 1b is output to the image signal output terminal.

However, since the reduced image signal clock 12 is not output at the time when this pixel 1b is output, the pixel 1b is not considered as an image signal. In this state, pixel 1 at time t1c
An image signal l for c arrives. The image signal 1 is supplied to the D terminal of the flip-flop circuit 7, but the flip-flop signal is not activated during the time period when the pixel IC is supplied to the image signal input terminal 1.

Since the cuff lock 14 does not arrive, the image signal for the pixel 1b is still output from its Q terminal. Therefore, at this time, the OR circuit 8 outputs the reduced image signal 16 obtained by logically ORing the image information of the pixel 1b and the image g1c to the image signal output terminal 17. This reduced image signal 16 is outputted in synchronization with the reduced image signal clock 12 generated at time t3c.
That is, the image information about the pixel 1b that should originally be discarded is incorporated into the image information of the next pixel IC and remains in the reduced image.

Similarly, the next pixel 1d becomes a pixel of a pixel line that makes up the reduced image, and the next pixel 1e becomes a different pixel by taking a logical OR with the next pixel 1f.
In this way, three pixels in the main scanning direction are changed to two pixels, and a new, smaller pixel line is created.

FIG. 4 shows an image reduction circuit in the sub-scanning direction. This image reduction circuit has a reduced image output from an image signal output terminal of the image reduction circuit in the main scanning direction shown in FIG.
It is provided with two input terminals: an image signal input terminal 21 for inputting q16, and a clock input terminal 23 for inputting a line clock 22 generated for each pixel line. The image signal input terminal 21 is connected to the first and second two-person AND circuit 24.2.
5, and gate control signals 27 and 28 are supplied from the ring counter circuit 26 to the other input terminal. 1st
The reduced image signal 29 output from the two-person AND circuit 24
is supplied to the first memory circuit 32 via the OR circuit 31.

The image signal read out from the first memory circuit 32 is outputted to the -reduced image signal output terminal 35 via the two-man AND circuit 33 and the OR circuit 34, and is also output to the OR circuit 31 since the output is not controlled by the AND circuit 36. The logical sum is calculated and written into the 110th memory circuit 32. The reduced image signal 37 output from the second two-person AND circuit 125 also undergoes similar signal processing. For this reason, the second memory circuit 38.2-person AND circuit 39.4
1 and an OR circuit 42.

The operation of this image reduction circuit will be explained with reference to the chart shown in FIG. The ring counter circuit 26 includes four signal output terminals 26A to 26D, and the line clock 22 (
In synchronization with the supply of Figure 5 e), the fifth
Gate control signals 27.28, 43.4 shown in figures a-d
Output 4 respectively. When the line clock 22 is generated in synchronization with the arrival of the first pixel line at the current side tL□, H()1i) is output from the first signal output terminal 26A.
The gate control signal 27 whose level has changed is output, and the gates of the AND circuit 24 are opened across two lines. At this time, the gate of the AND circuit 25 is closed by another gate control signal 28, so that the 1
The reduced image signals 16 for each line are written to corresponding addresses of the first memory circuit 32 via an OR circuit 31, respectively.

When the line clock 22 is generated in synchronization with the arrival of the second pixel line at time tL□ thereafter, the third gate control signal 43 is opened for only one line, and the signal from the first memory circuit 32 is synchronized with this. The 1247-minute image signal read out passes through the AND circuit 36, and is supplied to the OR circuit 31. The 0-OR circuit 31 performs the logical sum of the image signals of the first pixel line and the second pixel line. 9. The resulting 1
Image signals for 247 minutes are loaded into the first memory circuit 32.

At this time, the image signal of the first pixel line read from the first memory circuit 32 is supplied to the AND circuit 33;
At this point, the gate of the AND circuit 33 is closed, so no image signal is output to the reduced image signal output terminal 35.

When the line clock 22 is generated in synchronization with the arrival of the third pixel line at time tL, 3 thereafter, the three gate control signals 27, 28, and 43 invert their logic states. As a result, the image signal of the third pixel line passes through the AND circuit 25 and the OR circuit 42 and is sent to the second memory circuit 3.
8 is written.

At the same time, the image signal obtained by calculating the logical sum of the first and second pixel lines written in the first memory circuit 32 passes through the AND circuit 33 and the OR circuit 34 and is output from the reduced image output terminal 35. be done.

At the next time tL4, when the line clock 22 is generated in synchronization with the arrival of the fourth pixel line, the first and second pixel lines
The gate control signals 27,28 invert the logic state. As a result, the image signal of the fourth pixel line is written into the first memory circuit 32.

At the same time, the image signal of the third pixel line stored in the second memory circuit 38 passes through the AND circuit 39 and the OR circuit 34 and is output from the reduced image signal output terminal 35. 'When the line clock 22 is generated in synchronization with the arrival of the fifth pixel line at the next time tL5, the first and second pixel lines
The gate control signals 27, 28 invert the logic state. In addition, the image signal of the fifth pixel line is written into the second memory circuit 32.

At the same time, the image signal of the fourth pixel line written in the first memory circuit 32 passes through the AND circuit 33 and the OR circuit 34, and the reduced image signal is further transmitted at the next time tL6.
When the line clock 22 is generated in synchronization with the arrival of the sixth pixel line, the fourth gate control signal 44 becomes 1.
During the line, it changes to H level. As a result, the image signal of the fifth pixel line read out from the second memory circuit 38 and the image signal of the sixth pixel line are logically summed, and the image signal for one line obtained as a result of this is ORed. is written to the second memory circuit 38. At this time, the gate of the AND circuit 33 connected to the output side of the first memory circuit 32 opens.
Since the contents of the first memory circuit 33 have been cleared, no image signal is output from the reduced image signal output terminal 35.

Thereafter, when the ring counter circuit 26 repeats the same abrogation of the gate control signal, the reduced image becomes smaller in the sub-scanning direction] - 4 for the reduced reduced image.

The image signal is output. This image signal is read using a reduced image signal clock whose generation is suppressed at a rate of one pixel line for every four pixel lines.

As described above, according to the present invention, since multiple images are reduced by the logic circuit, there is an advantage that a device having a reduction function can be manufactured in a small size and at low cost.

In the embodiment, the vertical and horizontal reduction ratios of the images are different, but it goes without saying that the images may be reduced using the same reduction ratio. In addition, in the embodiment, the image is reduced independently in the main scanning direction and the sub-scanning direction, but the image information about the pixel to be extracted is divided into 2 to 8 equal parts, and the image information is divided into 2 to 8 equal parts, and Of course, it is also possible to perform a logical sum with the image information for the eight pixels to further reduce the loss of information.

[Brief explanation of the drawing]

Figure 1 is a principle diagram for explaining the conventional image reduction method.
Figures 2 to 5 are for explaining one embodiment of the present invention, of which Figure 2 is a circuit diagram of an image reduction circuit in the main scanning direction, and Figure 3 is a circuit diagram for explaining the operation of this circuit. 4 is a circuit diagram of an image reduction circuit in the sub-scanning direction, and FIG. 5 is a circuit diagram of an image reduction circuit in the sub-scanning direction. FIG. 3 is various waveform diagrams for explaining the operation of the circuit shown in FIG. 2... Image signal input terminal 8, 31.42. ...OR circuit 35...
・Reduced image signal output terminal Applicant Fuji Xerox Co., Ltd. Representative Patent Attorney Yusai Umesai Yamauchi l Hitoshi Sono 2 Figure 3 Threshold

Claims (1)

[Claims] Pixels or pixel lines that are adjacent to each other on one image are converted into one pixel or one pixel line as appropriate depending on the ratio to which the image is to be reduced, and image information about these pixels or pixel lines after conversion is A Peng image reduction method characterized in that information is obtained by taking the logical sum of pixels or pixel lines before "A'l" conversion.