JPS6364147A - Processing system for parity error - Google Patents

Abstract

PURPOSE:To evade that a normal device is judged to be abnormal and an error processing is executed by providing means, etc., to check whether or not a parity error is obtained when an abnormality exists at parity checking and interruption is executed. CONSTITUTION:When data in a memory are read, the data and a parity bit to the data are collated, parity checking is always executed and when the abnormality exists, NMI (Non-Maskable Interrupt) is raised. Thus, it is checked whether or not a parity error is obtained, and at the time of the parity error, an error retrying flag is turned on and re-reading is executed. In accordance with the memory area of the address of the memory, the data are read and parity checking is executed. As the result, when the parity error does not exist, the memory is normal, and therefore, a parity error retrying flag is turned off, and RTI (Return from Interrupt) is obtained. Thus, it can be evaded that a normal device is judged to be abnormal and the error processing is executed.

Description

[Detailed Description of the Invention] [Summary] In order to avoid erroneously recognizing a normal device as having a failure due to a parity error caused by noise, etc., the error interrupt routine rechecks the memory error area and detects the error. If there is no such thing, it is not considered an obstacle.

[Industrial application field]

The present invention relates to a parity error processing method, and aims to eliminate erroneous recognition of parity errors due to noise and the like, and detect only true parity errors.

[Conventional technology]

There is a portable terminal equipped with a keyboard and memory, which the salesman brings and enters transaction data at the customer's home, connects it to the base unit when he returns to the office, and inputs the transaction data in memory into the base unit. It can be used for purposes such as

For parity checking, a parity bit is added to each byte of memory data in a portable terminal, and the parity is checked using the bit when reading the memory. When a parity error occurs, an interrupt is generated, the address where the parity error occurred is read, the parity error is displayed, and the portable terminal is sent for repair as a faulty device. The transaction data on the mobile device where this parity error occurred will be invalidated and will not be input to the base device, so this transaction data can be manually retrieved from the salesman's memory, memo, or data re-obtained over the phone. input.

[Problem that the invention seeks to solve]

By the way, even if a parity error occurs, it does not necessarily mean that the mobile terminal is malfunctioning; it may be due to electrostatic noise entering the memory when reading data, destroying part of the read data, resulting in a parity error, or a parity error interrupt. There are cases where the signal has gone up. In such a case, there is no abnormality in the memory, so it is problematic to assume that a parity error has occurred or that the device is defective.

The present invention aims to improve this point and check whether a true parity error has occurred using a simple means.

[Means for solving problems]

The parity error processing method of the present invention performs a parity check by comparing the data with the parity bit added to the data when reading memory data.
There is a means to raise the interrupt if it is abnormal, a means to check whether or not there is a parity error when the interrupt is raised, and a means to check whether or not there is a parity error when the interrupt occurs, and a means to move to the parity error interrupt routine and check whether the parity error retry flag is on or not. means for checking, means for performing parity error processing if the flag is on, and means for turning on the flag and setting the first address of the memory address range in which the parity error has occurred in an address storage area if the flag is off. and a means for parity checking the data read from the memory, and if there is no error, setting the next address and checking the parity of the next data, and a means for reading to the end of the memory address range, checking the parity, and detecting an error. If there is no error, the parity error retry flag is turned off and the routine is exited.

[Effect]

According to this processing method, it is possible to avoid by a simple means that the parity check circuit operates due to noise or the like, and a device that is not abnormal is judged as abnormal and an error process is performed.

〔Example〕

To explain with reference to the drawings, in the present invention, a portable terminal is provided with the illustrated processing means. A parity check is always performed on the memory of the terminal, and if a parity error occurs at this time, an NM I (Non Maskable Inter
rupt) rises. Therefore, the processing program moves from reading the memory to the routine shown in the figure, and first determines whether it is a parity error.
Check. This can be determined from the bit in the interrupt register (parity error determination bit). If it is not a parity error, the process moves to another process depending on the type of interrupt. If it is a parity error, the process moves to the parity error interrupt routine and the parity error retry flag is set. Check whether it is on or not.

Initially, this flag is off, then this flag is turned on, and the memory address where the parity error has occurred is set in the address storage area to read out the memory again. When a parity error occurs, the memory address is stored in a register, but only a portion of the address is stored, rather than the full address. That is, the memory address of this portable terminal is four hexadecimal digits 0000 to FFFF, but only the upper two digits are stored in the register as an error address, for example, in the case of 25XX, only 25.

Then, 2500 is written to the address storage area, and the data at this address is read out and parity checked. If there is no abnormality, it is incremented to 2501, and the data at this address is read and parity checked. In the same manner, up to 25 FFs are read out, and when the parity check is performed, the corresponding area check is completed.

If there is no parity error during this time, the memory is normal, and the parity error retry flag is turned off.
(Return from Interrupt
) Exit from the L/lever interrupt routine.

If a parity error is detected during the recheck, NMI goes up and the routine returns to the beginning. It is checked whether there is a parity error, and if YES, it is checked whether the parity error retry flag is on, and since it is YES in this case, the process moves to parity error processing, displays a device failure, and prompts for repair.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to avoid by simple means the parity check circuit malfunctioning due to noise or the like, and a device that is not abnormal is judged as abnormal and error processing is performed.

[Brief explanation of drawings]

The drawing is a flowchart showing the processing procedure of the present invention.

Claims (1)

[Scope of Claims] Means for performing a parity check by comparing the data with a parity bit for the data when reading data in a memory, and raising an interrupt if an abnormality is detected; means for checking whether or not there is an error; means for moving to a parity error interrupt routine and checking whether a parity error retry flag is on when a parity error occurs; and means for performing parity error processing if the flag is on; If the flag is off, means for turning on the flag and setting the first address of the memory address range where a parity error has occurred in the address storage area; parity checking the data read from the memory; and if there is no error, proceeding to the next step; means for setting the address of the memory address and checking the parity of the next data; and means for reading to the end of the memory address range and checking the parity, and if there is no abnormality, turning off the parity error retry flag and exiting the routine. A parity error processing method characterized by having the following.