JPS6362011B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a diagnostic function of an information processing device, and particularly to diagnosis when a shift pulse failure occurs.

(Prior art) Conventionally, in this type of information processing equipment, maintenance and replacement units (Field
Replaceable Unit) included multiple units for one shift unit.

(Problem to be solved by the invention) For this reason, when a failure occurs in the shift bus, multiple replacement units are required, resulting in a mean time to repair.
The drawback was that the To Repair (MTTR) was large. A conventional technique that compensates for the above disadvantages is to leave the device in the initial state, use the shift register function to output data for one shift unit including the faulty replacement unit, and transfer the data to the initial state of the device. There is a method of pointing out the exchange unit that caused the failure by comparing it with the data. When a shift register failure occurs in a device that initializes the device using the shift register function, the above method cannot set the device to its initial state, so multiple replacement units are required, and the average The drawback was that the time to repair (MTTR) increased.

Also, remember the initial state in advance,
This must be compared with the data outputting all bits using the shift register function, so
Another drawback was that it took time to point out the exchange unit.

An object of the present invention is to advance the clock so that when either a shift register including a plurality of exchange units or a memory element of each shift unit fails, the clock always becomes "1" and "0". At least, the above-mentioned drawbacks can be solved by using a predetermined memory element provided in the replacement unit, so that the replacement unit can be easily pointed out regardless of the initial state of the device, thereby reducing the average recovery time when the system goes down. An object of the present invention is to provide an information processing device configured as follows.

(Means for Solving the Problems) An information processing device according to the present invention includes a plurality of memory elements and a logic circuit network that connects the plurality of memory elements to form a plurality of selectable shift registers. It is constructed by comprising clock supply means, data input means, data output means, shift mode designation means, and "0"/"1" input means.

The clock supply means is for specifying one of the plurality of shift registers and supplying a predetermined number of clocks.

The data input means is for serially inputting data into one of the designated registers in accordance with the supply of a clock.

The data output means is for serially outputting data from one of the designated registers in response to the supply of a clock.

The mode specifying means is for validating the data input means and the data output means.

The "0"/"1" input means enables the shift mode specifying means and does not specify the shift mode.
This is for inputting "0" and "1" into a plurality of storage elements of one designated shift register when a predetermined number of clocks are supplied to one designated register.

(Example) Next, the present invention will be described in detail with reference to the drawings.

In FIG. 1 showing an embodiment of the present invention, an information processing apparatus according to the present invention includes a plurality of memory elements 1a-1.
-1a-n, 1b-1 to 1b-n, and the plurality of memory element groups 1a,
1b, a plurality of shift registers 3a, 3b, a shift register specifying circuit 4 for specifying one of the plurality of shift registers 3a, 3b, and shift registers 3a, 3b. a clock supply circuit 6 for supplying a predetermined number of clocks to one of the shift registers 3a and 3b through a decoder 5; and a shift-in input control circuit 7 for inputting data serially to the shift registers 3a and 3b in accordance with the supply of clocks. , a multiplexer 8 for selecting the output of the shift register 3a, 3b designated by the shift register designating circuit 4 from a plurality of shift registers 3a, 3b in accordance with the supply of the clock; and a multiplexer 8 for selecting data. , a shift-out output control circuit 9 for serially outputting data, a shift mode designation circuit 10 for enabling the shift-in input and shift-out output functions of the shift registers 3a and 3b, and a shift mode designation circuit 9. The shift register 3a, without enabling the shift mode of the circuit 10,
When a predetermined clock is supplied to one of the shift registers 3b, 0 input circuits 11a and 11b input "0" and "1" to a plurality of predetermined storage elements on this shift register, and input circuits 12a and 12b.
A shift buffer 13 that has a function of taking in data output by the shift-out output control circuit 9 and a function of supplying input to the shift-in input control circuit 7, and a maintenance diagnosis device 14 that can input and output data to the shift buffer 13. Consists of. In FIG. 1, 20 is a shift register designation signal line, 21 to 2
3 are CLK signal lines, 24 are shift mode (SM) signal lines, and 25 to 31 are data bus signal lines.

In FIG. 1, when there is no fault in the storage element 1a of the shift register 3a, the shift register 3a
The procedure for taking out the contents of the file to the shift buffer 13 will be explained.

First, the shift register designation circuit 4 selects the desired shift register 3a, the shift mode designation circuit 10 sets the shift mode (SM) to "1", and the clock supply circuit 6 selects the shift register 3a.
supplying clocks to Therefore, using the SO output control circuit 9, data is taken into the shift buffer 13 bit by bit from the shift out (SO) terminal. At this time, the shift in (SI) terminal of the shift register 3a is set to “0” by the SI input control circuit 7.
is input. In this way, shift register 3
When the contents of all memory elements of a are transferred to the shift buffer 13, all “0” is stored in the shift register 3a.
The contents of the file should be stored. In order to check this, the clock is further supplied to the shift register 3a just once, and the shift out (SO) is performed.
Check that the bit output from the terminal is “0”
Checked by SC output control circuit 9. At this time, if there is a failure in the mode where the bit is stacked in a certain storage element "1" of the shift register 3a, the bit output from the shift out (SO) terminal becomes "1" and becomes "1". ” failure can be detected. If normal, the clock is further supplied to the shift register 3a only once, and "1" is input from the shift-in (SI) terminal.
As a result, in the shift register 3a, the memory element of the shift-in (SI) input terminal becomes "1" by one bit.
Then, the contents of other memory elements become all "0". This “1” is called the last date (LSD),
Transferring the contents of the shift register to the shift buffer 13 in the above-described procedure is called scan-out. FIG. 2 is a flowchart showing the procedure of the scan-out operation.

Next, a procedure for transferring the contents of the shift buffer 13 to the shift register 3a after scan-out will be explained. First, the shift register designation circuit 4 selects the desired shift register 3a, the shift mode designation circuit 10 sets the shift mode (SM) to "1", and the clock supply circuit 6 supplies the clock to the shift register 3a to perform the shift. Using the shift-in (SI) input control circuit 7, data is transferred from the shift buffer 13 to the shift register 3a bit by bit from the input (SI) terminal. At this time, the data output from the shift out (SO) output terminal is
The SO output control circuit 9 checks whether it is "1" or "0".
If it is "1", the SO output control circuit 9 further checks whether clocks have been supplied for the total number of bits of the shift register 3a. If the clock is supplied for the entire number of bits and the process does not end normally, it is considered to have ended abnormally. This is because "1" is output in such an operation when the LSD that was last shifted in is shifted out when the above scan-out operation has completed normally, that is, when the clock is shifted out for the total number of bits. This is because it is limited to cases where it is supplied. Furthermore, when the data output from the shift out (SO) output terminal is "0", the SO output control circuit 9 further checks whether or not the clock has been supplied for the total number of bits of the shift register 3a. If the number of clocks equal to the number of bits is supplied, the shift-in from the shift buffer 13 to the shift register 3a is continued. If the shift out output is still "0" even though the clock has already been supplied for the total number of bits, this indicates a failure in which the contents of a certain storage element of the shift register 3a are stacked at "0", so the program terminates abnormally. do. Transferring the contents of the shift buffer 13 to the shift registers 3a and 3b using the above procedure is called scan-in. FIG. 3 is a flowchart showing the procedure of the scan-in operation.

After the scan-out operation and the scan-in operation, the diagnostic device 14 detects the signal line 3 forming the data bus.
1 to read the contents of the shift buffer 13, the contents of any shift registers 3a, 3b forming the logic circuit network 2 can be displayed. Furthermore, after the scan-out operation, the maintenance diagnostic device 14
The desired data is transferred to the shift buffer 13 using the data bus 30, and then a scan-in operation is performed. Thereby, desired data can be set in arbitrary shift registers 3a and 3b forming the logic circuit network 2.

FIG. 4 shows the shift register 3 in FIG.
A and 3b are shown in more detail, and MCP
(Multi-Chip Package) consisting of 9 maintenance replaceable units (Field Repleable Units: FRU) MCP
0 to MCP8 and the first one that implements the above nine MCPs.
Card C equipped with shift register 3a in the figure
It consists of 10. The card C10 forms a logic circuit network 2 consisting of a plurality of storage elements 1a and 1b, which is developed into one shift register 3a in FIG. Shift register 3a, 3
b is a connection between the shift-in (SI) terminal and shift-out (SO) terminal of each MCP unit, and the shift-in (SI) terminal of MCP8 is connected to the shift-in (SI) terminal of shift registers 3a and 3b. Terminal corresponds to shift register shift out (SO)
The shift out (SO) terminal of MCP0 corresponds to the terminal. Furthermore, the two bits of the memory element on the shift out (SO) terminal side of each MCP become 1 when the clock is supplied to the shift registers 3a and 3b without enabling the shift mode of the shift mode specifying circuit 10 in FIG. Input circuit 11a and 0
"1" and "0" are respectively input from the input circuit 11b. That is,
When a clock is supplied to the shift registers 3a, 3b without enabling the shift mode of the shift mode specifying circuit 10 on the shift registers 3a, 3b, the memory elements set to "1" or "0" are unconditionally set to "1" or "0". Nine bits are placed at predetermined positions corresponding to each MCP.

Next, the (x+1)th bit of MCP1 is “1”
The following describes the procedure for pointing out a replacement unit as a failure.

First, the contents of the shift register 3a constituted by MCP0 to MCP8 are scanned out to the shift buffer 13. Since there is a failure in the above "1" mode, "1" is output when one bit is output from the shift register 3a after all bits are output to the shift buffer 13 during the scan-out operation. Therefore, such scan-out operation ends abnormally. Next, shift mode designation circuit 1
0 is not used to specify the shift mode, and the clock supply circuit 6 supplies the clock to the shift register 3a only once. As a result, 0 input circuit 1
1a and 1-input circuit 12a, each
"0" and "1" are respectively set for the memory elements at predetermined positions in the MCP. Subsequently, when the contents of the shift register 3a are scanned out to the shift buffer 13, there is a failure in the "1" mode on the signal line forming the shift bus.
Until the MCP is output, the contents of the shift register 3a are output onto the shift buffer 13 so that data at predetermined positions in each MCP becomes "1" and "0". In this embodiment, only MCP0 outputs data at predetermined positions as "1" and "0". Therefore, from the above results, MCP
It is found that MCP1 has a "1" mode failure, and it is possible to point out MCP1 as a replacement unit. FIG. 5 is a transition diagram showing the state transition of the shift register 3a and shift buffer 13 due to this operation.

Next, the (x+1) bit of MCP1 is “0”
A method for pointing out a replacement unit as having a failure in the mode will be explained.

First, the contents of the shift register 3a are scanned out to the shift buffer 13. In the scan-out operation, a failure in the "0" mode is not checked, so at first glance it appears that the scan-out operation ends normally, but the data on the shift buffer 13 shows that the failure is in the "0" mode. The data that is subsequently shifted out of the storage element is
All of the data becomes 0 and becomes invalid data. Next, the contents of the shift buffer 13 are scanned into the shift register 3a. At this time, even if clocks corresponding to the total number of storage elements of the shift register 3a are supplied from the clock supply circuit 6, the last digit (LSD) "1" is not detected, and the scan-in operation ends abnormally, resulting in "0". mode of failure is detected. Next, without using the shift mode designation circuit 16 to designate a shift mode, the clock supply circuit 6 supplies a clock to the shift register 3a once. As a result, "0" and "1" are set in the memory elements at predetermined positions of each MCP by the functions of the 0-input circuit 11a and the 1-input circuit 12a, respectively. Subsequently, when the contents of the shift register 3a are scanned out to the shift buffer 13, the data at a predetermined position in each MCP is "0" until the faulty MCP in the "0" mode is output on the signal line forming the shift bus. The contents of the shift register 3a are output onto the shift buffer 13 so as to become "1" and "0". In this embodiment, only MCP0 outputs data at predetermined positions as "1" and "0". Therefore, from this result, it can be seen that MCP0 has a "0" mode failure, and MCP0 can be pointed out as a replacement unit. FIG. 6 is a transition diagram showing the state transition of the shift register 3a and shift buffer 13 due to such an operation.

(Effects of the Invention) As explained above, the present invention has the following advantages: In a system including a plurality of exchange units in an apparatus, when one of the storage elements on the shift register of one shift unit fails, the clock is advanced. By using a predetermined memory element provided in at least one exchange unit that always becomes "1" and "0" at this time, the exchange unit can be easily pointed out regardless of the initial state of the device. In this way,
This has the effect of shortening the time required to repair a failure when the system goes down.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. FIG. 2 is a flowchart showing the scan-out operation. FIG. 3 is a flowchart showing the scan-in operation. FIG. 4 is a block diagram showing a partial circuit configuration of the shift register shown in FIG. 1. FIG. 5 is a transition diagram showing state transitions of the shift register and shift buffer when one of the storage elements shown in FIG. 1 causes a "1" mode failure. FIG. 6 is a transition diagram showing the state transitions of the shift register and shift buffer when one of the storage elements shown in FIG. 1 causes a "0" mode failure. DESCRIPTION OF SYMBOLS 1...Storage element, 2...Logic circuit network, 3a, 3b...
Shift register, 4...shift register specification circuit,
5... Decoder, 6... Clock supply circuit, 7... SI input control circuit, 8... Multiplexer, 9... SO output control circuit, 10... Shift mode designation circuit, 11
a, 11b...0 input circuit, 12a, 12b...1 input circuit, 13...shift buffer, 14...maintenance diagnosis device, 20...shift register designation signal line, 21,
22, 23...CLK signal line, 24...Shift beat (SM) signal line, 25, 26, 27, 28, 29,
30, 31...Data bus signal lines.

Claims (1)

[Claims] 1. In an information processing device including a plurality of storage elements and a logic circuit network connecting the plurality of storage elements to form a plurality of selectable shift registers, specifying one of the plurality of shift registers. clock supply means for supplying a predetermined number of clocks; data input means for inputting data serially into the designated one register in accordance with the supply of the clocks; data output means for serially outputting data from the specified one register; shift mode designation means for enabling the data input means and the data output means; and activation of the shift mode designation means. When a predetermined number of clocks are supplied to the specified one register without specifying a shift mode, "0" and "1" are input to the plurality of storage elements of the specified one shift register. 1. An information processing device comprising: a "0"/"1" input means for inputting information.