JPH0553862A - Scan path diagnostic system - Google Patents

Abstract

PURPOSE:To obtain the scan path diagnostic system which can deal with the change of a scan path length without being conscious of the scan path length. CONSTITUTION:This scan path diagnostic system is composed of a diagnostic processor 1 and a main processor 2, which is provided with a diagnostic control part 3 and a scan path, connected to the processor 1. The diagnostic control part 3 serially connects integer (n) flip-flops 311-317 and operates the flip-flop groups 311-317 in the case of a scan operation by inputting scal path signals to the flip-flops 311-317 in the front step. Either any one of the flip-flops 311-317 in a temporary storage means 31 or the scan path signal is selected according to a select signal SEL from a selection holding means 32. A scan-in signal SIN selected by a selecting means 33 is impressed to the scan path of the main processor 2, and the information of the scan path is sampled by the diagnostic processor 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system including a diagnostic processor and a main processor diagnosed by the diagnostic processor, and more particularly to a scan path diagnostic system for diagnosing a main processor having a scan path.

[0002]

2. Description of the Related Art Conventionally, a scan path diagnosis method has been proposed as one of methods for diagnosing a processor. In this scan path diagnosis method, the inputs and outputs of the flip-flops in the main processor are switched to make all the flip-flops into one path, and the diagnosis processor collects the information in the path to diagnose an abnormality or the like. It is a thing.

FIG. 2 is a block diagram showing an information processing system for implementing a conventional scan path diagnosis method. Figure 2
As shown in, the diagnostic processor 101 sends a scan operation execution request on the diagnostic command D _CNT to the diagnostic control unit 103 of the main processor 102 and sends the scan data input signal D _IN . As a result, the diagnostic control unit 103 shifts the information in the path of the main processor 102 to obtain the information. As a result, the diagnostic processor 101 collects the scan data output signal D _OUT from the diagnostic control unit 103.

In this case, the scan data input signal D _IN and the scan data output signal D _OUT are serial signals, and one parity is generated and added to 8 bits of data in order to improve the reliability line. Then, in the input sections of the diagnostic processor 101 and the diagnostic control section 103, the validity of the data of the input signal D _IN and the output signal D _OUT is checked by using the parity bit thereof.

In the conventional scan path diagnosis method described above, the scan data input signal D _IN and the scan data output signal D _OUT are designed to be sent with 1 parity for 8 bits of data. It is necessary that the sum of the bits of the scan paths in the processor is an integral multiple of 8, and if the total is not an integral multiple of 8, it is necessary to add a dummy flip-flop.

[0006]

By the way, in recent years, LS
As the integration of I progresses, the bit length of one scan path increases, and if a configuration is adopted in which a plurality of LSIs are connected to form one scan path, all the LSIs will eventually be There was a problem that the length of the dummy flip-flop could not be determined until the design of was fixed.

When the scan path length is changed after the design is fixed, the number of dummy flip-flops must be readjusted each time, and the scan path length should be an integral multiple of 8. Had a problem that it greatly burdens the LSI design work.

Further, there is a problem that even if it is found that the scan path length is not an integral multiple of 8 after the LSI is completed, this cannot be dealt with.

In addition, when the scan path length is not an integral multiple of 8 due to the combination of LSIs, there is a problem that the method of diagnosing by the scan path cannot be adopted.

It is an object of the present invention to solve the above problems and to provide a scan path diagnosis system which can cope with a change in the scan path length without worrying about the scan path length.

[0011]

In order to achieve the above object, a scan path diagnostic system of the present invention comprises a diagnostic processor for forming various diagnostic signals, a diagnostic controller connected to the diagnostic processor, and a scan path. In an information processing system including a main processor, an integer n number of flip-flops are connected in series, a scan path signal is input to the frontmost flip-flop, and the above-mentioned flip-flop group can be operated during the scan operation. The temporary storage means, the selection condition holding means for forming a specific selection signal according to the selection instruction signal from the diagnostic processor, and any one of the flip-flops of the temporary storage means or the scan path signal are described above. Selection means for selecting according to a selection signal from the selection holding means, and selecting by the selection means described above. It is characterized in the use of output signals as a scan path input signal at the scan path of the main processor.

Here, the selection condition holding means may be composed of an integer of m flip-flops so that 2 ^m kinds of selection signals can be formed in response to a selection instruction from the diagnostic processor.

At least 2 ^m = n + 1 is established between the m flip-flops of the holding means and the n flip-flops of the temporary storage means.

[0014]

Next, the present invention will be described based on the illustrated embodiments.

FIG. 1 is a block diagram showing an embodiment of the scan path diagnosis system of the present invention. The information processing system to which the scan path diagnosis system shown in FIG. 1 is applied is
The diagnostic processor 1 includes various diagnostic signals and a main processor 2 that is diagnosed by the diagnostic processor 1. The main processor 2 is the diagnostic processor 1
The diagnostic control unit 3 connected to the computer and a scan path (not shown). The diagnostic processor 1 is the main processor 2
The scan operation execution request is sent on the diagnostic command D _CNT and the scan data input signal D _IN is sent to the diagnostic control unit 3. As a result, the diagnostic control unit 1
03 obtains the information by shifting the information in the path of the main processor 102, so that the diagnostic processor 101 obtains the scan data output signal D _OUT from the diagnostic control unit 103.

Here, the diagnosis control unit 3 has a temporary storage device 31, a selection condition holding means 32, and a selection means 33 in addition to a conventional processing circuit (not shown).

The temporary storage device 31 is composed of, for example, seven flip-flops 311 to 317. The flip-flops 311 to 317 each include a set terminal S, a data input terminal D, and a data output terminal Q, and each of the flip-flops 311 to 317 outputs a clock when the input signal of the set terminal S becomes "1". The input signal of the data input terminal D is set in synchronization with a signal (not shown). Then, the flip-flop 311 causes the scan data input signal D _IN from the diagnostic processor 1 to be supplied to the data input terminal D, and its output terminal Q.
Are supplied to the input terminal D of the next-stage flip-flop 312, and the following flip-flops 317 are similarly connected in series. Each flip-flop 311 to 317
The shift mode signal SMD is input to each of the set terminals S. This shift mode signal SMD is used by the diagnostic control unit 3
It is the same signal that is generated in the main processor 2 for performing the scan operation of the main processor 2.

In the selection condition holding means 32, m is composed of, for example, three flip-flops (not shown), and a specific selection signal can be set by a selection instruction signal from the diagnostic processor 1.

The selection means 33 includes the scan data input signal D _IN from the diagnostic processor 1 and the flip-flop 3.
The signals from 11 to 317 are taken in, and one of these signals is selected and used as the scan-in signal S _IN for the main processor 2
Is supplied to the scan path (not shown). The selection means 33 performs a selection operation by the selection signal from the selection holding means described above. Further, the selection condition holding means is composed of an integer of m flip-flops, and 2 ^m kinds of selection signals can be set by a selection instruction from the diagnostic processor.

Further, m (7 in this embodiment) flip-flops 311 to 317 of the holding means,
N temporary storage means (three in this embodiment)
2 ^m ≧ n + 1 (2 ³ = 7 + 1 in this embodiment) is established between the flip-flop and the flip-flop.

The operation of the embodiment thus constructed will be described.

First, when the selection signal SEL set in the selection condition holding means 32 is "000", the selection means 33 selects the scan data input signal D _IN , and the selection signal SEL.
Is "001", the selection means 33 selects the flip-flop 311. When the selection signal SEL is "010", the selection means 33 selects the flip-flop 312.
... and so on. This relationship is shown in Table 1 below. The diagnostic processor 1 also stores this information.

[0023]

[Table 1]

Here, when the scan operation of the main processor 2 is performed, data is set from the diagnostic processor 1 to the selection condition holding means 32 so that the total bit length of the scan path of the main processor 2 becomes an integral multiple of 8. The diagnostic processor 1 causes the main processor 2 to perform the scan operation.

Now, if the total bit length of the scan path of the main processor 2 is 795 bits, 5 bits are insufficient to make the total bit length an integral multiple of 8. Therefore, the diagnostic processor 1 refers to Table 1 and sets "101" in the minute selection condition holding means 32. Then, the selection means 33 selects the flip-flop 315. As a result, the signal from the flip-flop 315 is output as the scan-in signal S _IN output from the selection means 33. The scan data input signal D _IN passes through the contents of the flip-flops 311 to 315, whereby the scan in signal S _IN becomes data to which 5 bits are added.
Therefore, the total scan path length of the main processor 2 is an integral multiple of 8, that is, 800 bits, and is output.

In the above embodiment, the case where the total bit length of the scan path of the main processor 2 is short by 5 bits due to an integral multiple of 8 is explained, but the case where it is short by 1 to 7 bits can be similarly explained.

[0027]

As described above, according to the present invention, the scan path data is guaranteed to be an integral multiple of 8 regardless of the total bit length of the scan path of the main processor. There is an effect that it is not necessary to be aware of the campus length, and the scan operation from the diagnostic processor can be surely performed even if the scan path length changes.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a scan path diagnosis system of the present invention.

FIG. 2 is a block diagram of an information processing system to which a conventional scan path diagnosis system is applied.

[Explanation of symbols]

 1 Diagnostic Processor 2 Main Processor 3 Diagnostic Control Unit 31 Temporary Storage Device 32 Selection Condition Holding Means 33 Selection Means 311 to 317 Flip-Flops

Claims (3)

[Claims] 1. An information processing system comprising a diagnostic processor for forming various diagnostic signals, and a main processor having a diagnostic control section and a scan path connected to the diagnostic processor. An integer n flip-flops are serially connected. A temporary storage unit that is connected and inputs a scan path signal to the frontmost flip-flop to enable the flip-flop group during a scan operation, and a selection that forms a specific selection signal according to a selection instruction signal from the diagnostic processor. Condition holding means and selection means for selecting any one of the flip-flops of the temporary storage means or the scan path signal by the selection signal from the selection holding means, and the output signal selected by the selection means Characterized by being used as the scan path input signal in the scan path of the main processor Scan path diagnostic system. 2. The scan path diagnosis according to claim 1, wherein the selection condition holding means is composed of an integer m flip-flops and can form 2 ^m kinds of selection signals in response to a selection instruction from a diagnostic processor. system. 3. The m 2 flip-flops of the holding means and the n flip-flops of the temporary storage means have a relationship of 2 ^m ≧ n + 1. Scan path diagnostic system.