JPS62204172A - Multiplexing deagnosis system for scan route - Google Patents

Abstract

PURPOSE:To detect whether an FF circuit is normal or not accurately by operating a switching means, and dividing a route extending to the FF circuit and taking a diagnosis. CONSTITUTION:A scan route consists of a decoder 4 which outputs a switching signal for multiplexers 5 (5-1-5-(n-1)) and a register 3 which sends information to the decoder while respective FF circuits 1 (1-1-1-n) are provided with multiplexers 5 (5-1-5-(n-1)). Then when the scan loop of the FF circuit 1 is checked, data is stored in the register 3 and the decoder 4 decodes it to make a connection with the multiplexer 5. Therefore, the FF circuits 1 are connected in series, a scan input is supplied from a point A, and the signal is checked to check the loop of the FF circuit 1. Thus, whether or not the FF circuits are normal is detected accurately.

Description

[Detailed Description of the Invention] [Summary] The present invention is a scan method for diagnosing a group of flip-flop circuits by connecting flip-flop circuits in series and sequentially shifting the input data. In addition, a switching means for switching routes is provided to enable route switching and improve the efficiency of diagnostic processing.

[Industrial application field]

The present invention relates to a scan route multiplexing diagnosis method, and more particularly to a multiplexing diagnosis method for a large-scale integrated circuit equipped with a plurality of flip-flop circuits.

Recently, devices have been using many large-scale integrated circuits (hereinafter referred to as LSI). This LSI is increasingly required to have a high density. This LSI uses a plurality of flip-flop circuits (hereinafter referred to as FF circuits). Therefore, there is a need for a scan route multiplex diagnosis method that can efficiently determine the quality of a large number of FF@roads.

[Conventional technology]

Conventionally, when diagnosing FF circuits built into LSIs, each FF circuit has an internal OR circuit, as shown in FF circuit 1-1 in Figure 2, and an FF circuit that is activated by scan input is used. Output terminal B of circuit 1-1 and next OFF circuit 1-2
are connected in series so as to connect the scan input terminals A of the two.

Normal data is input as shown in FIG. 2, and the outputs are used for different purposes. Furthermore, a clock terminal C is provided for shifting scan input data to the next FF circuit.

Therefore, data is input from the scan input terminal A of the FF circuit 1-1, and the data is shifted until the final FF circuit 1 is input.
A scan method was used in which output terminal B of -n was determined to determine the quality of a group of FF circuits connected in series.

[Problem that the invention seeks to solve]

The conventional method described above is effective when the number of FF circuits mounted on an LSI is relatively small, but as LSIs become denser and the number of FF circuits mounted increases, There is a problem that it becomes difficult to detect the circuit.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional situation, it is an object of the present invention to provide a scan route multiplexing diagnosis method that can efficiently detect a faulty FF circuit.

[Means for solving problems]

In the present invention, the route of the FF circuit is divided as shown in FIG. 1, and the switching means 2 are provided at the division points.

[Effect]

Diagnosis is performed by activating the switching means 2 to divide the route spanning the FF circuits 1-1 to 1-n. Therefore, it is possible to accurately detect whether the FF circuit is good or bad.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention, and each F
A multiplexer 5-1 is provided for each of the F circuits 1-1 to 1-n.
~5-(n-1) is provided. It is comprised of a decoder 4 that outputs switching signals for these multiplexers 5-1 to 5-(n-1) and a register 3 that sends information to the decoder 4. The switching means 2 is composed of the above-described register 3, decoder 4, and multiplexers 1-1 to 1-(1-n).

For example, when checking the scan loop of FF circuits 1-1 to 1-3, store data in register 3,
Decoder 4 decodes this and multiplexer 5-1
, 5-2 are connected to the D side, and the multiplexer 5-3 is connected to the E side. Therefore, the FF circuits Ll to 1-3 are connected in series. Perform scan input from point A, and
By checking the signal at the FF circuit 1-
Checks for loops 1 to 1-3 are performed.

The above explanation was based on three FF circuit loops, but any F.F.
Needless to say, the same holds true for loops with F circuits. Note that (1) [Although the explanation has been made regarding the FF circuit inside the LSI of 1a, it may also be applied between LSIs.

Note that each of the multiplexers described above is preferably provided inside the LSI.

〔Effect of the invention〕

As is clear from the above description, the present invention achieves extremely effective effects in detecting failure points when applied to devices containing a large number of FF circuits, especially to diagnosis using the scan route method of LSI. Ru.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram for explaining a scanning method. In the figure, -1 to 1-n are FF circuits, and 2 is a switching means. ) The example is 17-Rotu 7121 Figure 1 Skianka Take 8 Awa Ming Uru R Kome - Block times Figure 2

Claims (1)

[Claims] A plurality of flip-flop circuits (1-1 to 1-n) are connected in series, input data is sequentially shifted to the flip-flop circuits, and the flip-flop circuits (1-1 to 1-n) are connected in series.
In the scan method for diagnosing the operation of item 1-n), the series-connected routes are divided into at least two routes, and a switching means 2 for switching the routes is provided, and the diagnosis is performed by switching the routes. Multiplexed diagnosis method for scan routes.