JPS62107596A - Pulse checking circuit - Google Patents

Abstract

PURPOSE:To check a shift pulse while a channel controller is initialized or operating and to facilitate maintenance by dividing continuously generated pulses from a pulse generator circuit into plural groups and ORing them in each group. CONSTITUTION:Shift pulses are ORed by output lines (a), (d) and (f), and applied to the clock input terminal CLK of a shift register 2. The output terminals B and C of the shift register 2 at the time of the 3rd pulse come to logics '0' and '1', respectively. The shift pulses are ORed by output lines (b), (e) and (g), and logics '0' and '1' appear on the output terminals B and C. The pulse of a line 13 is applied to the clock input terminal C of a D-type flip-flop 4, and a logic '1' appears on an output terminal Q. Logics '1' and '0' appear on the output of a NAND element 5 and that of a NAND element 6, respectively. The output of an EX-OR element 7 becomes a logic '1' and applied to the clock input terminal C of a D-type flip-flop 8. Then the output becomes a logic '1', and all eight shift pulses are decided to operate normally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The communication path control device receives instructions from the central control device and distributes information to the network and reads information.

Shift pulses are required to perform this sequential operation, but the generation status of these pulses is checked to confirm the normal operation of the device, and in the event of an abnormality, it is notified to the central control unit and the fault is dealt with. , which makes maintenance easier.

[Industrial application field]

The present invention relates to an improvement of a pulse check circuit in a communication path control device of a digital exchange system.

Digital exchanges have been widely accepted in the information society because they can handle both telephone communications and data communications, and have become a driving force for office automation, especially in the field of private branch exchanges.

FIG. 3 is a conceptual diagram of a digital exchange, where 31 is a network, 32 is a communication path control device, 33 is a central control device, and 34 is a subscriber circuit.

The switching connection is made by the central control unit 33 monitoring the status of the subscriber circuit 34 via the channel control unit 32 and learning the subscriber's request, and the central control unit 33 performs internal processing and
External processing including the network 31 and communication path control device 32 is performed to complete the desired connection.

The network 31 consists of a communication path memory and a control memory, and once stores digital voice information in the communication path memory, it performs time slot I conversion corresponding to the destination of the information based on the address information of the communication path memory recorded in the control memory.

The channel control device 32 receives order information from the central control device 33, and accesses the network 31 and anti-controls the central 4&l device 33, but internally generates shift pulses to perform sequential operations for this purpose. It is used as such. Since the shift pulse defines the operation of the channel controller 32, its proper operation is extremely important and checking of the shift pulse must be considered.

[Conventional technology]

A conventional pulse check circuit for shift pulses in a communication path control device is shown in FIG.

In FIG. 4, 1 is a pulse generation circuit, 21 is a NAND
Element 22 represents a D-type flip-flop.

When the synchronization signal is received from the central control device 33 together with the order information at the terminal ■, the pulse generation circuit 1 generates a plurality of pulses one after another to advance the operation of the channel control device 32. However, in the initial state of receiving the synchronization signal, the pulse generation circuit 1 The outputs of circuit 1 are still all logic 0, so they are passed through the inverter to N
All inputs to the AND element 21 have a logic value of 1, so the input terminal of the D-type flip-flop 22 has a logic value of 0, and the synchronization signal pulse applied to the clock terminal C of the flip-flop causes the output terminals Q and A logic value O appears at the terminal AS, indicating that the initial state is normal.

If any of the pulses in the pulse generating circuit 1 continues to be generated, a logical value of 1 appears at the terminal, indicating an abnormality, and the central control unit 33 can be requested to handle the failure.

[Problem that the invention seeks to solve]

As explained above, the operation of the pulse check circuit is limited to the initial state. However, there is a maintenance problem in that checking only in the initial state makes it impossible to know whether the communication path control device is operating normally. Therefore, it is desirable to continue checking even while the device is in operation.

[Means for solving problems]

The above problem can be solved by the pulse check circuit according to the present invention, which divides the pulses successively generated by the pulse generation circuit into 61 groups, inputs each group to each shift register, and includes a circuit for identifying the output. It is solved by

[Effect]

That is, the pulses generated one after another by the pulse generation circuit are divided into a plurality of groups, and by ORing within each group, a clock line with no overlapping pulses is created.
When input to each shift register corresponding to the clock line, an output corresponding to the number of pulses appears, but when this output is input to a comparison circuit, an output is output only when a fixed number of pulses arrive, indicating normal operation. If there is an abnormality, the central control unit can handle the failure.

〔Example〕

FIG. 1 shows a pulse check circuit according to an embodiment of the present invention,
2 and 3 are shift registers, 4 and 8.9 are D-type flip-flops, 5.6 is a NAND element, and 7 is an EX-OR
The element is shown.

FIG. 2 is an explanatory diagram of shift pulses for sequence operation of the call control device, and output lines a, b-h of the shift pulse generation circuit 1.
This shows how pulses are generated in response to. When reading information to the network, all 8 pulses are used, and when writing information, 6 pulses on output lines c and dxh are used.

The operation of the pulse check will be described below.

The shift pulses are ORed as a set on output lines a, d, and f, and three pulses appear on line 11. The pulse is applied to the shift register 2 input terminal CLK, and the 3
Output terminal B of shift register 2 at the time of the second pulse,
C has a logical value of 0.1. In the shift register 2, there are j and t, A is the output "::5", D is the data input terminal, R is the input terminal, and the sign of the shift register 3 is the same.

The shift pulses are ORed with another set of output lines S, a, and g, and three pulses appear on line 12. The output system of shift register 3; children B and C each have logical values 0. 1 appears in the same manner as above.

The pulse on line 13 is applied to the clock input terminal C of the D-type flip-flop 4, and since the power is applied to the data input terminal with a logic value of 1, the output terminal Q
A logical value of 1 appears in .

Expressed in another way, cotton 14, 15, 16, 17, and 18 have logical values of 0, 1, 0, 1, respectively. There will be an I. As a result, the output of NAND Soryo 5 is a logic value of 1, N
The logical value O appears at the output of the AND element 6, and therefore l1X-
The output of the OR element 7 has a logical value of 1 and is applied to the input terminal of the D-type solid flop 8. When the last soft pulse 1) is applied to the clock input terminal C of the D-type flip-flop 8, its output becomes logic 1 and 8
This means that it has been determined that all three shift pulses are working normally.

Here, the code of the D type flip-flop 8.9 is D
It has the same sign as type flip-flop 4.

Six shift pulses are used to occupy the information, but in this case the outputs of the NAND elements 5 and 6 have a logic value of 0.
．． 1, and the output terminal Q and therefore the terminal S of the D type flip-flop 8 exhibit a logic value of 1, which is inverse to the above case, and it is determined that the output terminal is functioning normally.

In the case of Schiff I/pulse generation other than the above, EX-
Of? The output of element 7 becomes a logic value O, and therefore the terminal S
Since the logical value becomes 0, indicating an abnormality, it is possible to request the central control unit 33 to handle the failure.

There is a D type flip-flop 9 for checking the initial state. In the initial state, lines LL12 to LL18 are all in a state of logical value 0, and if the previous check was normal, the end 7
-s indicates a logic value of 1, so when the synchronization pulse of order information is received from the central controller 33, the terminal ASW, which is the output of the D type flip-flop 9, becomes a logic value of 0, indicating normality. If any of the lines 11.12 to 1H has a logic value of 1, or if there was an abnormality in the main pulse check circuit last time and the terminal S shows a logic value of 0,
Since the terminal AS- has a logic value of 1, indicating an abnormality, it is possible to request the central control unit 33 to handle the failure.

In this way, it is possible to check the initial state of the channel control device and the shift pulses during operation.

[Effects of the Invention] As explained in detail above, according to the present invention, it is possible to check the initial state of the communication path control device and the soft pulses during operation 1, and in the event of an abnormality, the central control device is called and the fault is detected. This has the effect of facilitating processing and maintenance.

[Brief explanation of drawings]

, FIG. 1 shows a pulse check circuit according to an embodiment of the present invention, and FIG.
3 is a conceptual diagram of a digital exchange, and FIG. 4 is a conventional pulse check circuit. In the figure, 1 is a shift pulse generation circuit, 2.3 is a shift register, 4, . 8.9 is a D-type flip-flop, 5.6 is a NAND element, 7 is an EX-OR element, and 11 to 18 are lines. Large ff'J for the h ticket gate, Chadama distribution beggar ceremony I, 7th Duke of Gyo [Shipunsu] Power country shift, 2 res concubines, Hu tu rod 2 Kuchi no Bano, Chetsu 2a Xiu 1, Gu spear 3 Diagram Barnukeeff box of IL Jji'J "Saya 4th

Claims (1)

[Scope of Claims] A shift pulse generation circuit (1) that performs sequential operations to distribute information to the network and read information in a communication path control device that interfaces between a network of a digital exchange and a central control device. Divide the output lines of the shift pulses into groups, perform the OR of the output lines for each group, connect them to the shift register (2, 3), and further calculate the output lines of the shift pulses based on the output information of the shift register. A pulse check circuit comprising a circuit for checking the normality of all shift pulses of a generating circuit (1).