US3246305A

US3246305A - Message distribution system

Info

Publication number: US3246305A
Application number: US234392A
Authority: US
Inventors: Arneth August Philip
Original assignee: International Business Machines Corp
Current assignee: International Business Machines Corp
Priority date: 1962-10-31
Filing date: 1962-10-31
Publication date: 1966-04-12
Anticipated expiration: 1983-04-12

Description

A ril 12, 1966 A. P. ARNETH MESSAGE DISTRIBUTION SYSTEM Filed Oct. 51, 1962 BY y g f ATTORNEY .1 lllllllllllll m m. m w m 2 W m TL; W n m mi a mam x $5 -lIEIiIEIIL 3 "N8 W 8 3 w w r||!||i||.|| s s L mmn I O M7 2 N; s 22 mo 6 L M. Q n a w o w w w w m lwii J El 12 5 i a $2 Ha I 1 O v Iii}: 2 g a J w; 0 v mm O z Q m L United States Patent 3,246,305 MESSAGE DISTRHBUTHON SYSTEM August Philip Arneth, Roekville, Md, assignor to International Business Machines Corporation, New York, N .Y., a corporation of New York Filed Oct. 31, 1962, Ser. No. 234,392 6 Claims. (Cl. 34ill72.5)

The present invention is directed generally to a system for commutating messages and more specifically to a message commutation or distribution system employing a skipping counter.

The invention described herein was made in the performance of work under a NASA contract and is subject to the provisions of the National Aeronautics and Space Act of 1958, Public Law 85568 (72 Stat. 426; U.S.C. 2451), as amended.

It is the practice in certain types of message distribution systems to provide a plurality of load groups, where the loads in any group may use signals emanating from a common source. In order to commutate (directively route) messages made up of such signals to particular groups in accordance with the needs of the system, it is the practice to interpose gating means between the source and each of the various groups into which the loads have been divided, the gating means being of any suitable type which may be directively operated to allow passage of signals therethrough.

in the past, message distribution systems have used message formats wherein a certain fixed portion of each message is reserved to addressing information identifying one of the above-mentioned load groups which is to receive the data within the message. In the process of effecting such distribution, it has been the practice to assemble and express all message information, i.e. data and address portions, in a register for use when the entire message has been received. Traditionally, systems where information in each message is received from channel in serial order require that addressing operations (i.e., decoding of address information and of switching or gating devices which are effected in accordance with the results of the decoding) be withheld until an entire message has been received and registered. Since such addressing operations require a finite time interval, the effect is to delay delivery of message data to the loads. Distribution systems organized in the traditional fashion may include counting apparatus to obtain directive signals for operating the gating means. Such counting apparatus usually includes a counter-decoder in which the counter has an input and is operative in response to successive pulse signals applied thereto through a series of consecutive steps, With the counter-decoder combination effective at each counter step for generating a signal or signals on the decoder outputs which in turn selectively condition one or more of the gating means appropriate to the step to which the counter has been advanced. This counting apparatus may employ any type of equipment ranging from electro-mechanical, multiple bank stepping switches to ring counters and decoders employing electronic apparatus.

In a commutating system of the above mentioned type, it is the practice to combine into groups the counter decoder outputs used to control the various gating means and to use the signals appearing on the outputs in the various groups to selectively prepare pulsing apparatus for operation. In such a system, an independently operable pulse source may be used to provide an initial stepping signal to the counter decoder input in order to advance the counter by one step. Upon the completion of this initial step, the prepared pulsing apparatus can be repetitively operated to supply other pulses to the counter-decoder input. In this manner, the counter- Patented Apr. 12, 1966 decoder is advanced step by step in a so-called searching operation. Such a searching operation of the counter decoder combination usually is continued under the control of the pulsing apparatus until the counter-decoder has been advanced to a step at which the decoder is effective to enable the gating means individual to the load group to which it is desired to admit messages from the above mentioned source. The ability of the counter to avoid stopping on (i.e., to skip over) certain steps during such a searching operation has led to use of the phrase skipping counter to describe such a device. I

In the past, it has been the practice to effect such searching operation of a counter-decoder among groups where each group is restricted to include only consecutive counter steps (and, therefore, decoder outputs) owing to the relative complexity of the problem of switching the decoder output signals to the pulse apparatus. This in turn has made message distribution systems relatively inflexible in the matter of being able to control the admission of messages to loads appearing in particular groups (which may be regarded as being assigned arbitrarily with respect to the counter-decoder output numbering system). The problem is magnified when the further requirement is made that a particular load be assigned to more than one group of loads.

Accordingly, it is an object of the present invention to provide a new and improved message distributing system.

Another object of the invention is to provide a new and improved message distribution system in which addressing operations are carried out immediately upon the receipt of address information from a channel over which address and data information are received in the order named.

Another object of the present invention is to provide a new and improved skipping counter.

Another object of the present invention is to provide a new and improved skipping counter particularly adapted for use in a message distribution system.

Another object of the present invention is to provide a new and improved system for distributing messages from a common source to loads in various ones of a plurality of groups of such loads.

Another object of the present invention is to provide a new and improved message distribution system in which the address of the group of loads to which the message is to be switched is included as a part of the message received from a common source.

The present invention may be practiced in a system where there is provided a channel on which signals are delivered in serial order. These signals are divided into sets, each of which represents a message. The system also has a source to which the channel is coupled and which is operative in response to a first-occurring group of signals in each message for generating a set of signal which represent the identity of a class of load group or groups, and which thereafter produces from the remainder of the signals in each message a set of signals representing data for use within the appropriate load. Such signal may hereinafter be referred to as address bits or signals. The system also has a plurality of loads which are divided into groups of one or more loads each. Each such load is operative for using message signals produced by the incoming message register. In order to permit selective admission of messages to the various load groups, there is provided in the system a plurality of gating means interposed between the source and load groups. Each such gating means has a conditioning input and is responsive to a signal applied thereto for passing message signals from the source to the loads of the group with which the gating means is unique. The various load groups are further divided into the above-mentioned classes. There is provided address means having a plurality of outputs.

This address means is selectively operable for producing on those outputs signals which represent the identity of the above mentioned class of load groups to which a message is addressed.

In accordance with the principles of the present invention, there also is provided counting means, for instance a conventional counter-decoder combination, having an input and a plurality of outputs. The counting means is cyclicly operative in response to successive signals applied to its input for producing signals on successive ones of those outputs in accordance with the steps through which the counting means is advanced. The counting means outputs are divided into groups, each group corresponding and being unique to one of the aforementioned load group classes and the outputs in each such group being individual to one of the gating means of the load groups in that class. It is pointed out that the outputs included in each such group need not necessarily be consecutive with re spect to each other, nor exclusive to a particular class of groups. Means is provided for coupling each such group of outputs to the conditioning input of an appropriate one of the gating means, so that the latter can be selectively conditioned by stepping the counting means. Consequently, messages are admitted to a load group within a particular class when the counter has been advanced to any step in the group of such steps which produces a signal on the one of the decoder outputs coupled to the conditioning input assigned to the gating means of the particular l-oad group under consideration.

In order to control the advance of the counter, there is provided a pulse source which includes an output coupled to the counting means input and an input. The pulse source is operable in the presence of a signal on its input to produce a continuing series of pulses on the output. There also is provided comparing means having inputs coupled to the above mentioned address means and to the grouped counting means outputs. This comparing means also has an output coupled to the pulse source input and is operative in response to a difference between the selection signals generated by the address means and the group selection signals produced by the counting means for supplying a signal to the pulse source input. Consequently, the source supplies stepping pulses to the counting means input until there is no difference between the selection signals generated by the address means and the class identity of the selected load group by the signal generated at the counting means output.

The foregoing and other objects of the invention will be apparent from the following detailed description of the preferred embodiment of the invention as illustrated in the accompanying drawing.

Throughout the following description and in the accompanying drawing, certain conventions are employed which are familiar to those skilled in the art. Additional information concerning these conventions is as follows. In the drawing, an arrowhead is employed to indicate (1) a circuit connection, (2) energization with standard pulse or level, and (3) the direction of travel which also indicates the direction of control. The input and output lines of the block symbols are connected to the most convenient side of the block. An input connected to a corner of a first block symbol may be continued along an edge of that block to a point on an adjacent block symbol, in orderto illustrate the fact that the inputs of such bolcks are intended to be energized in parallel from a common source.

Bold-face character symbols appearing within a block symbol identify the common name of the circuit or element represented. For instance, FF indicates a flip-flop, G a gate which can be conditioned to pass pulses, & a logical AND circuit which produces a continuing output only so long as the levels on all inputs are up, or a logical OR circuit, and so on. Such flip-flops, gates, OR and AND circuits referred to in the following description may be of any suitable type, but preferably are the ones shown and described in chapter 2 and 4 in the book entitled: Digital Computer Components and Circuits, by

R. K. Richards, published in 1957 by D. Van Nostrand, Co., Inc., Princeton, New Jersey. The apparatus also employs a delay unit such as those generally described on pages 102 of the Richards reference and more particularly described on pages 286294.

For ease of understanding, it is assumed in the following description that all non-significant or 0 binary bits are represented by ground level potentials, and that up level and 1 bits are represented by signals which are positive with respect to ground. The latter signals may be referred to hereinafter as a level and pulses, respectively. I

Signal s0urce.Turning next to the detailed description of the invention, each of serially-occurring messages incoming over channel 2 to termination equipment shown generally in the drawing as 3 consists of serially-occurring bit signals. Termination equipment 3 is of any of a number of types well known to those skilled in the art, so that its description here is generalized, since the termination per se does not form a part of the present invention. The channel signals ofa message are converted at termination 3 into a series of binary pulses on output conductor 5, the presence of a pulse on conductor 5 representing a binary 1 and the absence of such a pulse representing a binary 0. In addition to producing pulses of the above described type on output conductor 5, termination 3 also produces timing pulse signals on conductor 4 in substantial coincidence with the time position of each binary 0 and 1 representation produced on conductor 5. Further, termination 3 produces on output conductor 6 a start-of-message signal which precedes but does not overlap the first conductor 4 pulse. The appearance of a signal on conductor 6 sets flip-flop 48 to its 1 state, is passed via OR circuit 61 to reset input 62 of binary, add-one type counter 63, the 0 inputs of flip-flops 24 and 25 within address register 23, and to reset input 35A to its 1 state and binary, add-one type counter 32. As a consequence, if flip-flop 48 LiS shifted, conditions gate 20, and both

counters

32 and 63 are set to register zero count at this time. Counter 32 may be of any suitable type, but preferably is similar to the one described on pages 177 and 178 of the Richards reference, While counter-decoder 63 includes a counter of the last-named type driving a decoder similar to decoder 33, which is defined in a later section of this description.

Serially appearing message bits on conductor 5 are applied to the first stage A of incoming (assembly) register 1. The timing pulses appearing on line 4 are passed through delay line 18 and applied to the shift input of register 1, so that the message bits appearing on line 5 are shifted into stages along the length of register 1. The format of messages received from line 2 is such that the first two bits of each message and first expressed in stages A and B of register 1 represent the address or identity of the class of the load group which is to receive the data bits contained in the remainder of the message.

The process by which the above-mentioned address bits are extracted is described next. The above-mentioned bit counter 63, having been reset to express zero count in the above described manner, thereafter receives via delay line 69 at its add-one input 64 each timing pulse produced on output conductor 4 of termination 3. Counter 63 is effective when it has been advanced to express a count of 2 to produce a signal on its output conductor 65. The signal on output conductor 65 is applied to an input of already-conditioned AND circuit 20, so that circuit 20 is eifective at this time to produce a signal on its output which conditions gates 19A and EB, and is applied via OR circuit 66 to the conditioning input of gate 67. The signal on counter output conductor 65 also is applied to the conditioning input of gate 68. In addition to being used to shift bits within the stages of register 1 and to increase the count expressed in counter 6.3, the next appearing (third) pulse produced on conductor 4 is passed by conditioned gate 68 to reset flip flop 48 to its 0 state and is passed via conditioned gate 67 to: a reset input 62 of Counter 63 and via conductor 49 to the start input of pulse source 59. The use to which the latter signal is put is to be explained in a section which follows.

Turning to the consideration of gates 19A and 19B, the signals produced on output lines 9A and 93 from register 1 upon the production of the above-mentioned third pulse on conductor 4 finds gates 19A and 19B conditioned in the above-described manner, so that signals appearing at 9A and 9B are passed via conductors 7 and 8 to the input of address register 23, where they are stored and used in a manner to be described.

The resetting of flip flop 48 to its 0 state and the consequent deconditioning of AND circuit 20 prevents the subsequent reading out of signals via gates 19A and 193 to register 23. It is pointed out at this time that the length of time delay introduced by line 69 between the production of a conductor 4 pulse and the admission of the pulse to input 64 of counter 63 is sufficient to allow counter 63 to be reset and to respond to register the above mentioned third conductor 4 pulse. For reasons that are to be apparent later, the delay so introduced also is sufficiently short to allow the last count to be expressed and to bring up the level on output line 70 of counter 63 during the time that output signal representing data are being read from register it on lines 9A-9M.

Upon the restoration of flip flop 48 to its 0 state and the resetting of counter 63 to zero, the assembly of the remaining message data bits in stages A-M of register ll proceeds in a manner similar to the one described above. Upon the registration of a message bit in last stage M of register 1, the count in counter 63 has been advanced to apply a dump signal to output conductor 70. The latter marks the end of the message and is passed via OR circuit 66 to condition gate 67 and is further used to condition AND circuits associated with

load groups

10 and 11 in a manner to be described. As the result of reconditioning gate 67, counter 63 is reset to zero and the above described signal is produced on conductor 49 at this time. Thus, in the event no start-of-message signal is produced on conductor 6 after register 1 has been filled with data bits, each refilling of register 1 is marked by the occurrence of another signal on output conductor 7 L0ads.-In the preferred embodiment of the present invention, each set of data signals appearing on conductors 9 is to be distributed to one or more groups of loads. Such groups of loads, shown collectively in the drawing as Iii-ill, may be of any type suitable for using parallel input signals such as those delivered over conductorsii. The loads of each group have multiple inputs connected to input conductors (collectively indicated in the drawing as 12 and 13).

In order to control the admission of signals from conductors 9 to the various load inputs, groups of gates indicated in the drawing as 14-15 are interposed and provide coupling between conductors 9 and input conductors 12-13, respectively, of each load group. The conditioning inputs of gate groups 14-15 are connected to control conductors 16-17, respectively. Consequently, the application of a signal to control

conductor

16 or 17 in coincidence with message signals appearing on conductors 9 directs the appropriate gate set to admit such message signals to a particular load group. The manner in which conditioning signals are applied to conductors 16-17 is described presently.

Class register.-The above mentioned class register 23 includes flip-flops 24 and 25 into which are written the class indicating bits transmitted from stages A and B of register 1. Assuming that the flip-flops have been reset to their zero states prior to the receipt of signals from

register

1, 1 signals subsequently delivered over conductors 7 and 8 are applied to the 1 inputs of the flip-flops and shift the flip-fiops to their 1 states. Consequently, flip-flops 24 and 25 produce on their outputs 0 and 1 signals which represent the identity of a load group class 6 to which message bits from register 1 are to be admitted after the address bits firom register 1 have been received at register 23.

The output signals from flipflops 24 and 25 are applied to the input of a decoder 27. Decoder 27 may be of any of a number of types recognized in the art, but preferably is of the type shown and described on pages 56 through 59 of the Richards reference. Decoder 27 is efiective in response to the receipt of each unique combination of signals from the outputs of flip-flops 24- and 25 for producing an up level on a particular one of its output conductors 28-29. It is pointed out that the identity of decoder output on which a signal is produced expresses the class of load groups 16-11 of the system to which signals appearing on conductors 9 may be admitted.

C0urzter-Dec0der.The apparatus used to provide conditioning signals to the above-described gate sets 14-15 includes counter 32 and its companion decoder 33. While decoder 33 may be of any suitable type, preferably it is similar to the above mentioned decoder 28. The various outputs of counter 32 collectively indicated in the drawing as 34 are coupled to the inputs of decoder 33. Counter 32 is operative in response to successive pulses supplied to its input 35 through cycles of successive steps and is effective upon its advance to each step for producing significant signals on a unique combination of its output conductors 34. Decoder 33 is effective in response to the receipt of signals on each unique combination of conductors 34 for producing a signal on a particular one of its output conductors 36, the number of output conductors 36 being equal to the number of steps in a cycle of such steps through which counter 32 may be advanced.

Certain of the output conductors 36 of decoder 33 are divided into a number of groups 37-33, the number of such groups being equal to the number of the above described output or" register 23. The conductors included in any such output group need not be consecutive with respect to each other, i.e., energized in order, by decoder 33, nor exclusive to a particular conductor group. Each such output conductor group is unique to a particular class of load groups. For instance, output conductor group 37 may correspond to the class of load groups that includes group it} and to register output conductor 29.

Each output conductor 36 which is included in one of groups 37-38 is coupled to an input of a particular one of AND circuits 55, so that the production of a signal on one of output conductors 36 included in a particular group, such as 37, also is effective to prepare the AND circuit of a particular load group within the appropriate class of loads. It is pointed out that the AND circuits 55 are prepared for operation in parallel at the time the above mentioned signal appears on conductor 70, so that a signal appearing on one of output conductors 36 are etiectively passed by the prepared one of circuits 55 to one of the above-mentioned gating means. The manner in which signals produced by circuits 55 are used is described in greater detail in paragraphs which follow. Assuming for the moment that one or more AND circuits 55 produce output signals, such signals are passed to the appropriate conductors 16-17 to the conditioning inputs of gating means 14-15. In the example chosen for illustration here, the signal is produced on conductor 16 and is effective to condition gating means 14.

Comparison 0perati0n.ln the presently contemplated system, counter-decoder combination 32-33 is to search (on demand) for a particular decoder output group which coincides with the class of load groups expressed by the output of register 23. More specifically, the counterdecoder to be advanced to a step at which the counterdecoder is effective to produce a signal on one of its outputs included in the group corresponding to the address expressed by signals on output conductors 28-29 of register 23.

To this end, comparing means 40 is provided with AND circuits 44-45, each of which has first and second inputs. The first input of each such AND circuit is connected to one of the above described out conductors 2-829, while the second input of each AND circuit is connected to one of conductors 30-31. Each conductor in the set 3tl31 is fed signals from the output of an appropriate one of inverters 42. Each of inverters 42 in turn is provided .at its input with signal from one of the groups 3738 of output conductors from decoder 33 by an appropriate one of OR circuits 41. A signal appearing on the output of AND circuits 44-45 is passed through OR circuit 46 to output conductor 47.

With this arrangement of elements, the receipt of a signal on one of output conductors 28-29 which does not correspond to the group containing the one of output conductors 36 on which decoder 33 currently is producing a signal causes coincident signals on the first and second inputs of one of AND circuits 4445. The latter AND circuit in turn produces a signal which is applied to output conductor 47 and which is used in a manner to be described below. For instance, in the case where a signal on conductor 28 identifies a class of load groups different from the load group 16) which is currently prepared to receive data signals by virtue of a signal appearing on conductor 36 which is also included in group -37, the absence of a signal on the conductors in all other groups such as 38 is inverted by appropriate ones of inverters 42. The resulting signal produced by these inverters 42 are applied to the second inputs of AND circuits including circuit 44. With its first and second inputs energized, circuit 44 produces a signal which is passed through OR circuit 46 to output conductor 47. In the opposite case, where the address signal produced by register 23 agrees with the identity of the group of output conductors 36 on which a signal currently is being produced, comparing means 40 withholds a signal from the output conductor 47. For instance, when a signal is being produced on a conductor 36 within group 38 and a signal also is being produced on conductor 28, the resultant inversion of the signal at the appropriate one of inverters 42 withholds the signal from the above-described second input of AND circuit 44. Consequently, AND circuit 44 withholds a signal from its output. Since register 23 at this time does not supply signals to the first inputs of AND circuits other than 44, none of the latter circuits is effective to produce an output signal. Therefore, none of the AND circuits in comparing means 40 is effective in the presently considered case to produce an output signal, with the result that no signal appears on conductor 47.

While certain of decoder outputs conductors 3d combined in the above-described groups 37-33 correspond to various register 23 outputs, the remainder of outputs 36 are combined into still another group 54. This group 54 includes output 36 conductors which correspond to no register load group class expressed by register 23. When a conductor 36 within group 54 is energized, it is desired to cause comparing means 40 to produce a signal on output conductor 47 no matter which of output conductors 27- 28 of register 23 is energized. Accordingly, each of the conductors 36 in group 54 is connected to an input of OR circuit 46.

Pulse sm'ce.Pulse source 50 has a triggering input, a conditioning input and an output which are connected to conductor 49, conductor 47 and input 35 of counter 32, respectively. Source to a trigger signal appearing on conductor 49 to advance counter 32 by one step and also is efiective in response to the appearance of a signal on conductor 47 to produce thereafter a series of pulses for application to input 35 of counter 32 so long as the signal is maintained on conductor 47. From the above description, it is to be seen that counter-decoder 3Z33 is caused to search (i.e., step) under the control of pulses supplied by source 5% until the load group class expressed in register 23 matches the identity of the gating means 144.5 selected for use by counter-decoder 32-33.

To the end of operating pulse source 50, the signal appearing for the above-described reasons on conductor 49 and applied to the signal input of source St) is passed through OR circuit 51 to input 35 of counter 32 and to the input of delay line 52. Consequently, counter 32 is advanced at such a time by one step. Should counterdecoder 32-33 be effective in combination with register 23 at this time to cause comparing means 40 to produce a signal on its output conductor 47, gate 53, the conditioning output of which constitutes the above-mentioned conditioning input of source 59, becomes enabled to reshape and pass the above-mentioned pulse as it emerges from delay line 52. A pulse passed by gate 53 is reapplied via OR circuit 51 to the input 3d of counter 32 and to the input of delay line 52. In this manner, source 50 continues to regenerate pulses and counter 32 is stepped until the load group selected by counter-decoder 3233 is in agreement with the load group class expressed by registers 1 and 23. When the latter event occurs, comparing means 40 removes the signal from its output conductor 47. As a consequence, gate 53 within source 50 is deconditioned and thereupon blocks the above-described path for regenerating signals. For this reason, source 50 stops producing output pulses, so that the searching operation of counter 35 is stopped at this time. It is pointed out that pulses are produced by source 56 at a rate that is substantially faster than the rate at which signals appear on the above-mentioned conductor 4. The ratio of these rates is chosen to allow source 56 to step counter 32 through at least one complete cycle of steps in the time period between adjacent conductor 4 pulses.

Admitting a message to a load gr0up.it is next assumed that a message is incoming to register 1. From the above description, it is to be seen that the load group class bits set into register 1 stages A and B are admitted to set flip-flops within register 23, while the data bits thereafter expressed in stages A-M are conveyed via conductors 9 to the inputs of gating means 1415. Also from the above description, it is to be seen that the appearance of a pulse on conductor 49 during the time data bits are being assembled in register 1 advances counterdecoder 32-33 by one step and that comparing means 4% thereafter is effective to cause pulse source 50 to continue supplying counter 35 with pulses until the load group class identity expressed in stages A and B of register 1 agrees with or matches the group of output counters containing the energized decoder 36 output conductor if such agreement does not exist after the signal first appears on conductor 6. This advance of the counter-decoder takes place during the time stages A-M of register 1 are being filled with data bits.

When agreement has been achieved and a signal is produced on conductor 7t? (which takes place only after all data bits have been received), the appropriate one or more of AND circuits 55 passes a signal from the signalbearing one of conductors 36 to condition the appropriate one of gating means 14 and 15. In this manner, gating means 14 and 15 are made operative on a selective basis to pass the message data bit signals transmitted from register 1 as the latter signals appear on lines 9 into the ones of the load groups of the addressed class.

While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:

1. In a distribution system having a source for producing a sequence of message signals,

a plurality of load groups, each of said loads being operative to use signals produced by said source,

and a plurality of gating means interposed between said source and said load groups,

where each of said gating means has a conditioning input and is operative in response to the application 9 of a signal thereto for passing signals from said source to the one of said load groups individual thereto,

the combination comprising:

counting means having an input and a plurality of outputs,

said counting means being operative through cycles of steps in response to signals applied to said input thereof and effective for producing signals on said outputs in accordance with the steps to which said counting means is advanced,

said counting means outputs being divided into groups,

each group corresponding and being unique to a particular class of said load groups and said gating means individual thereto,

means for coupling said counting means outputs within each of said groups to said conditioning input of one of said gating means,

a pulse source having an output coupled to said counting means input and an input, said pulse source being operable in response to a signal applied to the input thereof for producing a continuing series of signals on said pulsesource output,

and means having inputs coupled to said groups of counting means outputs and an output coupled to said pulse source input eifective in response to the receipt of signals from any of said outputs in selected ones of groups of counting means outputs for applying a signal to said pulse source input, whereby said counting means is advanced to a step at which said gating means unique to a selected one load groups are conditioned to pass message signals emanating from said source.

2. In a system for distributing message signals produced by a source to groups of loads which have been divided into classes,

Where a plurality of gating means are interposed between said source and said load groups, each of said gating means has a conditioning input and is operative in response to the application of a signal thereto for passing message signals from said source to the one of said load groups individual thereto,

and where said system also includes class identifying means selectively operable for producing on outputs thereof signals representing the identities of the class of said load groups to which messages are to be admitted;

the combination comprising:

counting means having an input and a plurality of outputs,

said counting means being operative in response to signals applied to said input thereof through cycles of steps and effective for producing signals on said outputs which identify the steps to which said counting means is advanced,

said counting means outputs being divided into groups,

each of said output groups corresponding and being unique to said load groups included in a particular class, with each of said outputs in such a one of said groups being unique to one of said load groups and the one of said gating means corresponding thereto, means for coupling said counting means outputs within each of said output groups to said conditioning input of the corresponding one of said gating means,

a pulse source having an output coupled to said counting means input,

said pulse source also having an input and being operable in response to the receipt of a signal thereat for producing a continuing series of signals on said pulse source output,

and comparing means having inputs coupled to said class identifying means outputs and to said groups of counting means outputs and having an output coupled to said pulse source input,

said comparing means being effective in response to the receipt of signals from said address means identifying one of said load groups different from the one of said groups of counting means outputs on which a signal currently is being produced for applying a signal to said pulse source input.

3. In a system for distributing message signals pro duced by a source to groups of loads which have been divided into classes,

where a plurality of gating means are interposed be tween said source and said load groups,

each of said gating means has a conditioning input and is operative in response to the application of a signal thereto for passing message signals from said source to the one of said load groups individual thereto,

and where said system also includes class identifying means selectively operable for producing on outputs thereof signals representing the identities of the classes of said load groups to which messages are to be admitted;

the combination comprising:

counting means having an input and a plurality of outputs,

certain of said countin means outputs being divided into groups, each of said output groups corresponding and being unique to a particular class of said load groups and with each of said outputs in such a one of said groups being unique to one of said load groups and the one of said gating means corresponding thereto,

means for coupling said counting means outputs included within each of said output groups to said conditioning input of the corresponing one of said gating means,

a pulse source having an output coupled to said counting means input,

comparing means having inputs coupled to said address means outputs and to said groups of counting means outputs and having an output coupled to said pulse source input,

said comparing means being effective in response to the receipt of signals from said class means identifying a class of said load groups dilferent from the one of said groups of counting means outputs on which a signal currently is being produced for applying a signal to said pulse source input,

and means for coupling said counting means outputs not included in any of said groups to said comparing means ontput.

4. In a system for distributing message signals produced by a source to load groups which have been divided into classes,

where a plurality of gating means are interposed between said source and said load groups,

said system also includes class means selectively operable for producing on outputs thereof signals representing the identities of those of said load group classes to which messages are to be admitted,

and where said source is operative to produce a signal marking the start of each set of signals which constitute a message,

the combination comprising:

counting means having an input and a plurality of outputs,

said counting means outputs being divided into groups, each of said output groups corresponding and being unique to a particular class of said load groups and with each of said outputs in such a one of said groups being unique to one of said load groups and the one of said gating means corresponding thereto,

means for coupling said counting means outputs within each of said groups to said conditioning input of the corresponding one of said gating means,

a pulse source having an output coupled to said countting means input,

said pulse source also having first and second inputs and being operable in response to a trigger signal applied to said first input and to a conditioning signal applied to said second input thereof for producing a continuing series of signals on said pulse source output for so long as said second input signal continues,

comparing means having inputs coupled to said address means outputs and to said groups of counting means outputs and having an output coupled to said pulses source second input,

said comparing means being effective in response to the receipt of signals from said address means which identify the one of said load group classes different from the class of said group of counting means outputs on which a signal currently is being produced for applying a signal to said pulse source second input,

and means responsive to the receipt of a start of message signal from said message source for applying a signal to said pulse source first input,

whereby said counting means selects a load of an identified one of said classes during the time signals of a message are being received.

5. In a distribution system employing a skipping counter,

counting means havingan input and'outputs divided into a plurality of groups, said counting means being operative through cycles of successive steps in response to successive signals applied to said input for producing signals on the ones of said outputs representing the steps to which said counting means is advanced,

means having a plurality of outputs operative for producing: thereon signals identifying said counting means output conductor groups,

comparing means having first and second input sets connected to said counting means outputs and to said identifying means outputs, respectively,

said comparing means also having an output and being operative for producing a signal thereon in response to a signal applied to said first input set identifying one of said counitng means output groups different from the one of said groups which includes the signal-bearing one of said counting means outputs,

a pulse source having an input coupled to said comparingmeans output and an output coupled to said counting means input,

said pulse source being operable in response to the receipt of a signal on said input thereof for producing a continuing series of signals on said pulsesource output.

6. The combination set forth in claim 5 wherein,

said pulse source includes a gate circuit having a conditioning input coupled to said source as well as a sampling input and an output,

said pulse source also includes means for coupling said gate output to said source output and a delay line for coupling said source output to said gate circuit sampling input,

and wherein there additionally is included means for applying a single pulse to said delay line and to said pulse source output.

No references cited.

ROBERT C. BAILEY, Primary Examiner.

Claims

1. IN A DISTRIBUTION SYSTEM HAVING A SOURCE FOR PRODUCING A SEQUENCE OF MESSAGE SIGNALS, A PLURALITY OF LOAD GROUPS, EACH OF SAID LOADS BEING OPERATIVE TO USE SIGNALS PRODUCED BY SAID SOURCE, AND A PLURALITY OF GATING MEANS INTERPOSED BETWEEN SAID SOURCE AND SAID LOAD GROUPS, WHERE EACH OF SAID GATING MEANS HAS A CONDITIONING INPUT AND IS OPERATIVE IN RESPONSE TO THE APPLICATION OF A SIGNAL THERETO FOR PASSING SIGNALS FROM SAID SOURCE TO THE ONE OF SAID LOAD GROUPS INDIVIDUAL THERETO, THE COMBINATION COMPRISING: COUNTING MEANS HAVING AN INPUT AND A PLURALITY OF OUTPUTS, SAID COUNTING MEANS BEING OPERATIVE THROUGH CYCLES OF STEPS IN RESPONSE TO SIGNALS APPLIED TO SAID INPUT THEREOF AND EFFECTIVE FOR PRODUCING SIGNALS ON SAID OUTPUTS IN ACCORDANCE WITH THE STEPS TO WHICH SAID COUNTING MEANS IS ADVANCED, SAID COUNTING MEANS OUTPUTS BEING DIVIDED INTO GROUPS, EACH GROUP CORRESPONDING AND BEING UNIQUE TO A PARTICULAR CLASS OF SAID LOAD GROUPS AND SAID GATING MEANS INDIVIDUAL THERETO, MEANSA FOR COUPLING SAID COUNTING MEANS OUTPUTS WITHIN EACH OF SAID GROUPS TO SAID CONDITIONING INPUT OF ONE OF SAID GATING MEANS, A PULSE SOURCE HAVING AN OUTPUT COUPLED TO SAID COUNTING MEANS INPUT AND AN INPUT, SAID PULSE SOURCE BEING OPERABLE IN RESPONSE TO A SIGNAL APPLIED TO THE INPUT THEREOF FOR PRODUCING A CON-