JPS635925B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a ladder resistance type DA conversion circuit using a monolithic integrated circuit, and in particular to an element arrangement for realizing a highly accurate ladder resistance type DA conversion circuit. This is related to the improvement of

[Conventional technology]

As shown in Figure 1, there is a ladder resistor network R _O , a group of transistors T _R whose bases are commonly connected, and a group of resistors connected to the emitter of each transistor.
R _EO , and the above ladder resistance network R _O and transistor group
In the DA converter circuit, which is composed of a switch group S _O (weight switching circuit group) provided between T _R and T R, its resolution depends on the resistance accuracy of the ladder resistor network R _O and the resistance _R This is due to the relative output current accuracy of a constant current circuit group consisting of a group of connected transistors T _R with a common base, so conventionally methods such as resistor trimming have been used to obtain high resolution.

[Summary of the invention]

In this invention, the R-
Connect the 2R ladder resistor network with resistor R in series to create a resistor.
By obtaining 2R, all resistors R are configured as a unit, or by connecting resistors 2R in parallel to obtain resistance R, all resistors 2R are configured as a unit, and by each unit resistor that configures this ladder resistance network. The elements constituting each group of the ladder resistance group, the transistor group, and the resistor group (hereinafter referred to as the emitter resistance group) each consisting of a resistor connected to the emitter of each transistor in the transistor group are in charge of the most significant bit. By placing components in the center and sequentially distributing them to the left and right of the central component in order from those in charge of higher-order bits, the relative consistency between each element is utilized. The object of the present invention is to provide a ladder resistance type DA converter circuit using a monolithic integrated circuit that can easily and inexpensively obtain high resolution using a completely different method.

[Embodiments of the invention]

Generally speaking, in a monolithic integrated circuit, adjacent elements having the same crystal direction have similar characteristics, and the larger the distance between the elements, the greater the difference in their characteristics. Therefore, when building a ladder resistance type DA converter circuit as shown in FIG. 1 using a monolithic integrated circuit, the arrangement of its constituent elements greatly affects the accuracy of the DA conversion output. Here, by taking the 5-bit ladder resistance type DA converter circuit shown in FIG. 2 as an example, the optimum arrangement of its constituent elements will be specifically explained.

In the figure, T ₁ to _{T 5} are NPN transistors provided corresponding to each bit of input digital data, with transistor T ₁ in charge of the most significant bit (MSB), and hereinafter referred to as transistors.
T ₂ to _{T 5} are sequentially responsible for the lower bits, and transistor T ₅ is responsible for the least significant bit (LSB). Furthermore, _T6 is a transistor that forms a current mirror together with the transistors _T1 to _T5 , and these transistors _T1 to _T6 form a transistor group _TR . R _E1 to R _E6 are emitter resistors connected to each emitter of the transistors T ₁ to _{T 6} and forming an emitter resistor group R _{EO ;}
R ₃ , R ₅ , R ₇ , R ₉ are bit resistors connected to the collectors of the transistors T ₁ to T ₅ , and R ₂ , R ₄ , R ₆ ,
_R8 is the above transistors _T1 to _T5 and the bit resistor _R1 ,
This is an inter-bit resistance that connects each connection point with R ₃ , R ₅ , R ₇ , and R ₉ , and the above-mentioned bit resistances R ₁ ,
R ₃ , R ₅ , R ₇ , R ₉ and inter-bit resistance R ₂ , R ₄ , R ₆ ,
R ₈ and the ladder resistance network, i.e. the ladder resistance group R _O
is configured.

Note that S ₁ to _{S 5} are switches that open and close according to input digital data, and these switches S ₁ to _{S 5} constitute a weight switching circuit group _SO . Further, Iref is a constant current source, and Vref is a reference voltage source.

In this way, first of all, regarding the ladder resistance group R _O ,
As shown in Figure 3a and b, the resistors 2R (R ₁ , R ₃ ,
R ₅ , R ₇ ) are obtained by connecting resistors R in series, and therefore the ladder resistor group R _O is all constructed using resistors R as a unit. Also, this ladder resistance group R _O
In this example, resistors R ₁ to _{R 9} formed by P ⁺ diffusion 1 with a resistance value R are arranged as close as possible and in parallel, and N ⁺ is placed at both ends of these resistors R ₁ to _{R 9} in a direction perpendicular to the direction of the resistors. Diffusion 2 is inserted and the potential of this resistor island is taken there. By doing this, a resistor group R ₁ to _{R 9} with highly matched resistance values R is formed, and the bit resistor responsible for the most significant bit (MSB)
For R ₁ and the bit-to-bit resistance R ₂ , the bit-to-bit resistance is
Bit resistors R ₁ are arranged on the left and right of R ₂ , and resistors R 3 , R ₃ ,
R ₄ , R ₅ , R ₆ , R ₇ , R ₈ , and R ₉ are arranged in this order, alternately on the left and right, and then connected with Al wiring 3 as shown in the figure. Configure a ladder resistance group. Most significant bit (MSB) like this
By arranging the resistors _R2 , which is in charge of the bits, as the center, and distributing the resistors to the left and right in order from the resistors in charge of higher-order bits, the D-A conversion output caused by variations between each element and thermal gradients within the chip can be reduced. The error can be minimized.

In addition, in FIG. 2, transistors T ₁ , T ₂ , T ₃ , T ₄ , T ₅ , T ₆ constituting the constant current source circuit group and emitter resistance groups R _E1 , R _E2 , connected to the emitters of the transistors are shown. For R _E3 , R _E4 , R _E5 , and R _E6 , the most significant bit (MSB) is also
The transistor T ₁ in charge of the upper bit and the resistor R _E1 connected to the emitter of the transistor are arranged in the center, and the transistors T ₂ , T ₃ , T ₄ , T ₅ , The emitter resistors R _E2 , R _E3 , R _E4 , and R _E5 are distributed alternately to the left and right, respectively, and the transistor T ₁ and resistor R _E1 are
They are arranged parallel to and as close to each other as possible, and connected with Al wiring 3 as shown in the figure. By configuring the transistor group and emitter resistor group with such an element arrangement, as in the case of the ladder resistor group, variations between each element and the influence of thermal gradients within the chip can be minimized. Can be done.

In the above embodiment, the resistor ladder network was constructed using each resistor R as a unit by connecting resistors R in series to obtain resistor 2R. By obtaining, all resistors 2R may be configured as a unit,
Effects similar to those of the above embodiment can be obtained.

Note that in the above embodiment, the ladder resistance type DA converter circuit shown in FIG. is not limited to the above embodiments.

〔Effect of the invention〕

As described above, according to the present invention, the R-2R ladder resistance network of the ladder resistance type D-A converter circuit can be configured entirely using the resistance R as a unit by connecting the resistances R in series to obtain the resistance 2R. , or resistance
By connecting 2R in parallel to obtain a resistor R, all resistors 2R are configured as a unit, and the constituent elements of each group of ladder resistance groups, transistor groups, and emitter resistance groups are made up of each unit resistance that makes up this ladder resistance network. The components in charge of the most significant bit are arranged in the center, and the components in charge of the higher order bits are distributed alternately to the left and right of the central component, allowing for monolithic integration of high-precision D-A converters. Because it can be easily manufactured with circuits and can be easily combined with other circuits, D-A
This has the effect of making it possible to integrate various circuits with built-in conversion circuits into one-chip monolithic circuits.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a typical ladder resistance type DA converter using NPN transistors, and Fig. 2 is a circuit diagram of a ladder resistance type DA converter circuit in a monolithic integrated circuit according to an embodiment of the present invention. , 3rd
Figures a and b are an element layout diagram of a ladder resistor group and its sectional view taken along the line A-A' when the circuit in Figure 2 is implemented as a monolithic integrated circuit, and Figure 4 is a monolithic integrated circuit in which the circuit in Figure 2 is implemented as a monolithic integrated circuit. FIG. 2 is an element layout diagram of a transistor group and an emitter resistor group when realized as a transistor. T _R ...Transistor group, S _O ...Weight switching circuit group, R ₁ , R ₃ , R ₅ , R ₇ , R ₉ ... Bit resistor, R ₂ ,
R ₄ , R ₆ , R ₈ ... Resistance between bits, R _O ... Ladder resistance group, R _EO ... Emitter resistance group. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A ladder resistance type D-A conversion circuit using a monolithic integrated circuit consisting of an R-2R ladder resistance network, a constant current source group, and a weight switching circuit group. By doing this to obtain a resistor 2R, it can be constructed using a resistor R as a unit, or by connecting resistors 2R in parallel to obtain a resistor R.
As a result, in each element group, all of which are composed of the resistor 2R as a unit, the transistor group and the resistor group that make up the constant current source group, and the resistor group of each unit resistor that makes up the above R-2R ladder resistance network. , the element in charge of the most significant bit is arranged in the center, and the elements in charge of the lower bits have the same element shape as the above-mentioned center element, and the element directions are aligned, and the elements in charge of the upper bit are placed on the left and right of it. A ladder resistance type D-A converter circuit using a monolithic integrated circuit, characterized in that the elements are arranged in an alternating manner, and the element in charge of the least significant bit is arranged at the outermost side.