JPS6359129A - Route identification system - Google Patents

Abstract

PURPOSE:To improve the operating efficiency of an additional bit of a transmission line by scrambling a data signal coded by a coding circuit for FORWARD ERROR CORRECTION (FEC) by means of a scramble pattern different from every transmission route. CONSTITUTION:An FEC coding circuit (FECENC) 12 operates 70 X 6 bits arranged in time slots 1-70 to generate redundancy bits (12 bits) and the redundancy bits are arranged in the time slots 71, 72. Thus, the FECENC 12 codes the information bits (70 x 6 bits) into the clock code of 72 X 6 bits. One word is accommodated in one frame constituted by a mltiplexing circuit (MUX) 11. A pattern generator (PG) 13 generates a scramble pattern synchronously with the word frame of a data signal A1. An exclusive OR circuit (EX-OR) 14 scrambles the data signal A1 by the output of the PG 13 and sends the result to a transmission route SYS-1. Six columns of data signals subjected to scrambling are sent to the receiving end while radio carrier is subjected to 64-value orthogonal amplitude modulation in the route SYS-1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a route identification method, and particularly to a route identification method in a digital wireless communication system using FmC.

[Conventional technology]

In digital wireless communication systems, additional bits for signal section monitoring are inserted into the data signal to be transmitted,
Since it is necessary to scramble the data signal to ensure randomness of symbols in the transmission interval, the data signal is framed, and the additional bits usually include seven frame synchronization bits.

However, FEC (Forward
Error Correction),
Since the data signal is divided into blocks by encoding, one word of the code word is used as one of the above-mentioned frames. In this way, frame synchronization can be achieved at the receiving end by confirming that meaningful decoding has been performed (no code errors are detected except for a small code error corresponding to a transmission path code error). No special frame sync bits required.

The effectiveness of using the additional bits of the transmission path is improved.

Among the additional bits, the VC contains 1 (usually 1) i & another bit.

In wireless communication systems, the receiving input electric field fluctuates significantly due to fading, so there is a wide tolerance for fluctuations in the receiving input electric field, and even if the regular received signal is cut off, interference signals from other routes can be received and There is a possibility that you will not notice it. In particular, in a two-round network, the intermediate relay station receives several channels of signals from both the upstream and downstream routes on the same cycle.
This fear is strong. To address this problem, conventional digital wireless communication systems insert a route identification unique to each route into the data signal.

This route identification bit was detected at the receiving end to confirm that a legitimate received signal was being received.

[Problem that the invention seeks to solve]

As explained above, the conventional route identification method.

Since additional bits for route identification are required, there is a drawback that the efficiency in using the additional bits of the transmission path is low.

SUMMARY OF THE INVENTION An object of the present invention is to provide a route identification method that eliminates the need for additional bits for route identification by solving the above-mentioned drawbacks when FEC is used.

[Means for Solving the Problems] The route identification method of the present invention includes an encoding circuit that encodes each of a plurality of data signals transmitted through different transmission routes into block codes.

and a scrambling circuit that scrambles the outputs of these encoding circuits with different scrambling patterns for each of the transmission routes and outputs the scrambled signals to the transmission routes.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments.

FIG. 1 is a block diagram showing an embodiment of the route identification method of the present invention.

The embodiment shown in FIG. 1 is for the case where there are transmission routes SYS-1 to SYS-5YS-k for transmitting data signals 81 to Sk, respectively, and data signals 81 to Sk and additional bits D1 to Dk. A multiplex circuit (hereinafter referred to as MUX) that inputs
FE that manually outputs 11~kl and MUXll~kl
C encoding circuit (hereinafter referred to as FEINC) 12 to 2, pattern generator (hereinafter referred to as PG) 13 to 3, and F
gCENCl 2~ transmits the exclusive OR of the output of 2 and PGI 3~ the output of 3) SYS-1~5YS-
Exclusive OR circuit (hereinafter referred to as gX-OR) 14 to 4, PO43-5, and transmission route 5M5.
EX-OR16 to 6 and F3X-OR which manually input the received output from -1 to 5YS-k and the output of 5 to PO43-
FEC decoding circuit (hereinafter referred to as F
F3CDgc) 17 to 7 and FECDECl
Separation circuit (hereinafter referred to as I) EM that inputs the decoded output of 7 to 7~
(referred to as UX) 18 to 8.

FIG. 2 shows FECENCl in the embodiment shown in FIG.
2 is an explanatory diagram showing the frame structure of the data signal A1 which is the output of No. 2. FIG.

The operation of the embodiment shown in FIG. 1 will be explained below with reference to FIG.

Each of the data signals 81-8 has six columns.

Each of them is composed of data signals that are binary code strings.

MLIXllri, 72/69 each column of Boolean m No. S1
As shown in FIG. 2, the bits of each column of the data signal S1 are placed in the 1st to 69th time slots after speed conversion, and the additional bit D1 is inserted in the 70th time slot. However, the 71st and 72nd time slots are left empty to form a 72x6-bit frame. Additional bit Died.

As illustrated in Figure 2, ? - and schannel bit S
Includes C, Parityche, Kvivt P1 and P2, etc.

F'gCENC12 calculates 70x6 bits placed in time slots 1 to 70 @ to generate 12-bit redundant bits, and uses these redundant bits and bits in time slots 71 and 72. Place it in

this! 5K, FECENCl 2rm, and encodes the 70 x 6 bit information bits into a 72 x 6 bit production code. One word is accommodated in one frame composed of MUXII.

PG13ri generates a scramble pattern of a synchronized word frame K of data signal A1. E
The X-ORI 4 scrambles the data signal A1 with the output of the PGI 3 and sends it to the transmission route SMS-1.

The scrambled six-column data signal rt is transmitted to the receiving end through a radio carrier wave in 64-value orthogonal amplitude mode on a transmission route 8Y8-1.

Data signals 82 to Sk are similarly framed.

SMS-encoded and scrambled before transmission
2 to 8Y8-. However, 3 to PO43-
Scramble patterns of different patterns (a pattern with t and an L, or a pattern with the phase of one pattern shifted) are generated for each of rj and rj.

Generates the same scramble pattern as that generated by PGI 5rt and PGI 3. This pattern r
In the word frame of the decoding operation of lt%FBCDIC17 (including with pattern phase l) F E CFJNC12 and P
1) Synchronized exactly the same as with GI 3. Therefore, if FECDgCl7 is word synchronized correctly, EX-OR16 descrambles the six columns of data signals manually input from transmission route 5YS-1, restores them to data signal A1, and outputs it.

FECDgCl 7 calculates each bit (information bit) of time slots 1 to 70 of the word frame of data signal A1 input by one person, and outputs the calculation result and each bit (redundant bit) of time slot 71 and 72. A transmission code error is detected by comparing the information bits, and the transmission line code error in the information bits is corrected and output as a decoded output.

Using the word synchronization of DEMtJX18ri and FECDgCl7, separate and output the additional bit D1 from the decoded output,
It also performs 69/72 speed conversion to restore and output the data signal 81.

If the word synchronization of FEcngcl 7 is correct.

Not only cannot decryption be performed, but also descrambling cannot be performed. In this state, FBCDget 7 detects an abnormally large number of code errors that do not correspond to the transmission path code vA. At this time, FECDgCl7 shifts the word frame by one time slot to detect a code error. PGI 5
The pattern output by is also shifted by one time slot. If you repeat this operation up to 72 times, word synchronization will be achieved, and at the same time, descrambling will also be normal and FgCDEC17
The frequency of code errors detected by the system also becomes normal.

When data signals passing through the transmission routes 8M5-2 to 5YS- are manually input to EX-OR 16 as interference signals, they are scrambled with a scramble pattern different from the scramble pattern generated by these interference signals rtP'G13.

The signal is not descrambled by the PGI5/EX-OR16 and becomes a meaningless signal, and the FgCDESCt7 continues to detect an abnormally large number of code errors even after repeating the word synchronization operation as described above 72 times. At this time, FECDgC1
7rj transmission route 5YS-1 is not received, and thereby the υ route can be identified.

The data signals transmitted over the transmission routes 5M5-2 to 5YS- are also restored and output in the same manner as the transmission route 5Y8-1, and the route is identified.

If PGI 3~3 each produce completely different patterns from each other (not just out of pattern phase), PO43~3 need not be synchronized to the word frame of FECENC12~2. In this case 1, for example, the word synchronization operation of FhiCDBCl 7 is repeated up to 72 times while the pattern phase of PGls (which generates the same pattern as PGI 3) is fixed. If word synchronization cannot be achieved through this repetition, the pattern phase of PGI 5 is shifted by one time slot and the word synchronization operation is repeated up to 72 times. By sequentially shifting the pattern phase of PGI 5 in this way, word synchronization can be achieved while the entire pattern length is shifted. If word synchronization cannot be achieved even if the entire pattern length is shifted, it means that the data signal via SMS-1 is not being received, and the route can be identified.

〔Effect of the invention〕

As explained in detail above, the route identification method of the present invention is
By scrambling the data signal encoded by the FEC encoding circuit with a different scramble pattern for each transmission route, it is possible to separate the data signals without using additional bits for route identification. This has the effect of being more efficient in its use.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the route identification method of the present invention. FIG. 2 shows the data signal A1 in the embodiment shown in FIG.
FIG. 2 is an explanatory diagram showing the frame structure of FIG. 12~ 2... FHC encoding circuit, 13~ 3, 15~ 5... pattern generator, 14~ 4, 16~ 6... Exclusive OR circuit, 17~
7...FEC decoding circuit. Agent Patent Attorney Uchihara 1, Hitoshi 2

Claims (1)

[Claims] An encoding circuit that encodes each of a plurality of data signals transmitted through different transmission routes into a block code, and each output of these encoding circuits is scrambled with a different scrambling pattern for each of the transmission routes. and a scrambling circuit for outputting to the transmission route.