JPS6350221A - Radio communication system - Google Patents

Abstract

PURPOSE:To improve the error rate of each current line and facilitate designing the timing of redundant bit transmission by encoding signals of respective lines to an error correction code by a common clock to transmit only redundant bits through a stand-by line if all current lines are normal and stopping the redundant bit transmission to switch a current line to the stand-by line if this current line out of current lines is abnormal. CONSTITUTION:In the transmission side, a clock means 101 generates a master clock common to devices of respective lines, and a means 102 generates timing signals, which are successively shifted by the number of redundant bits of the error correction code, for respective current lines based on said master clock. An error correction encoding means 103 synchronizes signals of respective lines by the master clock and successively shifts the head of a frame in accordance with timing signals to encode signals of respective lines to the error correction code and outputs this code. A redundant bit multiplexing means 104 multiplexes redundant bits of respective lines. A switching means 105 switches the current line, where trouble occurs, to the stand-by line, and a switching means 106 switches the signal of said redundant bits and the output of the means 105 and outputs them to the stand-by line. In the reception side, said redundant bits are used to decode the error correction code of current lines. Thus, the timing design of redundant bit transmission and the error correction in the reception side are made easy.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Prior Art (Figures 4 and 5) Field of Industrial Application Problems to be Solved by the Invention Means for Solving the Problems (Figure 1) Example of operation (Fig. 2, Fig. 3) Effect of the invention [Summary] In a wireless communication system in which one protection line is provided for a plurality of working lines, when all the working lines are normal, the working line is By transmitting the redundant bits of the error correction code using the protection line and performing error correction on the receiving side, the error rate of each working line is improved, and if any of the working lines is abnormal, the redundant bits are The faulty working line is rescued by stopping the transmission of bits and prohibiting the error υ correction operation on the receiving side, and transmitting the signal of the faulty working line using the protection line. To simplify the timing design of transmitting redundant bits by making them common to lines, and to simplify the device configuration by making the positional relationship of information bits and redundant bits of each line the same.

[Industrial application field]

The present invention relates to a wireless communication system that detects and corrects code errors on the receiving side by using an error correction code in signal transmission, and in particular, when all working lines are normal, redundant bits of the error correction code are transmitted via a protection line. The present invention relates to a wireless communication system for transmitting data.

In wireless communication systems, code errors in received signals often occur due to deterioration of propagation conditions due to selective fading. For this reason, a method is generally used in which signals are transmitted using error correction codes and errors are detected and corrected on the receiving side.

In this case, by transmitting redundant bits of the error correction code,
It is desired that the frequency utilization rate in communication lines does not decrease. Furthermore, it is desired that the operation for correcting code errors be easy and that the equipment configuration be simple.

[Conventional technology]

In wireless communication systems, in order to prevent deterioration of received signals due to deterioration in line quality, a common method is to set up a backup line and replace it with a failed working line that falls below the momentary interruption standard. be.

In addition, methods that use digital multiphase multilevel modulation to improve frequency utilization efficiency are often used, but as the number of multilevels increases, the signal spacing becomes narrower, resulting in transmission line distortion due to equipment deterioration or deterioration of propagation conditions. Code errors are likely to occur on the receiving side due to increases in noise and noise. For this reason, a method is used in which signals are transmitted using error correction codes and error detection and correction is performed on the receiving side to improve signal quality.

In this case, when all working lines are normal, the redundant bits of the error correction code are transmitted using vacant spare circuits, thereby avoiding a decrease in the frequency usage efficiency of the main signal of each working line due to the insertion of redundant bits. can do.

FIG. 4 shows an example of the configuration of a conventional wireless communication device, in which (cL) shows the transmitting side and (b) shows the receiving side.

On the transmitting side, the baseband switch EBSW connects the input signals 1 to N to the working lines 1 to N, respectively, or connects them to the protection line P.
When there is no fault in the working lines, the input signals 1 to N are connected to be sent to the working lines 1 to N, respectively. The signals on each working line are converted from bipolar signals to unipolar signals via bipolar/unipolar converters B/U, and then speed converted and converted from serial signals to parallel signals at speed conversion/serial/parallel converters 5c-s7p. and applied to the modulator MOD. Each modulator, 'bfOD, converts the input parallel signal into a multiphase, multilevel modulated signal, such as a 64QA, ', (signal), and each transmitter TX thereby generates a radio frequency signal for the working lines 1 to N. These signals are combined through a multiplexer (not shown) and sent out to the other party's station via an antenna.

At this time, the error correction encoder FEN ENC performs speed conversion and
Check bits of error correction codes for each channel are created in accordance with the signals of each line from the serial/parallel converters 5c-s7p. The check bit multiplexing unit CEMUX multiplexes the check bits of each working line into one channel signal. On the other hand, switch SW is baseband switch BB
In response to the control signal from SW, check bit multiplexing unit CB
The multiplexed test bit signal from the MUX is applied to the modulator MOD.

The modulator MOD converts the input signal into a multiphase multilevel signal similar to each working line. This signal is converted to a radio frequency signal of the protection line P via the transmitter TX, combined with the signal of the working line via a multiplexer, and supplied to the antenna.

On the receiving side, the signal from the antenna is separated into signals for working lines 1 to N and signals for protection line P through a branching filter (not shown). Each receiver RX receives the signal of the respective line and inputs it to the demodulator DEW, and each demodulator DEM demodulates the input signal and reproduces the original parallel signal.

Each demodulated output goes through a delay adjuster DLY ADJ to have its phase aligned, and the signals of each working line 1 to N are further sent to a delay circuit DL.
It is added to the exclusive OR circuit EOH via Y.

On the other hand, the error correction decoding unit FECDEC separates the check bits of each working line from the demodulated signal of the protection line P, calculates syndromes between them and the demodulated signal of each working line,
Generates an error position detection signal.

The exclusive OR circuit EOR performs an exclusive OR operation on the demodulated signal of each working line whose phase has been adjusted through the delay circuit DLY, using the error υ position detection signal for each channel. Corrects error bits.

The error-corrected signal of each working line is converted from a parallel signal to a serial signal via a speed converter/parallel/serial converter 5c-p7s, and is also speed-converted to produce an output consisting of a unipolar signal. The unipolar/bipolar converter U/B converts the unipolar signal input into a bipolar signal and outputs it, thereby converting the baseband switch BES.
output signals for channels 1-N via W.

When there is a fault in any of the working lines 1 to N, the baseband switch BE SW switches the input for the faulty line to the protection line, and the control signal causes the switch SW to switch to the speed converter/serial/parallel converter sc - syp
side, and outputs the signal of the protection line as a radio frequency signal P.

At the same time, on the receiving side, the signal on the protection line is phase-adjusted via the delay adjuster DLY ADJ, the delay circuit DLY, and added to the speed converter/parallel/serial converter 5C-P/S, along with the signal on the remaining working line. Parallel/serial conversion and speed conversion are performed, and the signal is converted into a bipolar signal via a unipolar/bipolar converter U/B, and is input to the baseband switch BB SW. This allows the baseband switch BE f
From f, the output of the protection line P is added to produce N-channel output signals 1 to N. At this time, the error υ correction decoding unit FEC
DEC operation is prohibited and no error position detection signal is output.

Therefore, no code correction operation is performed in the exclusive OR circuit EOR.

FIG. 5 shows an example of the structure of a transmission code in the wireless communication system shown in FIG. 4 during normal operation. Channels 1, 2 of the working line. ......, in N, the information bits ■, ■, ......, ■2■', ■', ...
・・・、■′、■″、■9．・・・・・・、■′、・・
-... are transmitted sequentially for each frame, whereas on the protection line P, the similar fire information bit ■.

■、・・・・・・、Inspection corresponding to ■Vitro, Kasumi,・
...2 diagram, information bits ■', ■', ...
■ Check bit ml corresponding to ', [i] J.

. . . 2′, . . . are shown to be multiplexed and transmitted, respectively.

In this way, in the wireless communication system shown in Figures 4 and 5, when the working line is normal, the redundant bits of the error correction code for each working line are transmitted using the protection line, and the receiving side This can be used to perform error detection and correction operations on each working line, and in the event of an abnormality in the working line, the error correction operation on each working line is prohibited.
Signals from the failed working line can be transmitted using the protection line.

[Problem that the invention seeks to solve]

In the wireless communication systems shown in Figures 4 and 5, each working line has a unique clock for creating a transmission signal, making it difficult to synchronize the timing when transmitting redundant bits. , the problem is that it is difficult to design.

Also, on the receiving side, when calculating the syndrome from the redundant bits transmitted via the protection line and the data on each working line, division is performed on the data on the working line and the redundant bits, as shown in Figure 4. In this system, the clocks of each line are asynchronous, making it difficult to synchronize the timing.
There are some aspects that are difficult to get rid of. 'Also, even if synchronized, if the frames of each line are at the same position, memory is required to delay the data of each line to the position of each redundant bit, which increases the circuit size. there were.

[Failure to solve the problem]

In order to solve these problems, the present invention has a wireless communication system having the principle configuration shown in FIG. 1, in which one protection line is provided for a plurality of working lines. , timing generation means 102 , error correction encoding means 103 , and redundant bit multiplexing means 10
4 and switching means 105° 106, and the receiving side is provided with error correction decoding means 107 and switching means 108.

Clock means 101 generates a master clock commonly used for devices on each line.

The timing generating means 102 generates a timing signal that is sequentially shifted by the number of redundant bits of the error correction code or more bits for each working line based on the master clock.

The error correction encoding means 103 synchronizes the signals of each line with a master clock, and sequentially shifts the beginning of the frame according to the timing signal generated by the timing generation means 102 to error correction encode the signals of each working line. output.

Redundant bit multiplexing means 104 multiplexes redundant bits in the error correction code of each line.

The first switching means 105 switches the failed working line to a protection line.

The second switching means 106 includes the redundant bit multiplexing means 1
04 multiplexed redundant bit signal and the output of the first switching means 105 are switched and outputted to the protection line.

The error correction decoding means 107 performs error correction decoding on the signals of each working line using the redundant bits transmitted via the protection line.

The fifth switching means 108 switches the signal of the faulty working line transmitted via the protection line to the corresponding working line and outputs the signal.

[For production]

When all working lines are normal, the signals of each working line are encoded with error correction code, and only the respective redundant bits are multiplexed and transmitted via the protection line, and on the receiving side, the signals of the redundant bits are separated for each line. The error correction operation is performed for each working line using the signals of the faulty working line and the error correction operation is prohibited on the receiving side when one of the working lines is abnormal, and the signal of the faulty working line is By transmitting the data through the protection line, the faulty working line is relieved. In this case, the clock used for error correction encoding on each line on the transmitting side is made common to each working line to facilitate timing design for transmitting redundant bits to the receiving side, and the position of information bits on each line is By sequentially shifting the relationships for each line and aligning the redundant bits and the temporal relationships, it is possible to eliminate the need for memory for waiting information bits at the corresponding redundant bits on the receiving side.
The device configuration can be simplified.

〔Example〕

FIG. 2 shows an embodiment of the present invention, (c
L) shows the transmitting side, and (b) shows the receiving side.

In FIG. 2, the same reference numerals as in FIG. 4 indicate the same parts, and their operations are also similar. On the transmitting side and the receiving side, A(K is a master clock, CTR frame counter, and TL%f is a timing generation circuit.

Further, FIG. 6 shows an example of the structure of a transmission code in a normal state in the embodiment of FIG. 2.

On the transmitting side, a frame counter CTR generates a signal with a frame period of each channel signal in response to a clock signal of a master clock MK.

The timing generation circuit TIM generates a timing signal for each channel by sequentially shifting the signal of the frame counter CTR by the number of error correction redundant bits or more bits for each channel.

The speed conversion/serial/parallel converters 5c-s7p speed convert the signals of each working line and protection line using a common clock signal from the master clock and VK, and convert serial signals to parallel signals to generate outputs. However, at this time, the signals of each channel are stored in a -H buffer, and are sequentially read out and converted by the timing signal of the timing generation circuit TIM, so that the number of redundant bits for error υ correction or the number of redundant bits for error υ correction is sequentially determined for each channel. The bits are shifted by the above number of bits. The signals of each channel are respectively applied to a modulator MQ7).

When there is no fault in the working line, the error correction encoder FECE
The NC creates check bits of error correction codes for the signals of each working line, and sends the check bits to the check bit multiplexing unit CB MU.
X multiplexes this into one channel signal. The switch SW applies the multiplexed check bit signal of the check bit multiplexer CB MUX to the modulator MOD in response to a control signal from the baseband switch BB ff.

Each modulator MOD converts the input signal into a multi-phase multi-value modulation signal, thereby generating radio frequency signals for the working lines 1 to N and the protection line P through the transmitter TX of each channel. This is the same as in the conventional example shown in the figure.

The master clock MK on the receiving side is synchronized with the master clock MK on the transmitting side. On the receiving side, receiver R
The signals of each working line received via X and demodulated by the demodulator DEH are applied to the exclusive logic circuit EOR via the delay circuit DLY. The error correction decoding unit FECDEC extracts the check bits of each working line from the demodulated signal of the protection line P.
The conventional example shown in Fig. 4 is to separate the signal, generate an error position detection signal for each channel from this and the demodulated signal of each working line, and use this to correct the error bit in the exclusive OR circuit EOR. It's the same.

The error-corrected signal of each working line is converted from a parallel signal to a serial signal in a speed converter/parallel/'serial converter sc-p7s, and is also speed-converted to produce an output consisting of a unipolar signal. The signals of each channel are temporarily stored in the batzer memory and read out by the clock of the master clock M, thereby producing output signals aligned at the same timing for each channel. Depending on the output signal of each channel, unipolar/bipolar conversion circuit U/B and baseband switch EB SW
The process of generating N-channel output signals 1 to N is similar to the conventional example shown in FIG.

On the other hand, when there is a fault in one of the working lines, the signal of the faulty working line is transmitted to the protection line P (instead of redundant bits) on the transmitting side, and the error correction decoding unit FECD is transmitted on the receiving side.
By prohibiting the operation of EC and stopping the error correction operation in the exclusive OR circuit EOR, the signal of the faulty working line transmitted via the protection line P is output as a signal of the corresponding channel. This is the same as in the conventional example shown in FIG. 4, in that it is used for the purpose of relieving the faulty working line.

〔Effect of the invention〕

As explained above, according to the present invention, when the working line is normal, the redundant bits of the error correction code are transmitted via the protection line,
By performing error correction on the receiving side, error correction is performed without reducing the frequency utilization efficiency of each line, improving line quality. In the event of a failure in the working line, this can be switched to a backup line, which can be used as a backup line. The line can be used for its original purpose of relieving a faulty working line. According to the present invention, since the transmission clock is common to each working line, it is easy to design the timing for transmitting redundant bits, and it is also easy to perform error correction on the receiving side. Furthermore, since the information bits and redundant bits of each line can be placed in the same positional relationship, no memory is required for timing alignment, and the circuit scale is reduced.

[Brief explanation of drawings]

1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, FIG. 3 is a diagram showing the transmission code configuration in the embodiment of FIG. 2, FIG. 5 is a diagram illustrating an example of the configuration of a conventional wireless communication system, and FIG. 5 is a diagram illustrating a conventional transmission code configuration. EB SW...Baseband switch B/U...
・Bipolar/unipolar converter 5c-s7p...Speed conversion ・Serial/parallel converter MOD...Modulator TX...Transmitter FECENC...Error) Correction encoder CB MUX Check bit multiplexer SW ...Switch MK ...Master clock CTR ...Frame counter TIM ...Timing generation circuit RX ...Receiver DEW ...Demodulator DLY ...Delay circuit EOR ...Exclusive OR circuit

Claims (1)

[Claims] In a wireless communication system in which one protection line is provided for a plurality of working lines, there is provided a clock means (101) for generating a master clock, and error correction for each working line using the master clock. Timing generation means (10
2); and an error correction encoding means (103) for synchronizing with the master clock and sequentially shifting the beginning of the frame according to the timing signal to encode the signal of each working line for error correction; a redundant bit multiplexing means (104) for multiplexing redundant bits in an error correction code; a first switching means (105) for switching a signal on a faulty working line to a protection line; and a redundant bit multiplexing means (104) for multiplexing redundant bits in an error correction code. a second switching means (106) for switching between the output and the output of the first switching means (105) and outputting the same to the protection line; Therefore, an error correction decoding means (107) performs error correction decoding on the signals of each working line, and a third means (107) performs error correction decoding on the signals of each working line, and a third unit that switches the signal of the faulty working line transmitted via the protection line to the corresponding working line and outputs the signal. A switching means (108) is provided on the receiving side, and when all the working lines are normal, each working line is encoded with error correction coding, each redundant bit is transmitted via the protection line, and the receiving side converts each working line to each working line. What is claimed is: 1. A wireless communication system that performs an error correction operation, and when one of the working lines is abnormal, prohibits the error correction operation and transmits a signal on the working line via a protection line.