JPS6358876A - Non-volatile semiconductor device - Google Patents
Non-volatile semiconductor deviceInfo
- Publication number
- JPS6358876A JPS6358876A JP61201669A JP20166986A JPS6358876A JP S6358876 A JPS6358876 A JP S6358876A JP 61201669 A JP61201669 A JP 61201669A JP 20166986 A JP20166986 A JP 20166986A JP S6358876 A JPS6358876 A JP S6358876A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- groove
- diffusion layer
- thin film
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000010408 film Substances 0.000 claims abstract description 53
- 238000009792 diffusion process Methods 0.000 claims abstract description 28
- 239000010409 thin film Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 21
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 17
- 229920005591 polysilicon Polymers 0.000 abstract description 17
- 238000002347 injection Methods 0.000 abstract description 7
- 239000007924 injection Substances 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract description 2
- 230000008030 elimination Effects 0.000 abstract 2
- 238000003379 elimination reaction Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 42
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 241000282330 Procyon lotor Species 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- NTQGILPNLZZOJH-UHFFFAOYSA-N disilicon Chemical compound [Si]#[Si] NTQGILPNLZZOJH-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、ＥＥＰ ＲＯＭ （Ｅｌｅｃｔｒｉｃａｌ
ｌｙ Ｅｒａｓａｂｌｅａｎｄ Ｐｒｏｇｒａｍｍａｂ
ｌｅ Ｒｅａｄ ０ｎｌｙ Ｍｅｍｏｒｙ ）と称され
る不信発性半導体装置７ζ関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This invention is directed to EEP ROM (Electrical
ly Erasable and Programmab
The present invention relates to a non-volatile semiconductor device 7ζ called "Le Read Only Memory".
（従来の技術）
従来のこの種の不揮発性半導体装置を、第２図に示す従
来の製造方法を参照して製造工程５．項に説明する。な
お、第２図の製造方法は、特開昭６１−１８２２６７号
公報に開示される。(Prior Art) A conventional non-volatile semiconductor device of this type is manufactured by manufacturing process 5. with reference to the conventional manufacturing method shown in FIG. This is explained in section. The manufacturing method shown in FIG. 2 is disclosed in Japanese Patent Application Laid-open No. 182267/1983.
第２図（ａ）において、１はＰ型シリコン単結晶基板で
あり、まずこの基板１の表面部に通常のＬＯＣＯ８法に
よりフィールド酸化膜２を選択的に形成することにより
、基板面をフィールド領域とアクティブ領域に分ける。In FIG. 2(a), reference numeral 1 denotes a P-type silicon single crystal substrate. First, a field oxide film 2 is selectively formed on the surface of the substrate 1 by the usual LOCO8 method, thereby converting the substrate surface into a field region. and active area.
次に、アクティブ領域の基板１表面に酸化処理によジシ
リコン酸化膜３を形成する。Next, a disilicon oxide film 3 is formed on the surface of the substrate 1 in the active region by oxidation treatment.
次に、第２図（ｂ）に示すように、シリコン酸化ａ３の
一部にホトリングラフィ技術により開口部４を形成する
。そして、この開口部４に対応する部分の基板１表面部
内にイオンインプランテーション技術により第１のＮ型
拡散層５′ｆ！：形成する。Next, as shown in FIG. 2(b), an opening 4 is formed in a part of the silicon oxide a3 by photolithography. Then, a first N-type diffusion layer 5'f! is formed in the surface of the substrate 1 in a portion corresponding to the opening 4 by ion implantation technology. :Form.
その後、酸化処理を施すことにより、第１のＮ型拡散層
５上に第２図１（ｃ）に示すように１００＾厚程度の非
常に薄いシリコン酸化膜６を形成する。この時、シリコ
ン酸化膜３は５００人厚程度となり、このシリコン酸化
膜３と前記シリコン酸化膜６とにより局所的に薄膜部を
有する第１のｆ−）酸化膜７が製造される。Thereafter, by performing oxidation treatment, a very thin silicon oxide film 6 of about 100^ thickness is formed on the first N-type diffusion layer 5, as shown in FIG. 2(c). At this time, the silicon oxide film 3 has a thickness of about 500 nm, and the silicon oxide film 3 and the silicon oxide film 6 form a first f-) oxide film 7 having locally thin film portions.
次に、第２図（ｄ）に示す第１のポリシリコン層８゜！
２２のゲート酸化膜９および第２のポリシリコン層１０
（第１および第２のポリシリコン層８．１０には不純物
がＭａ度にドーグされる）と順次全面をで形成した後、
これらと前記第１のゲート酸化膜７をホトリソ技術によ
りパターニングすることにより、それらを第２図（ｄ）
に示すようにｒ−）領域にのみ残す。Next, the first polysilicon layer 8° shown in FIG. 2(d) is formed.
22 gate oxide film 9 and second polysilicon layer 10
(The first and second polysilicon layers 8 and 10 are doped with impurities to Ma degree).
By patterning these and the first gate oxide film 7 by photolithography, they are formed as shown in FIG. 2(d).
As shown in , it is left only in the r-) region.
その後、前記パターニングにより露出した基板１の表面
部にソース・ドレイン領域となる第２のＮ型拡散層１１
ａ、ｌｌｂを自己整合技術により前記第２図（ｄ）に示
すように形成する。この時、前記ＪｌのＮ型拡散層５が
ドレイン領域としての一部の第２のＮ型拡散層１１ｂと
接触し電気的に導通した状態となり、第１のＮ型拡散層
５はドレイン領域の一部となる。After that, a second N-type diffusion layer 11 which becomes a source/drain region is formed on the surface of the substrate 1 exposed by the patterning.
A, llb are formed by self-alignment technique as shown in FIG. 2(d). At this time, the N-type diffusion layer 5 of Jl comes into contact with a part of the second N-type diffusion layer 11b serving as the drain region and becomes electrically conductive, and the first N-type diffusion layer 5 of the drain region Become a part.
しかる後、第２のポリシリコン層１０．第２のｒ−ト酸
化膜９．第１のポリシリコン層８および第１のＰ−ト酸
化膜７からなる積層体の表面に第２図（ｅ）に示すよう
にシリコン酸化１漠１２（絶縁膜）を形成した後、同図
に示すように全面にＰＳＧなどの中間絶縁膜１３を形成
し、さらにこの中間絶縁、摸１３と前記シリコン酸化膜
１２にホトリソグラフィ技術によりコンタクト穴１４ａ
、１４ｂ。Thereafter, a second polysilicon layer 10. Second r-t oxide film 9. After forming a silicon oxide film 12 (insulating film) on the surface of the laminate consisting of the first polysilicon layer 8 and the first P-oxide film 7, as shown in FIG. As shown in FIG. 3, an intermediate insulating film 13 such as PSG is formed on the entire surface, and contact holes 14a are formed in this intermediate insulating film 13 and the silicon oxide film 12 by photolithography.
, 14b.
１４ｃ’ｚ開ける。さらに、このコンタクト穴１４ａ。Open 14c’z. Furthermore, this contact hole 14a.
１４ｂ、１４ｃを通して第２のＮ型拡散層１１ａ。The second N-type diffusion layer 11a passes through 14b and 14c.
１１ｂおよび第２のポリシリコン層１０に接続されるア
ルミ配線１５ａ、１５ｂ、１５ｃを形成し、最後に図示
しない保護膜を形成する。Aluminum wirings 15a, 15b, and 15c connected to 11b and the second polysilicon layer 10 are formed, and finally a protective film (not shown) is formed.
（発明が解決しようとする問題点）
しかるに、上記のようにして製造された従来の装設では
、微細化に伴ない第１のゲート酸化膜７の局所的な薄膜
部（シリコン酸化、摸６）が小さくなると、該薄膜部を
通して第１のポリシリコン層８（フローティングゲート
）に対して行われる電荷の注入および消去効圭が低下し
てしまうという欠点があった。(Problems to be Solved by the Invention) However, in the conventional device manufactured as described above, local thin film portions of the first gate oxide film 7 (silicon oxide, ) becomes smaller, the disadvantage is that the charge injection and erasing efficiency performed on the first polysilicon layer 8 (floating gate) through the thin film portion decreases.
この発明は上記の点に鑑みなされたもので、その目的は
、第１のＰ−）酸化膜の局所的な薄膜部の面積が縮小さ
れても、該薄膜部を通してフローティングゲートに対し
て行われる電荷の注入および消去効率を高くとることが
できる不揮発性半導体装置を提供することにある。The present invention has been made in view of the above points, and its object is to provide a floating gate through the first P-) oxide film even if the area of the local thin film portion is reduced. An object of the present invention is to provide a nonvolatile semiconductor device that can have high charge injection and erasing efficiency.
（問題点を解決するための手段）
この発明では、半導体基板に形成された拡散層内に溝を
形成し、その内壁に第１のゲート酸化膜の局所的な薄膜
部を形成し、さらにその溝内に一部埋め込んでフローテ
ィングゲートを形成する。(Means for Solving the Problems) In the present invention, a trench is formed in a diffusion layer formed in a semiconductor substrate, a local thin film portion of a first gate oxide film is formed on the inner wall of the trench, and A floating gate is formed by partially filling the trench.
（作用）
このような構成においては、第１のｙ−４酸化嘆の局所
的な薄膜部の面積が縮小されても、該薄膜部を払んで接
触する拡散層とフローティングゲートとの面、損を、溝
の側面によって大きくとることができる。(Function) In such a configuration, even if the area of the local thin film portion of the first Y-4 oxidation layer is reduced, the surface of the floating gate and the diffusion layer that come into contact by brushing off the thin film portion, the damage can be increased depending on the side surface of the groove.
（’ｔ４Ｚｉ’４例）
以下、この発明の不揮発１半導体装置の一実施例を、第
１図を参照して製造工程頭に説明する。(Example of 't4Zi') An embodiment of a non-volatile semiconductor device of the present invention will be described below with reference to FIG. 1, starting from the beginning of the manufacturing process.
第１図（ａ）において、２１はＰ型シリコン単結晶基板
（半導体基板）であり、まず、この基板２１の表面部に
通常のＬＯＣＯ８法によりフィールド酸化膜２２を選択
的に形成することにより、基板面をフィールド領域とア
クティブ領域に分ける。次に、アクティブ領域の基板２
１表面部内の一部分にイオンイングランチージョンによ
り第１のＮ型拡散層２３を形成し、アニール処理により
成る程度の深さまで拡散させる。その後、この第１のＮ
型拡散層２３の表面を含むアクティブ領域の基板２１全
表面にシリコン酸化膜２４を５００人厚程度に形成する
。In FIG. 1(a), 21 is a P-type silicon single crystal substrate (semiconductor substrate). First, a field oxide film 22 is selectively formed on the surface of this substrate 21 by the usual LOCO8 method. The substrate surface is divided into a field area and an active area. Next, the active area substrate 2
A first N-type diffusion layer 23 is formed in a portion of one surface by ion implantation, and is diffused to a depth that can be achieved by annealing. Then this first N
A silicon oxide film 24 is formed to a thickness of approximately 500 nm over the entire surface of the substrate 21 in the active region including the surface of the type diffusion layer 23 .
その後、第１図（ｂ）に示すように、シリコン酸化膜２
４に、前記第１のＮ型拡散層２３上にて開口部２５をホ
トリソグラフィ技術により形成する。After that, as shown in FIG. 1(b), the silicon oxide film 2
4, an opening 25 is formed on the first N-type diffusion layer 23 by photolithography.
そして、その開口部２５全通してＲＩＥ技術により第１
のＮ型拡散層２３の一部分をエツチングすることにより
、同図に示すように第１のＮ型拡散ｊ脅２３内に溝２６
を形成する。Then, through the entire opening 25, the first
By etching a portion of the N-type diffusion layer 23, a groove 26 is formed in the first N-type diffusion layer 23 as shown in the figure.
form.
次いで、その溝２６の内壁に第１図（Ｃ）に示すように
１００＾厚程度の非常に薄いシリコン酸化膜２７を形成
する。この薄いシリコン酸化膜２７は第１のｒ−）酸化
膜の薄膜部であり、このシリコン酸化膜２７と前記５０
０＾厚程度のシリコン酸化膜２４とにより局所的に薄膜
部を有する第１のダート酸化・メ２８が形成される。Next, a very thin silicon oxide film 27 of about 100^ thickness is formed on the inner wall of the groove 26, as shown in FIG. 1(C). This thin silicon oxide film 27 is a thin film part of the first r-) oxide film, and this silicon oxide film 27 and the
A first dirt oxide film 28 having a locally thin film portion is formed by the silicon oxide film 24 having a thickness of about 0^.
その後は、第１図（ｄ）に示す第１のポリシリコン層２
９．第２のｆ−）酸化膜３０および第２のポリシリコン
層３１（第１および第２のポリシリコン層２９．３１に
は不純物が高濃度にドーグされる）を順次全面に形成し
ｆｃ後、これらと前記第１のＰ−ト酸化嘆２８をホトリ
ソ技術によυノンターニングすることにより、それらを
第１図（ｄ）に示すようにｒ−ト領域にのみ残す。さら
に、七〇／９ターニングにより露出した基板２１の衣面
部にンース・ドレイン領域となる第２のＮ型拡散層３２
ａ。After that, the first polysilicon layer 2 shown in FIG.
9. Second f-) Oxide film 30 and second polysilicon layer 31 (the first and second polysilicon layers 29 and 31 are doped with impurities at a high concentration) are sequentially formed on the entire surface, and after fc, By non-turning these and the first P-oxide layer 28 by photolithography, they are left only in the r-tone region as shown in FIG. 1(d). Furthermore, a second N-type diffusion layer 32 is formed on the surface of the substrate 21 exposed by the 70/9 turning process to become a drain region.
a.
３２ｂを自己整合技術により形成する。さらに、第２の
ポリシリコン層３１．第２のゲート酸化膜３０、第１の
ポリシリコン層２９および第１のｒ−ト酸化４２８から
なる積層体の表面にシリコン酸化膜３３（絶縁膜）を形
成した後、全面にＰＳＧなどの中間絶縁膜３４を形成し
、この中間絶縁膜３４とシリコン酸化、９３３にホトリ
ン技術によりコンタクト穴３５ａ、３５ｂ、３５ｃを開
けた後、アルミ配置’９ｊ３６ａ、３６ｂ、３６ｃを形
成し、最後に図示しない保ｊ膜を形成する。32b is formed by self-alignment technique. Furthermore, a second polysilicon layer 31. After forming a silicon oxide film 33 (insulating film) on the surface of the laminate consisting of the second gate oxide film 30, the first polysilicon layer 29 and the first r-oxide 428, an intermediate film such as PSG is formed on the entire surface. After forming the insulating film 34, forming contact holes 35a, 35b, and 35c in the intermediate insulating film 34 and silicon oxide layer 933 using photorin technology, forming aluminum arrangements '9j 36a, 36b, and 36c, and finally forming a protective layer (not shown). j form a film.
なお、ゲート領域に残された第１のポリシリコン層２９
はフローティングｒ−トを形成するものであり、このフ
ローティングｒ−）（第１のポリシリコン層２９）は、
第１のｒ−ト酸化膜２８の薄膜部（シリコン酸化膜２７
）で内壁が覆われた溝２６内に一部埋め込まれて形成さ
れることになる。Note that the first polysilicon layer 29 left in the gate region
forms a floating r-t, and this floating r-) (first polysilicon layer 29) is
Thin film portion of first r-to oxide film 28 (silicon oxide film 27
) is formed by being partially embedded in the groove 26 whose inner wall is covered.
また、第１のＮ型拡散層２３は、ドレイン領域としての
一部の第２のＮ型拡散層３２ｂと接触し電気的に導通し
念状態となり、ドレイン領域の一部となる。Further, the first N-type diffusion layer 23 comes into contact with a part of the second N-type diffusion layer 32b serving as a drain region, becomes electrically conductive, and becomes a virtual state, and becomes a part of the drain region.
以上のように、この発明の一実施例では、第１のＮ型拡
散層２３に溝２６が形成され、その内壁に第１のｆ−）
酸化膜２８の局所的な薄膜部（シリコン酸化膜２７）が
形成され、その溝２６内に一部埋め込まれてフローティ
ングｆ−１（第１０ポリシリコン層２９）が形成される
ことになる。As described above, in one embodiment of the present invention, the groove 26 is formed in the first N-type diffusion layer 23, and the first f-)
A local thin film portion (silicon oxide film 27) of the oxide film 28 is formed, and a portion of the trench 26 is buried to form a floating f-1 (tenth polysilicon layer 29).
したがって、第１のｒ−ト酸化膜２８の局所的な薄膜部
の面積が縮小されても、該薄膜部を挾んで接触する拡散
層とフローティングゲートとの面積は、溝２６の側面に
よって大きくとれるようになる。例えば、溝２６の開口
部の面積が１．５ Ｘ １，５μばである時、溝２６の
深さを０．３μｍとすれば、溝２６側面の面積は０．３
Ｘ １．５ Ｘ ４ ＝ １，８μゴとな９、接触面
積は従来０８割も増加した。そして、その結果、第１の
ダート酸化膜２８の薄膜部を通してフローティングゲー
トに対して電荷の注入・消去を行う際の注入・消去電流
も８割増加となり、注入・消去効率が非常に向上する。Therefore, even if the area of the local thin film portion of the first r-t oxide film 28 is reduced, the area of the floating gate and the diffusion layer that sandwich and contact the thin film portion can be increased by the side surfaces of the trench 26. It becomes like this. For example, if the area of the opening of the groove 26 is 1.5 x 1.5 μm and the depth of the groove 26 is 0.3 μm, the area of the side surface of the groove 26 is 0.3 μm.
X 1.5 X 4 = 1.8μ (9) The contact area has increased by 0.80% compared to before. As a result, the injection/erasing current when injecting/erasing charges to the floating gate through the thin film portion of the first dirt oxide film 28 increases by 80%, and the injection/erasing efficiency is greatly improved.
（発明の効果）
以上詳細に説明したように、この発明の装置によれば、
半導体基板に形成された拡散層内に溝を形成し、その内
壁に、′ｇｌのダート酸化１漠の局所的な薄膜部を形成
し、その溝内に一部埋め込んでフローティングｒ−）を
形成したので、前記薄）漠部の面積が縮小されても、溝
の側面を利用して拡散層とフローティングｒ−トとの前
記薄膜部を挾んでの接触面積を大きくとることができ、
薄膜部を通シてフローティングゲートに対して行われる
電荷の注入あ・よび消去効率を高くとることができる。(Effects of the Invention) As explained in detail above, according to the device of the present invention,
A groove is formed in the diffusion layer formed in the semiconductor substrate, a local thin film portion of 'gl dirt oxidation 1 is formed on the inner wall of the groove, and a part of the groove is buried to form a floating r-). Therefore, even if the area of the thin film part is reduced, it is possible to increase the contact area between the diffusion layer and the floating r-t by sandwiching the thin film part by using the side surfaces of the groove.
Charge injection and erasing efficiency performed on the floating gate through the thin film portion can be increased.
第１図はこの発明の不揮発性半導体装置の一実施例を説
明するための製造工程断面図、第２凶は従来の装置２Ｉ
−説明するための製造工程断面図である。
２１・・・Ｐ型シリコン単結晶基板、２３・・・第１の
Ｎ型拡散層、２４・・・シリコン酸化）漠、２６・・・
ｎ１２７・・・シリコン酸化膜、２８・・・ＷＪｌのｒ
−ト酸化膜、２９・・・第１のポリシリコン層、３２ａ
、３２ｂ・・・第２のＮ型拡散層。
特許出願人 沖電気工業株式会社
代理人 弁理士 菊 池 弘 −１に
′３・−・・ｈ
：１−発Ｂ門−大オセ１列？：光Ｂハオろｔ−灼の製ｔ
フェ１■牟筐１コ３２ｏ、３２ｂ ？２１１Ｎ”！−
徂敗４下１１’！−夫万セ１デ１乞状−ｌハ１ろＴ＝め
の）斥１工Ｔヱ断面口第１１
丈末Ｘ石乞誂明Ｔ名ｒ： ／、 Ｉ−＋製１ユｕ１昨面
囚７２図
夜米裂Ｉ乞誂褐するｒ；めの製造上↑！狸なｉ図７２図FIG. 1 is a cross-sectional view of the manufacturing process for explaining one embodiment of the non-volatile semiconductor device of the present invention, and the second figure is a conventional device 2I.
- It is a manufacturing process sectional view for explanation. 21... P type silicon single crystal substrate, 23... First N type diffusion layer, 24... Silicon oxide), 26...
n127...silicon oxide film, 28...r of WJl
- oxide film, 29...first polysilicon layer, 32a
, 32b... second N-type diffusion layer. Patent Applicant Oki Electric Industry Co., Ltd. Representative Patent Attorney Hiroshi Kikuchi -1 to '3...h: 1-B Gate-Ose 1 row? : Light B Haoro t-Saku no Sei t
Fe 1 ■ Muko 1ko 32o, 32b? 211N"!-
Defeat 4-11'! -fumanse1de1beggar-lha1roT=meno)ko1workTヱsectionmouth 11th length Prisoner 72 picture night rice cracking I beg for browning r; production of ↑! raccoon i figure 72 figure
Claims (1)
の局所的な薄膜部が位置し、その薄膜部を通してフロー
ティングゲートに対する電荷の注入および消去を行うよ
うにした不揮発性半導体装置において、 （ａ）前記拡散層内に溝を形成し、 （ｂ）その溝の内壁に第１のゲート酸化膜の局所的な薄
膜部を形成し、 （ｃ）この薄膜部で覆われた前記溝内に一部埋め込んで
フローテイングゲートを形成するようにしたことを特徴
とする不揮発性半導体装置。[Claims] A non-volatile device in which a local thin film portion of the first gate oxide film is located on a diffusion layer formed on a semiconductor substrate, and charges are injected and erased to and from the floating gate through the thin film portion. In the semiconductor device, (a) a groove is formed in the diffusion layer, (b) a local thin film portion of a first gate oxide film is formed on the inner wall of the groove, and (c) the thin film portion is covered with the thin film portion. A nonvolatile semiconductor device, wherein a floating gate is formed by partially filling the groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61201669A JPS6358876A (en) | 1986-08-29 | 1986-08-29 | Non-volatile semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61201669A JPS6358876A (en) | 1986-08-29 | 1986-08-29 | Non-volatile semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6358876A true JPS6358876A (en) | 1988-03-14 |
Family
ID=16444933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61201669A Pending JPS6358876A (en) | 1986-08-29 | 1986-08-29 | Non-volatile semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6358876A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6051465A (en) * | 1997-07-30 | 2000-04-18 | Matsushita Electronics Corporation | Method for fabricating nonvolatile semiconductor memory device |
| US6051860A (en) * | 1998-01-16 | 2000-04-18 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit |
| US6121655A (en) * | 1997-12-30 | 2000-09-19 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit |
| US6147379A (en) * | 1998-04-13 | 2000-11-14 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| WO2014115581A1 (en) * | 2013-01-25 | 2014-07-31 | セイコーインスツル株式会社 | Non-volatile semiconductor memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS611056A (en) * | 1984-06-14 | 1986-01-07 | Toshiba Corp | Nonvolatile semiconductor memory device |
| JPS6331170A (en) * | 1986-07-24 | 1988-02-09 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
-
1986
- 1986-08-29 JP JP61201669A patent/JPS6358876A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS611056A (en) * | 1984-06-14 | 1986-01-07 | Toshiba Corp | Nonvolatile semiconductor memory device |
| JPS6331170A (en) * | 1986-07-24 | 1988-02-09 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6051465A (en) * | 1997-07-30 | 2000-04-18 | Matsushita Electronics Corporation | Method for fabricating nonvolatile semiconductor memory device |
| US6121655A (en) * | 1997-12-30 | 2000-09-19 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit |
| US6380585B1 (en) | 1997-12-30 | 2002-04-30 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile semiconductor device capable of increased electron injection efficiency |
| US6051860A (en) * | 1998-01-16 | 2000-04-18 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit |
| US6358799B2 (en) | 1998-01-16 | 2002-03-19 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile semiconductor memory device and method for fabricating the same, and semiconductor integrated circuit device |
| US6147379A (en) * | 1998-04-13 | 2000-11-14 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| WO2014115581A1 (en) * | 2013-01-25 | 2014-07-31 | セイコーインスツル株式会社 | Non-volatile semiconductor memory |
| JP2014143377A (en) * | 2013-01-25 | 2014-08-07 | Seiko Instruments Inc | Semiconductor nonvolatile memory |
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