JPS6366972A - Semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain an ultraviolet ray erasable, electrically writable read only semiconductor memory which has high production efficiency and extremely high integration by symmetrically disposing a control gate and a floating gate with respect to a diffused layer region. CONSTITUTION:A control gate 21 made of polycrystalline silicon is disposed on a semiconductor substrate 6, a floating gate 31 made of polycrystalline silicon is disposed at one side of the gate 21, and a plurality of combinations of the gates 21 and the gates 31 are disposed symmetrically through a reverse conductivity type diffused layer regions 4, 5 to the substrate 6. Thus, its integration density can be raised. Since the floating gate can be obtained only by anisotropically etching the polycrystalline silicon layer and two memory regions can be formed at both sides by etching only the center of the polycrystalline silicon layer provided with the regions which become the floating gates at both sides, manufacturing steps can be simplified.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly to a read-only semiconductor memory device that can be erased by ultraviolet rays, is electrically writable, and a method for manufacturing the same. Regarding.

[Prior Art] Ultraviolet-erasable, electrically writable, read-only semiconductor storage devices have been used as storage devices for various electrical devices or electronic computers. This electrically writable, read-only semiconductor memory device has a polycrystalline silicon floating gate, and a write control gate is provided on the polycrystalline silicon floating gate. As the degree of integration of semiconductor memory devices with this type of structure increases, it becomes difficult to reduce the length in the vertical direction while reducing the length in the horizontal direction, making it difficult to design a memory device with the required characteristics. becomes difficult.

Therefore, the semiconductor device shown in FIG. 4 is an example of this in which the control gate is placed next to the floating gate to eliminate this drawback. In the figure, 41 is a substrate, and a control gate 4 made of polycrystalline silicon is connected through a gate oxide film 45.
2 and a floating gate 43 of polycrystalline silicon are formed. Further, in the substrate 41, an impurity region 47
48 are provided, and each serves as a source and a drain.

By creating a semiconductor memory device with such a structure, it is possible to reduce the vertical dimension, and it becomes easy to design a memory device with the necessary characteristics [Problem to be solved by the invention] However, such a structure In the storage device, since each of the 70 units is manufactured separately, the manufacturing efficiency is not necessarily high, and the degree of integration cannot be made very high.

The present invention has been made in view of these points, and provides an ultraviolet erasable, electrically writable, read-only semiconductor memory device that has high manufacturing efficiency and can have an extremely high degree of integration. The purpose is to

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention is characterized in that the control gate and the floating gate are arranged symmetrically with respect to the diffusion layer region.

[Function] With this configuration, it is possible to provide a semiconductor memory device with high manufacturing efficiency and high degree of integration.

[Example] FIG. 1 and FIG. 2 are diagrams showing an example of the present invention,
1(a) is a cross-sectional view taken along line A-A of the plan view shown in FIG. 2(b). FIG. 2 is a diagram showing a method for manufacturing a semiconductor memory device according to the present invention. be.

First, a method for manufacturing a semiconductor memory device according to the present invention will be explained using FIG. First, prepare a P-type substrate 6,
An element isolation oxide film shown as 7 in FIG. 1<b) is formed. (Not shown in Figure 2). Next, the P-type substrate 6
is thermally oxidized to form a gate oxide film 2. As this gate oxide film 2, a nitride film can also be used. Then, polycrystalline silicon 1 is deposited on this gate oxide film 2, and N
After mixing type impurities, a resist 9 is formed only in regions where control gates and floating gates are to be formed. (See Figure 2 (1)).

Polycrystalline silicon 1 is etched using resist 9 as a mask. After etching, the resist 9 is removed and an interlayer insulating film 10 is formed on the patterned polycrystalline silicon 1.
will be established. As the interlayer insulating film 10, polycrystalline silicon 1
In addition to a silicon oxide film obtained by thermally oxidizing a silicon nitride film, other insulating films such as a silicon nitride film may be used. This interlayer insulating film 10
Polycrystalline silicon 3, which will later be used as a floating gate, is deposited thereon, and N-type impurities are mixed into the polycrystalline silicon 3. (See Figure 2 (2)).

This substrate is etched without a mask (anisotropic etching). According to this etching, it is possible to increase the vertical etching speed of the polycrystalline silicon 3 and form the region 31 used as a ting gate. The insulating film 11 including the floating gate 31 is created (see FIG. 2 (3)). A resist 12 is provided on the substrate on which the insulating film 11 is formed, and the polycrystalline silicon 1 is divided into two regions by the window 15. Etch to separate the parts (Figure 2 (
4)).

As a result of etching, it is divided into two regions 21, 21 in which polycrystalline silicon is used as a control gate. After removing the resist 12, a polycrystalline silicon 70-ting gate 31.31. Using the control gates 21, 21 as masks, N-type impurities are ionized and implanted, and diffused through a heat treatment process to form N-type diffusion layers 4, 5.

These N-type diffusion layers 4 and 5 function as sources or drains. That is, when the hemi-type diffusion layer 4 is used as a source, N
The type diffusion layer 5 acts as a drain, and conversely, when the N type diffusion layer 5 is used as a source, the N type diffusion layer 4 acts as a drain (see FIG. 2 (5)).Finally, the interlayer insulating layer 16
is provided to complete the semiconductor memory device (see FIG. 1).

In the semiconductor memory device shown in FIG. 1, an aluminum wiring 14 is provided and a control gate electrode is drawn out through a contact hole 8. In the semiconductor memory device shown in FIG.

As shown in FIG. 1 (2), the N-type diffusion layers 4 and 5 are continuous in the vertical direction on a plane, and the control gate 2
1 and 21 are laterally connected to each other by an aluminum wiring 14 through a contact hole 8 on the element isolation oxide film 7.

With this configuration, the horizontal aluminum wiring 14 and the diffusion layer 4
, 5 one by one, only one storage device is selected. This operation is performed in area C surrounded by dotted lines in FIG. 1(a).

Polycrystalline silicon as a floating gate 31.3
In order to inject electrons into 1 (when writing a program or the like), the diffusion layer 5 is set to a high voltage, for example, about 10 V, and the diffusion layer 4 is lowered to O potential. Regarding the other diffusion layers 4, 5, all the diffusion layers 4, 5 on the right side of the selected element are dropped to the O potential, and on the left side, all the diffusion layers 4, 5 are made floating. A high voltage, for example, about 15V is applied to the control gates 21, 21 through the aluminum wiring 14. As a result, thermal electrons generated near the diffusion layer 5 pass through the gate oxide film 2 to the floating gate 31 of the selected memory device.
injected into. This is because a potential is induced in the floating gate 31 by the high voltage applied to the control gate 21, an electric field is generated in the gate oxide film 2 by this potential, and thermal electrons are injected into the floating gate by this electric field. .

When reading information, one aluminum wiring 14 is selected, an appropriate potential of, for example, 2V is applied to the diffusion layer 4, and the diffusion layer 5 is lowered to O potential. Regarding the other diffusion layers 4 and 5, the right side is all floating, and the left side is all set to O potential. A difference in the amount of current occurs depending on whether or not electrons are injected into the floating gate polycrystalline silicon 31 of the selected memory device, which becomes information.

Further, in order to erase the injected electrons, ultraviolet irradiation may be performed.

FIG. 3 is a plan view of another embodiment of the invention.

In FIG. 3, a control gate 21 extends in the horizontal direction, an aluminum wiring 14 extends in the vertical direction, and diffusion layers 4 and 5 are connected to the aluminum wiring 14 through contacts 8 provided in the interlayer insulating film 13, respectively. It is connected.

When injecting electrons, the control gate 21
Select just one wire and set it to a high voltage, for example 15V,
Select one aluminum wiring 14 connected to the diffusion layer 5,
For example, let it be IOV, and other diffusion layers 5 and 4
When all the aluminum wirings connected to the memory device are set to O potential, hot electrons are injected into the floating gate of the selected memory device.

When reading information, select only one control gate 21, select one aluminum wiring 14 connected to the diffusion layer 4, apply a voltage of about 2V, for example, across the selected aluminum wiring 14, and If all of the diffusion layers 4 and 5 other than the one shown in FIG. shall be. The scales are erased by ultraviolet light as before.

Note that the cross-sectional view along BB- corresponds to FIG. 1(1). In this embodiment, the wiring 14, which is a long wiring, is made of aluminum, which is advantageous because its resistance value can be reduced.

[Effects of the Invention] As described above, according to the present invention, a control gate and a floating gate are arranged on four parts on one side of the control gate, and a combination of the control gate and the floating gate is formed with a diffusion layer region in between. By arranging a plurality of symmetrically, the integration density can be increased.

Furthermore, the 70-ting gate can be obtained only by anisotropic etching of the polycrystalline silicon layer 3, and moreover, by etching only the central portion of the polycrystalline silicon layer 1, which has regions on both sides that will serve as floating gates. , since two storage device areas can be formed on both sides, the manufacturing process can be simplified and costs can be reduced.

Furthermore, since the structure is arranged symmetrically, wiring can be facilitated.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a diagram showing a method for manufacturing a semiconductor memory device according to the present invention, and FIG. 3 is a diagram showing an embodiment of the semiconductor memory device according to the present invention. The figure shown in FIG. 4 is a diagram showing a conventional example. 1... Polycrystalline silicon layer, 2... Gate oxide film 3.
...Polycrystalline silicon 4...N type diffusion layer (drain) 5...N type diffusion layer (source) 6...Substrate 7...Element isolation oxide film 8
...Contact hole, 9...Resist 10...
Interlayer insulating film 11... Insulating film 12... Resist 16... Interlayer insulating layer 21... Control gate 31... Floating gate

Claims (2)

[Claims] (1) A control gate made of polycrystalline silicon and a floating gate made of polycrystalline silicon are arranged on one side of the control gate on a semiconductor substrate,
A memory device in which a plurality of combinations of control gates and floating gates are arranged symmetrically through diffusion layer regions of a conductivity type opposite to that of a semiconductor substrate. (2) Forming a first polycrystalline silicon layer on the semiconductor board via a gate insulating film, and etching the first polycrystalline silicon layer to form a region where a control gate will be formed later. After forming an interlayer insulating film on the first polycrystalline silicon region patterned by this etching, a step of forming a second polycrystalline silicon gate to become a floating gate, and anisotropic etching. forming floating gates on the sides of the patterned first polycrystalline silicon region, and etching the central portion of the patterned first polycrystalline silicon to form two control gate regions. A method of manufacturing a semiconductor memory device, comprising a step of forming.