JPS6358697A - Static semiconductor memory device - Google Patents

Abstract

PURPOSE:To read data out of a semiconductor memory device at a high speed by lowering the potential produced at a sense amplifier input terminal forming said memory device via a potential lowering means down to a prescribed level and actuating the sense amplifier at its highest point of sensitivity. CONSTITUTION:When data are read out of a memory cell 10, a word line 12 and a decoding line 15 are selected by the outputs of a row decoder 21 and a column decoder 23 respectively. Thus a specific one of cells 10 is selected and therefore the potential of either one of bit lines 11A and 11b connected to cell 10 is lowered slightly less than the power supply potentially VDD. In this connection, the potential lowering circuits 30A and 30B are connected between input lines 18A and 18B of a sense amplifier 17 and a reference potential VSS respectively. In such a constitution, the MOS TR31 forming the circuits 30A and 30B conduct and the potentials of both lines 11A and 11B are lowered than the initial levels. Then the amplifier 17 amplifies the potential difference between both lines 18A and 18B with high sensitivity and delivers outputs from cells 10 at a high speed.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention relates to a semiconductor memory device, particularly a static random access memory, and a method for reading data from memory cells at high speed. Regarding the improvements made.

(Prior Art) FIG. 6 is a block diagram showing a schematic configuration of a conventional static random access memory (hereinafter referred to as 5-RAM). In the figure, IO is a static type memory cell, lIA and 11B are bit lines for exchanging data with each of these memory cells 10, and 12 is a word for simultaneously selecting the plurality of memory cells 10 in the row direction. 13 is a load circuit that charges the bit line 11A and IIB with the power supply potential VDD applied to the power supply terminal 14, 15 is a column decode line that selects the plurality of memory cells 10 in the column direction, and 18A and 18B are bit lines. MOS transistors 18A and 1 for bit line selection that transfer data on lines 11A and IIB to sense amplifier 17;
8B is an input line connected to a pair of input terminals of the sense amplifier 17, and 19 is an output line of the sense amplifier 17.

FIG. 7 is a circuit diagram showing a specific configuration of the load circuit 13 in the conventional 5-RAM. the power supply terminal 14 and a pair of bit lines 11A to which a power supply voltage VDD is applied;
A p-channel MOS transistor 41 is connected between IIB and IIB.
．． 42 are inserted between their sources and drains. Each gate of the transistors 41 and 42 has a reference potential (
vss, ground potential), and both transistors 41
．． 42 is always in a conductive state.

FIG. 8 is a circuit diagram showing a specific configuration of each memory cell 10 in the conventional S-RAM. That is,
51 and 52 are n-channel MOS transistors for transfer gates, and 53 and 54 are n-channel MOS transistors for driving.
Transistors 55 and 56 are high resistance loads.

One end of each of the transfer gate MoS transistors 51 and 52 is connected to a pair of bit lines 11A and IIB, respectively, and the gates are commonly connected to the word line 12. The sources of the drive MOS transistors 53 and 54 are commonly connected to the reference potential VSS, the gates and drains are cross-connected, and each drain is connected to the other end of the transfer gate MoS transistor 5L 52. It is connected. One end of each of the load high resistances 55 and 56 is connected to the drain of each of the MOS transistors 58 and 54, and the other end is commonly connected to the power supply terminal 14. Here, the transistor 53 and the high resistance 55 and the transistor 54 and the high resistance 56 each constitute an inverter, and by interconnecting the human outputs of these two inverters, a flip-flop that statically stores 1-bit data is created. The circuit is configured.

Figure 9 shows the sense amplifier 1 in the conventional 5-RAM mentioned above.
FIG. 7 is a circuit diagram showing a specific configuration of No. 7; This sense amplifier is generally configured as shown in the figure in order to amplify a minute potential difference generated between a pair of bit lines at high speed.

That is, p-channel MOS transistors 61 and 6
2. Their respective sources are commonly connected to the power supply terminal 14, and the gates of both transistors 61 and 62 are commonly connected,
This gate common connection point is connected to the drain of the transistor 61.

An n-channel MOS is connected to the drain of the transistor 61.
The drain of transistor 63 is connected, and the source of transistor 63 is connected to reference potential VSS. Similarly, the drain of an n-channel MOS transistor 84 is connected to the drain of the transistor 62, and the source of this transistor 64 is connected to the reference potential VSS. Then, the gates of both transistors 63 and 64 are connected to the input line 18.
Connect to A and 18B respectively. The amplified data is then output from the common drain of transistors 62 and 64. Such a sense amplifier is generally called a current mirror load type sense amplifier, and is widely used because of its high output driving ability.

In the 5-RAM with such a configuration, the memory cell lO
When data is written to, a specific word line 12 and column decode line 15 are selected by an address input, a row decoder, and a column decoder (not shown), and one specific memory cell 1o is selected. Subsequently, write data from a write circuit (not shown) is sent to the input line 18A,
18B.

At this time, this write data is supplied to the bit lines 11A and IIB via the pair of MOS transistors IBA and 113B selected by the column decode line 15, so that one of the bit lines 11A%IIB becomes "H level". Then, the other one is set to 1L'' level. After this,
bit line 1 for preselected memory cell o
Data is written according to the potentials of 1A and IIB.

On the other hand, in a read operation, similarly to a write operation, a specific memory cell 10 is selected, and the bit line 11 is changed depending on the data read from the selected memory cell 10.
The potential of ASIIB changes. This potential change is transmitted to the input lines 18A and 18B of the sense amplifier 17. Thereafter, the sense amplifier 17 amplifies this potential difference and outputs data corresponding to the read data of the memory cell 10 from the output terminal 19. This data is output to the outside through a data output circuit (not shown).

By the way, the power supply voltage VDD normally used in the 5-RAM is +5V. However, recently, in order to reduce the size and weight of systems using 5-RAM, battery operation is increasingly required. For example, in order to guarantee 3V battery operation, the MOS transistor 41.4 used in the load circuit 13 shown in FIG.
2 has no choice but to use a p-channel one. That is, instead of a p-channel MOS transistor, an n
If you use the channel one, bit line 11A111
The potential of B is lowered from the power supply voltage +3V to a potential lower by the threshold voltage of the n-channel MOS transistor taking into account the back gate effect. That is, bit lines 11A, II
The potential of B does not rise above +1.5V, for example. At such a potential, data cannot be written or read correctly.

On the other hand, if p-channel MOS transistors are used as the MOS transistors 41 and 42, no voltage drop occurs in the load circuit 13 because the threshold voltage of the p-channel MOS transistor is negative. Therefore, bit line 11
The potential of either A or LIB rises to the power supply voltage +3V, allowing correct data writing and reading.

By the way, conventionally, p-channel MOS and transistors are used as loads for the bit lines 11A and IIB, so when read data from the memory cell 10 is output to the bit lines 11A and IIB, the potential thereof is different from the power supply voltage. It only decreases by a small amount.

The reason for this is that the size of the driving MOS transistors 53 and 54 constituting the memory cell IO is limited and cannot be increased unnecessarily.

Therefore, the bit line potential that drops to the "L# level" drops only slightly from the power supply voltage. For example, when the power supply voltage is +5V, the potential of one bit line becomes +5V, and the potential of the other bit line becomes +4. 5 V.The sense amplifier 17 needs to amplify this small potential difference at high speed.However, the sense amplifier with the configuration shown in FIG. It is designed so that its sensitivity is highest at the input potential.For this reason, in conventional 5-RAMs, the bit line potential changes around the power supply voltage, making it possible to amplify the bit line potential difference at high speed. First, it has the disadvantage that data reading cannot be performed at high speed.

(Problems to be Solved by the Invention) As described above, in the conventional memory device, there is a problem that data reading cannot be performed at high speed because the input potential of the sense amplifier cannot be lowered.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to provide a static semiconductor memory that can operate stably even at a power supply voltage lower than the normal voltage and can operate at high speed even at the normal power supply voltage. The goal is to provide equipment.

[Structure of the Invention] (Means for Solving the Problems) A static type semiconductor memory device of the present invention transmits and receives data between a plurality of static type memory cells for data storage and each of the above-mentioned memory cells. A bit line, a load circuit connected to the bit line, a sense amplifier that amplifies the potential generated on the bit line when reading data from the memory cell, and a potential generated at the input terminal of the sense amplifier at a predetermined potential. and a potential lowering means for lowering the potential by the same amount.

(Function) In the static semiconductor memory device of the present invention, the potential generated at the input terminal of the sense amplifier is lowered by a predetermined potential using the potential lowering means, so that the sense amplifier operates at the highest sensitivity. .

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a static semiconductor memory device according to the present invention. In the figure, 10 is a static type memory cell, 11A and IIB are bit lines for exchanging data with each of these memory cells 10, and 12 is a word for simultaneously selecting the plurality of memory cells 10 in the row direction. line, 13 is the bit line 11A,
A load circuit that charges IIB with the power supply voltage VDD applied to the power supply terminal 14, 15 a column decode line that selects the plurality of memory cells 10 in the column direction, 16A and 18B
The data on bit lines 11A and 11B are sent to sense amplifier 1.
MOS transistor for bit line selection to be transferred to 7, 1
8A and 18B are input lines connected to a pair of input terminals of the sense amplifier 17, 19 is an output line of the sense amplifier 17, 20 is a row address buffer, and 21 is connected to the word line according to the output of the row address buffer 20. 22 is a column address buffer; 23 is a column decoder that selects and drives the column decode line 15 according to the output of the column address buffer 22; 24 is read data output from the sense amplifier 17; and an I10 buffer for temporarily storing write data supplied from the outside; 25 is this I10 buffer;
This write circuit is supplied with the write data stored in the buffer 24 and sets the potentials of the input lines 18A and 18B of the sense amplifier 17 according to the write data when writing data.

In this embodiment, furthermore, potential lowering circuits 30A and 30B are connected between the pair of input lines 18A and 18B of the sense amplifier 17 and the reference potential VSS, respectively. In the same potential lowering circuit 30, there is an n-channel MO8.
A transistor 31 is provided, the source of which is connected to the reference potential VSS, and the drain and gate of which are commonly connected to the input line 18.

The specific circuit configurations of the load circuit 13, memory cell 10, and sense amplifier 17 in this embodiment device are the same as those shown in FIGS. 7, 8, and 9.

In such a configuration, when reading data from the memory cell 10, a specific word line 12 is selected by the output of the row decoder 21, and a specific column decode line 15 is selected by the output of the column decoder 23. memory cells 10 are selected.

Here, all the bit lines 11A and ILB are connected to the seventh
It is charged to the power supply potential VDD by p-channel MOS transistors 41 and 42 in the load circuit 13 shown in the concrete circuit of the figure. When one memory cell 10 is selected in this state, the bit line 1 to which this cell is connected is selected according to the data read from the selected memory cell.
The potentials of 1A and IIB change. At this time, the potential of either bit line ILA or IIB is the power supply potential VD.
Although it does not change from D, the other potential slightly decreases from the power supply potential VDD in accordance with the read data. Here, the input of sense amplifier 17! Potential lowering circuits 30A and 30 are provided between each of 18A and 18B and the base 4M position VSS.
B is connected. Each of these potential lowering circuits 30A,
In 30B, when the drain and gate potentials of the n-channel MOS transistor 31 become equal to or higher than the sum of the reference potential VSS and the threshold voltage of this transistor 31, this transistor 31 becomes conductive and connects each of the input lines 18A and 18B to the reference potential VSS. A current path is formed between the two. Therefore, when reading data, a specific column decode line 15 is selected by the output of the column decoder 23, a pair of transistors 18A and 18B are turned on, and the bit line 11A is turned on.
, IIB and input lines 18A and 18B are transistors I
When connected through bit lines 6A and I13B, the potential of each bit line 11A and IIB from which data is read is lowered from the initial potential. In other words, human force line 18A
, 18B are both lowered from the potential at the bit line 11A111B.
By setting this ratio, the input potential after the potential decrease can be set to a potential near which the sense amplifier 17 is most sensitive. For example, potential reduction circuit 30A1
When 30B is not provided, the “L” level potential of bit line 11A and IIB after data reading is +5V,
If the "0" level potential is +4.5V, when the potential lowering circuits 30A and 30B are provided, these potentials are lowered by, for example, 2V to +3V.

It can be set to 12.5V. Such an input potential almost coincides with an input potential near +2.5V, at which the sense amplifier 17 has the highest sensitivity.

Therefore, after this, the sense amplifier 17 inputs the input line 18A11.
The potential difference between gB is amplified with high sensitivity, and the data stored in the memory cell 10 is output from the output terminal 19 at high speed.

Further, this read data is output to the outside via the I10 buffer 24.

In this way, in the device of the above embodiment, the load circuit 13 is constituted by an n-channel MOS transistor that does not cause a voltage drop due to the threshold voltage, so that the bit lines 11A, LI
The potential of B rises to power supply voltage VDD. Therefore, stable operation can be achieved even at a low power supply voltage.

Furthermore, by providing the potential reduction circuit 30, the input potential can be set to a potential near which the sense amplifier 17 has the highest sensitivity, so data can be read out at high speed even when operating at a normal high power supply voltage. be able to.

FIGS. 2 to 4 are circuit diagrams showing the configuration of a potential lowering circuit 30 used in a memory device according to another embodiment of the present invention.

In the potential lowering circuit 30 used in the embodiment shown in FIG. 2, instead of connecting the gate of the n-channel MOS transistor 31 to the input line 18 of the sense amplifier 17,
4, always regardless of the potential of the human power line 18.
It is designed to conduct electricity.

In the potential lowering circuit 30 used in the embodiment shown in FIG.
A channel MOS transistor 32 is used. In this case, the gate of this transistor 32 is connected to the reference potential VSS.

In the potential lowering circuit 30 used in the embodiment shown in FIG. 4, a resistor 33 is used in place of the n-channel MOS transistor 31.

By the way, in each of the embodiments shown in FIGS. 1 to 4, the input line 1 is
The potential of either one of 8A and 18B is set to "H" level, and the other is set to "L" level.

Then, since the potential lowering circuit 30 is provided, a current flows from the input line 18 which is set to the "H" level potential by the write circuit 25 via the potential lowering circuit 3D. This leads to an increase in power consumption when writing data.

FIG. 5 is a block diagram showing the configuration of still another embodiment of the present invention, which is designed to prevent the increase in power consumption during data writing as described above.

In this embodiment device, the potential lowering circuits 30A, 30B
A write enable signal WE is supplied to the gate of an n-channel MOS transistor 31 in the transistor 31, and conduction of the transistor 31 is controlled based on this signal WE. Here, the write enable signal WE is a signal that is activated (set to "L" level) only when writing data, and although not shown, the operations of the write circuit 25 and the like are controlled by this signal WE.

In this embodiment, transistor 31 is rendered conductive only when signal WE is inactive, that is, when reading data. Therefore, when writing data when signal WE is active, input line 1
A current path from 8A and 18B to the reference potential VSS is not generated, and wasteful power consumption can be suppressed. Note that in this embodiment, a p-channel MOS transistor 31 is used instead of the n-channel MOS transistor 31.
Channel MOS transistors can also be used. In that case, the signal WE is supplied to the gate of this p-channel MOS transistor.

In the above embodiment, the memory cell consists of four transistors and two transistors each using a high resistance as a load, as shown in FIG.
Although the case of a resistor configuration has been described, a six-transistor configuration using transistors instead of a high resistance load may also be used.

[Effects of the Invention] As explained above, the static semiconductor memory device of the present invention has the advantage of operating stably even at a power supply voltage lower than the normal voltage and operating at high speed even at the normal power supply voltage. Furthermore, in this type of memory device, the bit line potential and signal amplitude settings have an important relationship with reducing the delay time from the memory cell to the sense amplifier output. Conventionally, the bit line potential and signal amplitude can only be set using a load circuit, but in the memory device of the present invention, this can also be done using potential lowering means, which has the effect of increasing the degree of freedom in design. Obtainable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
2 to 4 are circuit diagrams showing the configuration of main parts of other embodiments of the present invention, FIG. 5 is a block diagram showing the configuration of still another embodiment of the invention, and FIG. 6 is a conventional circuit diagram. A block diagram showing the configuration of the device, and FIGS. 7 to 9 are circuit diagrams specifically showing a part of the conventional device and each of the embodiments described above, respectively. 10...Memory cell, IIA, IIB...Bit line, 12A. 12B...Word line, 13...Load circuit, 14...
・Power terminal, 15... Column decode line, 16A,
16B...MOS transistor for bit line selection, 1
7...Sense amplifier, 18A, 18B...Input line, 19...Output line, 2o...Row address buffer, 21...Row decoder, 22...Column address buffer, 23... Column decoder, 24...I1
0 buffer, 25... writing circuit, 3o... potential lowering circuit, 31... n channel MOS transistor,
32...n-channel MOS transistor, 33...
resistance. Applicant's representative Patent attorney Takehiko Suzue Figure 2 Figure 3 Figure 4

Claims (7)

[Claims] (1) A plurality of static memory cells for data storage, a bit line for exchanging data with each of the memory cells, a load circuit connected to the bit line, and reading data from the memory cell. A static semiconductor memory device comprising: a sense amplifier that amplifies the potential generated on the bit line; and potential lowering means that lowers the potential generated at the input terminal of the sense amplifier by a predetermined potential. (2) Claim 1, wherein the potential lowering means is constituted by an n-channel MOS transistor whose gate and drain are connected, and whose gate and drain are connected and which are connected between the input terminal of the sense amplifier and a reference potential. static semiconductor memory device. (3) Claim 1, wherein the potential lowering means is constituted by an n-channel MOS transistor whose gate is connected to a predetermined potential and which is connected between the input terminal of the sense amplifier and a reference potential. static semiconductor memory device. (4) According to claim 1, wherein the potential lowering means is constituted by a p-channel MOS transistor whose gate and drain are connected, and which is connected between the input terminal of the sense amplifier and a reference potential. static semiconductor memory device. (5) The static semiconductor memory device according to claim 1, wherein the potential lowering means is constituted by a resistor connected between the input terminal of the sense amplifier and a reference potential. (6) The potential lowering means is connected between the input terminal of the sense amplifier and a reference potential, and is conductive only when data is read in the memory cell.
Claim 1 consisting of OS transistors
2. The static semiconductor memory device described in 2. (7) The potential lowering means is connected between the input terminal of the sense amplifier and a reference potential, and is conductive only when data is read in the memory cell.
Claim 1 consisting of OS transistors
2. The static semiconductor memory device described in 2.