JPS6043294A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve a sense speed and sense sensitivity in long-cycle operation by providing a high-resistance load between a couple of data lines as input lines to a sense amplifier and a grounded power source side. CONSTITUTION:For example, all column selection parts 11 connected to columns are in an off state. A data line DL is connected to the connection point between a load transistor (TR) Q1 provided in series between a positive power source VCC and the ground potential, and the high-resistance load R1, so its potential varies gradually to the optential VCC-VTHP (VTHP: threshold voltage of load p channel MOSTRs Q1 and Q2) obtained by dividing the source voltage VCC through said load TRQ1 and high-resistance load R1. Similarly, the potential of a data line DL' also varies gradually to VCC-VTHP. Therefore, even when a memory device is put in long-cycle operation, neither of the potentials of the data lines DL and DL' goes up to the source voltage VCC, so a decrease in neither the sensitivity nor sense operation speed of the sense amplifier S/A is caused.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device with increased speed of sensing operation.

[Technical background of the invention and its problems]

FIG. 1 is a diagram illustrating an example of a column sensing method of a conventional semiconductor memory device, where BL and BL indicate a specified memory column (
This is a bit line connected to a column (column). A large number of these columns are formed, and a predetermined column is selected by a column selection unit No. 1 consisting of a transfer gate of a pair of transistors Q3+Q4, which is controlled by a column selection No. 46 CD. The output is output to the data lines DL, DL.

This data 1) I, , DL are sense amplifiers S/A
This is the input line for a pair of differential input terminals. In addition, the column selection Hsl connected to the data Mi DL r DL
When all of i are inactive, data lines DL, D
In order to prevent the potential of L from floating at an intermediate potential, the positive power supply Vcc and the data lines DL and DL are connected.
A pair of load Mis for so-called pull-up between
) transistors Q1 + Q2 are provided.

The darts of this pair of MOS) synristors Ql and Q2 are connected in common, and the common connection point is connected to one of the Iv
I3 connected to the drain of llO3 transistor Ql
``It has become four generations.

Here, the data is DL, DL is from the column (g
Considering the case where the number is input, the data line D
The potential of L and DL is the potential of the above signal and a pair of M for load.
O8) A certain potential is determined by transistors Q1+Q2.

However, if we consider the case where such a circuit is operated in a slow long cycle, during the period from one read operation to the next read operation of this circuit, all the columns from DL to DL are When the hc is cut, at this time, the MO for sol-up
S) Although Lanzostar QisQx is in the OFF state, the data line DL is raised to the positive power supply voltage VCC by a minute current at the subthreshold level.

Pull up the door.

By the way, in general, the differential input type amplifier circuit of the sense amplifier S/A tends to have poor sensing sensitivity and slow sensing speed as the input signal voltage approaches the positive power supply voltage VCC.

Therefore, when the memory device is operated in a fast cycle, the sensing operation speed is significantly reduced because the next signal from the column is input before the data lines DL and DL rise to the voltage of the positive power supply. However, during long cycle operation, once the positive power supply voltage VC
It takes time for the voltage on the data lines DL and DL, which has risen to C, to drop to a voltage at which the sense amplifier S/A can restore sufficient sensing function, and the decrease in sense sensitivity and operation speed are noticeable. there were.

The circuit shown in FIG. 2 shows another example of the conventional semiconductor memory device b'. In this case, column selection section 1
1, the signal from the column is once amplified by the differential amplifier circuit, and the output with width N is sent to the data line DL.
, W. In this column selection section 1, one end is the positive power supply V. A pair of transistors Ql'+ in a current mirror configuration connected to
Q2' is the output load of the differential amplifier circuit, and this pair of transistors Q! 1 connected in series to each of 't (h')
Pair MOS) U/Jister Q3'lQ4' is column selection]
With the transfer dart controlled by the signal CD,
The transistors Qs'+Q6' connected in series to each of these transistors Q3'lQ4' are connected to the bit line B.
This is an amplification transistor to which L and BL are connected.

By the way, when such a column selection section 1 or 1 dynamic amplification circuit is configured, a pair of transistors Ql'l of a current mirror type configuration which becomes a load of the differential amplification circuit r,j: Q2' is the datan DL.

(2) Acts as a load transistor for sol-up.

That is, even in the case of the circuit shown in FIG. 2, the data line DL is closed during long cycle operation.

When all the transfer gates connected to DL are turned off, the load MO8) transistor Q1'.

The drain of Q2', that is, the data lines DL and DL, which are the output lines of the differential amplifier circuit section, are pulled up to the power supply voltage VCC, and the differential amplifier circuit school and sense amplifier S/A are pulled up to the power supply voltage VCC.
The sensitivity of the data line DL is low, and when a signal from the column is input, it takes time for the data line DL to drop.
This caused a decrease in sensing operation speed.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a semiconductor memory device with improved sense speed and sense sensitivity during long cycle operation.

[Summary of the invention]

That is, in the half-quad memory device according to the present invention, a high resistance load is provided between each of a pair of data lines serving as input lines of the sense amplifier and the ground power supply side. Create a potential that is divided between the load MO8) transistor on the positive power supply side and the high resistance load mentioned above on the ground power supply side, and apply this divided potential to the data line so that all columns are connected to the data line during long cycle operation. This prevents the data line from rising to the positive power supply potential when it is disconnected from the power supply.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

The circuit of FIG. 3 corresponds to the circuit of FIG. 1, and is the input of the sense amplifier 7'S/A! Data I5JDL,
Each of DL and positive power supply■. A load MOS transistor Ql-Q2 is connected between the data line DL and the data line DL.
, A large number of columns are connected to the DL via the column selection section 1. Furthermore, these data lines DL and DL have
Unlike the device shown in FIG. 1, resistors R1 and R2 each having one end connected to the ground power supply side are connected.

In the memory device having the above configuration, it is assumed that all column selection units 11 that continue for a long time in a column are turned off. Here, the data line DL is a positive power supply ■. , and the ground potential, and the high resistance load R1 is connected to the connection point between the load transistor Ql and the high resistance load R1, so that its potential gradually decreases to the power supply voltage V. 0 is the load transistor Q
1 and the high resistance load J.
vTHP (However, for VTHP load) p-channel MOS
Tosinjista Q! 1Q2 threshold voltage). Similarly, the potential of the data line DL gradually becomes VCC-VTHP. Therefore, even if the memory device is operated for a long cycle, the potential of the data lines DL and DL will not rise to the power supply voltage VCC, so the sense This does not cause a decrease in the sensitivity of the amplifier S/A or a decrease in the sensing operation speed.

In the circuit shown in FIG. 4, the column selection section 11 has differential amplification (effect) as in the circuit shown in FIG. A resistive load R1wR2 is provided.

In a circuit with such a configuration, when performing a long cycle operation, when the column selection signal CD is used to turn off all the column selection units 1), when Qa'=Q4' is turned off, the case shown in Fig. 3 above occurs. Similarly, data line D
L, DI, potential strip. 0-■, HPl (but VT
HP is a p Bouyanel MOS transistor Q1' for load.
(threshold voltage of lQ2').

Therefore, it is possible to prevent the data lines DL and DL from reaching the power supply voltage Vcc, and in this case as well, the differential amplifier circuit DA-
? It is possible to prevent a decrease in the sensitivity and sensing operation speed of the sense amplifier 7'S/A.

In the devices of the first and second embodiments described above, when performing high-speed operation, signals are frequently input to the data lines DL, DL as in the conventional case, so the potential levels of the data lines DL, DL are as low as the data lines DL, DL, DL. ' of the signal input to DL
1# and ``0# level (in both cases, positive power supply'-voltage V.

However, there are no problems with the sensing sensitivity and sensing operation speed of the sense amplifier S/A or the differential amplifier circuit.

Note that the load transistors Q1 and Q2 provided between each of the data KjJDL+DL and the positive power supply CC may be of the type shown in FIG. Figure 5 (a
) shows transistor QIIQ2 as p-channel M
O8) It is constructed of a runnostar, and its darts are not connected in common but are connected independently to the drains of each transistor t1';e.

In the case shown in FIG. 5(b), the load MO8) runnostars Q, 1, and Q2 are connected to J
The dirt of each transistor is connected to the drain.

What is shown in FIG. 6 is a data line DL of a semiconductor memory device.
, Fig. 6(a) is an example of high resistance loads R1+R2 connected to DL, and Fig. 6(a) uses a polysilicon resistor R as the high resistance load, and Fig. 6(b) shows an example of a normally-off state. 6 (C) is a normally-on n-channel MO3 with small conductance) and a runnostar is shown. Of course, in addition to this, it is also possible to use an S transistor as a normally-off stray channel or a normally-on p-channel transistor with small conductance as a high-resistance load.

Note that the high resistance loads R1 and R2 are the data line DL.

It is necessary to set the resistance (low conductance) to be sufficiently high so as not to affect the signal level when a signal from the column is input to the DL.

Furthermore, in the second embodiment described above, the configuration of the itA selection unit 11 was shown in which one column (or one pair of bit lines BL, BL) is input to one differential amplifier circuit, but this In addition to one differential amplifier circuit, a plurality of power signals may be input to the differential amplifier circuit. In this case as well, the data output DL, DL is achieved by the current mirror type MOS transistor Qt+Q2 in the differential amplifier circuit and the high resistance loads R1, R2 connected to the data edges DL, DL.
The potential of is set. Further, one high resistance load may be provided on one data line, or a plurality of high resistance loads may be provided on one data core. In addition, a high-resistance load is often installed so that a small current flows from the positive power supply to the ground power supply via the load MO8) transistor, and one end of this high-resistance load is not directly connected to the long ground potential source. Tomoyoshi. In other words, a MOS transistor or the like may be provided in series with the sieve resistance load between the data edge DL, DL and the ground power supply.

[Genmei effect]

As described above, according to the present invention, there is no fear that the data line rises to the power supply voltage even during long cycle operation, so the sense sensitivity of the differential amplifier circuit and sense amplifier of the column selection section during long cycle operation is improved. Also, it is possible to provide a semiconductor memory device with improved sensing operation speed.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing the configuration of a conventional semiconductor memory device, FIG. 3 is a circuit 1 showing an embodiment of a semiconductor memory device by Kazuo Kinoe, and FIG. 4 is a circuit diagram showing a semiconductor memory device according to the present invention. A circuit diagram showing another embodiment of the memory device, FIG. 5 is a load MO8 in a semiconductor memory device according to the present invention.
) FIG. 6 is a circuit diagram showing another example of the configuration of a transistor, and FIG. 6 is a circuit diagram showing an example of the configuration of a high resistance load of a semiconductor memory device according to the present invention. BL, BL...Bit line, Q r r Q
2 + Q1'+Q2' - MO8 for load;>y sister, Q3 1'Q4 1Q3', Q4' river transfer gate, Q5', Q6'...'・MO8 for a width) transistor, DA... Differential amplifier circuit, S/A...Sense amplifier, DL, DL...Data, VCC...
Positive power supply, R11R2 high resistance load, 1st column selection section. Applicant's agent, patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 BL Hidden 8L Previous Figure 6 (a) (b) (c) Continued from page 1 0 Inventor Takayasu Sakurai Kawasaki Inventor: Tetsuya Iizuka, Komukai 1 Laboratory, Saiwai-ku, Kawasaki Inventor: Akira Aono, Komukai Tag Co., Ltd., Saiwai-ku, Kawasaki City

Claims (7)

[Claims] (1) A plurality of columns, a column selection section to which the plurality of columns are connected, selects a predetermined one of the columns, and outputs the output to a pair of data rt'J serving as input lines of a sense amplifier; a pair of load MO8) transistors provided between the power source of the 8) and the pair of data lines, and a pair of high resistance loads provided between the other power source and the pair of data lines; A semiconductor memory device comprising: (2) The pair of load MO8) transistors are characterized in that their gates are commonly connected to each other, and the common connection point is directly connected to the drain of one of the load MO8) transistors. A half-quad memory device according to claim 1. (3) The semiconductor memory device according to claim 1, wherein each of the pair of load MO8) transistors is connected to a gate electrode of the transistor. (4) The column selection section has a differential amplifier circuit that amplifies the signal from the column, and has a pair of load MO8s.
) A transistor is provided between one power supply and a pair of data lines as an output load in a differential amplifier circuit.
4ffl A semiconductor memory device according to claim 2. (5) The semiconductor memory device 1a according to any one of claims 1 to 4, wherein the high resistance load is a polysilicon resistor. (6) MOS with the above high resistance load set to off state
) A semiconductor memory device according to any one of claims 1 to 5, characterized in that it is constituted by a transistor. (7) The above-mentioned high-resistance load is an on-state MOS (MOS transistor) with small conductance. Semiconductor memory device.