JPH0636317B2 - Differential amplifier - Google Patents

Description

TECHNICAL FIELD The present invention relates to a differential amplifier, and more particularly to a differential amplifier with reduced power consumption.

[Conventional technology]

FIG. 6 is an electric circuit diagram showing a conventional differential amplifier,
Reference numerals 1 and 2 denote P-channel type MOS transistors (hereinafter referred to as PMOSs) whose sources are connected to the power supply voltage V _CC. The gates of these PMOSs 1 and 2 are grounded and function as loads by utilizing their ON resistances. ing.
The drains of the PMOSs 1 and 2 are connected to the drains of N-channel MOS transistors (hereinafter referred to as NMOS) 3 and 4, and the sources of the NMOSs 3 and 4 are NMOS.
It is grounded via 6. The gates of the NMOSs 3 and 4 are respectively connected to the bit line B and the dummy bits D and B lines of a static memory cell array (not shown), and the common drain of the PMOSs 1 and 2 and the NMOSs 3 and 4 is the output node N ₁ , N ₂ and connected to an output circuit (not shown). The gate of the NMOS 5 is connected to the activation signal terminal of a control circuit (not shown).

The operation of the conventional example having the above configuration will be described with reference to the chart of FIG. 7, assuming that the logic "0" is stored in the accessed cell.

After precharging the bit line B and the dummy bit line DB,
When the accessed cell and the dummy cell are connected to the bit line B and the dummy bit line DB, the voltage of the bit line B gradually drops, but the dummy bit line DB has a power supply voltage of approximately V.
Stay in _CC . Here, when the activation signal SE is applied to the NMOS 5, the NMOSs 3 and 4 are grounded via the NMOS 5, and the voltage difference between the gate and the source of the NMOS 4 is NM.
Since the voltage difference between the gate and the source of OS3 is larger, the channel conductance of NMOS4 is NMOS.
3, the voltage of the output node N ₂ drops rapidly and stabilizes at a voltage determined by the on-resistance ratio of the PMOS2, NMOS4, and 5, but the voltage drop of the bit line B causes the NMOS3 to be turned off. Therefore, the voltage of the output node N ₁ recovers toward the power supply voltage V _CC .
In this way, the voltage difference between the bit line B and the dummy bit line DB is amplified and appears at the output nodes N ₁ and N ₂ , and is sent from the output circuit to an external device such as a microprocessor.

[Problems to be Solved by the Invention]

In the differential amplifier according to the above configuration, after the differential amplification is started, one of the NMOSs 3 and 4 (NMOS 4 if the accessed cell stores the logic “0”) stores the information from the cell. It keeps the ON state until reading is completed,
Since a current path is formed from the power supply voltage V _CC to the ground via the PMOS 2 and the NMOSs 4 and 5, the power supply current flows for a long period of time as shown in FIG. Atsuta

[Means for solving problems]

The differential amplifier of the present invention is a one conductivity type in which a pair of signal lines in which a minute potential difference appears between them, a first output node and a common node are connected, and a gate is connected to one of the pair of signal lines. Second transistor, a third transistor connected between the common node and the first power supply line and receiving an activation signal at its gate, the first output node and the second transistor
A reverse-conductivity-type fourth transistor connected between a power supply line, a reverse-conductivity-type fifth transistor connected between the second output node and the second power supply line, and the pair of signal lines The input is connected to one side and the output is the fifth
A first complementary inverter connected to the gate of the transistor; and a second complementary inverter having an input connected to the other of the pair of signal lines and an output connected to the gate of the fourth transistor. To do.

〔Example〕

FIG. 1 is an electric circuit diagram showing a first embodiment of the present invention,
The same components as those of the conventional example are designated by the same reference numerals, and the description thereof will be omitted.

The gates 11 and 12 have a bit line B and a dummy bit line D.
Complementary MOS inverters (hereinafter referred to as CMOS) respectively connected to B and the common drains N ₃ and N ₄ of the CMOSs 11 and 12 are cross-connected to the gates of the PMOSs 2 and 1. These CMOSs 11 and 12 constitute the closing means 13 as a whole.

The operation of the first embodiment will be described with reference to the chart of FIG. 2 when the cell connected to the bit line B stores the logic "0".

After the precharge, a slight voltage difference occurs between the bit line B connected to the cell and the dummy bit line DB, and when the activation signal SE is applied to the NMOS 5, the NMOS 3,
4 shifts to the ON state, and the voltage of the output node N ₂ is PMO.
S2 is stabilized at a voltage value proportionally divided by the on-resistance ratios of the NMOSs 4 and 5, but the NMOS 3 gradually turns to the off state due to the voltage drop of the bit line B, and the voltage of the output node N ₁ also becomes the power supply voltage V _CC . Trying to get back. Therefore, an output circuit (not shown) outputs a signal representing the logic "0" stored in the accessed cell, based on the voltage difference between output nodes N ₁ and N ₂ .

Here, in the CMOS 12, since the dummy bit line DB remains substantially at the power supply voltage V _CC , the common drain N ₄ becomes the ground potential and the PMOS maintains the ON state, but the CMOS 1
1 is inverted according to the voltage drop of the bit line B, and the voltage of the common drain N ₃ starts to rise. As a result, PMOS2 proceeds toward the off state, the voltage of the common drain _{N 3,} i.e., the difference between the gate voltage and the source voltage _{V CC} of PMOS2 is dividing the threshold value _{V TH} of PMOS2, PMOS2 is turned off . Therefore, the current consumption of the differential amplifier is the third
As shown in the figure, it drastically decreases with the transition of the PMOS 2 to the off state, and becomes “0” with the transition of the NMOS 3 to the off state.

FIG. 4 shows a second embodiment of the present invention. In addition to the configuration of the first embodiment, the PNOS 16 connected between the PMOSs 14 and 15 in parallel with the PMOSs ₁ and ₂ and the output nodes N ₁ and N ₂ is shown.
And each gate of the PMOSs 14 to 16 is connected to the activation signal terminal of the control circuit.

In the second embodiment, when the activation signal SE shifts to the low level before the start of a new read cycle,
The PMOSs 14 to 16 are turned on, and the output node is accurately precharged to an equal voltage (see FIG. 5). Therefore, the amplification operation can be speeded up, and it can be used as a sense amplifier for high speed and low power consumption of a static memory that generates a trigger pulse at the edge of an address signal and resets each part.

〔effect〕

As described above, according to the present invention, the closing means for shifting the load transistor connected to the amplifying transistor maintaining the ON state to the OFF state based on the minute voltage difference is provided. Even after completion, the current path for grounding the power supply current can be gradually removed, and the effect of reducing power consumption can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an electric circuit diagram of a first embodiment of the present invention, FIG. 2 is a timing chart diagram of the first embodiment, and FIG. 3 is a change of power supply current of the first embodiment. The graph shown in FIG. 4 is the second of the present invention.
5 is an electric circuit diagram of the second embodiment, FIG. 6 is an electric circuit diagram of the conventional example, FIG. 7 is a timing chart diagram of the conventional example, and FIG. 8 is a power supply current of the conventional example. It is a graph which shows the change of. B, DB ... Micro voltage source, 1, ... Load transistor, 3, 4 ... Amplifying transistor, 5 ... Activation transistor, 13 ... Closing means.

Claims (1)

[Claims] 1. A first of one conductivity type having a pair of signal lines in which a minute potential difference appears between them, connected between a first output node and a common node, and having a gate connected to one of the pair of signal lines. A transistor, a second transistor of one conductivity type connected between the second output node and the common node and having a gate connected to the other of the pair of signal lines; connected between the common node and the first power supply line A third transistor having a gate that receives an activation signal, a fourth transistor of an opposite conductivity type connected between the first output node and the second power supply line, and a second output node and the second power supply line. A reverse-conductivity-type fifth transistor connected in between,
A first complementary inverter having an input connected to the one of the pair of signal lines and having an output connected to the gate of the fifth transistor, and an input connected to the other of the pair of signal lines and having an output of the fourth pair. A differential amplifier comprising a second complementary inverter connected to the gates of the transistors.