JPS62146487A - Differential amplifier - Google Patents

Abstract

PURPOSE:To remove a current path after completion of differential amplification and to reduce power consumption by transferring a load FET to an off state based on a slight voltage difference. CONSTITUTION:When a cell stores '0', a slight voltage difference is generated between a bit line B and a dummy bit line DB after precharging, and when an activating signal SE is applied to an NMOSFET 5, FETs 3, 4 are turned on, the voltage of an output node N2 is proportionally divided by the ON resistance ratio of a PMOSFET 2 and FETs 4, 5, the FET 3 is turned off, and the voltage of the output node N1 is restored. Thereby, the output circuit outputs a signal '0' stored based on the voltage difference between the N1 and N2. At that time, a CMOSFET 11 is inverted in accordance with the voltage drop of the line B, the voltage of a common drain N3 is boosted, the FET 2 is transferred to OFF, and when the difference between the gate voltage and the VCC becomes a threshold VTH or less, the FET 2 is completely turned off.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a differential amplifier, and more particularly to a differential amplifier with reduced power consumption.

[Conventional technology]

Figure 6 is an electrical circuit diagram showing a conventional differential amplifier.
, 2 is a P-channel MOS transistor (hereinafter referred to as PMO8) whose source is connected to the power supply voltage ■cc.
The gates of these PMOs 81 and 2 are grounded, and function as a load using their on-resistances. P.M.O.
The drains of 8I, 2 are connected to the drains of N-channel MOS transistors (hereinafter referred to as NMO8) 3, 4, and the sources of NMO83, 4 are grounded via NMO86. The gates of NMO83 and NMO4 are connected to bit line B of a static type memory cell array (not shown).
and the dummy bit D and B lines respectively,
The common drain of PMO8I,2 and NMO83,4 is output node N1. It functions as N2 and is connected to an output circuit (not shown). Further, the gate of the NMO 85 is connected to an activation signal terminal of a control circuit (not shown).

The operation of the conventional example of the above configuration will be explained with reference to the chart of FIG. 7, assuming that the accessed cell stores a logic "'0".

After precharging bit line B and dummy bit line DB,
When the accessed cell and the dummy cell are connected to the bit line B and the dummy bit line DB, the voltage of the bit line B gradually drops, but the dummy bit line DB is connected to the power supply voltage path V.
Stay on CC. Here, when the activation signal SE is applied to the NMO 85, the NMOs 83 and 4 are grounded via the NMO 85, and the voltage difference between the gate and source of the NMO 84 becomes
Since the voltage difference between the gate and source of 83 becomes larger,
The channel conductance of NMOS 4 is NMO83
Since the voltage at the output node N2 decreases rapidly and stabilizes at a voltage determined by the on-resistance ratio of PMO82, NMO84, and 5, pNMO83 shifts to the off state due to the voltage drop on bit line B. Therefore, the voltage at the output node N1 recovers toward the power supply voltage VCC. In this way, the voltage difference between the bit line B and the dummy bit line DB is amplified and appears at the output nodes N1 and N2, and is sent from the output circuit to an external device, such as a microprocessor.

[Problem to be solved by the invention]

In the differential amplifier having the above configuration, after the start of differential amplification, one of the NMOs 83 and 4 (NMO 84 if the accessed cell stores logic ""O")
The on state is maintained until the reading of information from the cell is completed, and the PMO 82 and NMO 84, 5 are connected to the power supply voltage VCC.
Since a current path is formed to ground through the power supply, the power supply current flows for a long period of time as shown in FIG. 8, resulting in an increase in power consumption.

[Means for solving problems]

In view of the above problems, the present invention provides a closing means for shifting a load transistor connected to an amplification transistor that maintains an on state to an off state based on a minute voltage difference after a certain period of time has passed after activation of the amplification transistor. The gist is that the current path formed between the power supply voltage and the ground voltage is interrupted.

〔Example〕

FIG. 1 is an electrical circuit diagram showing a first embodiment of the present invention,
Components that are the same as those of the conventional example are given the same reference numerals, and explanations thereof will be omitted.

11.12, the gate is connected to bit line B and dummy bit line D
Complementary MOS inverters (hereinafter referred to as CMO8) connected to B and CMO8II, respectively.

12 common drains N3. N4 is cross-connected to the gate of PMO 82,1. These CMO8II.

12 constitutes a closing means 13 as a whole.

The operation of the first embodiment will be explained with reference to the chart of FIG. 2, assuming that the cell connected to the bit line B stores the logic "On".

After precharging, a slight voltage difference occurs between the bit line B connected to the cell and the dummy bit line DB, and when the activation signal SR is applied to the NMO85, the NMO83,
4 transitions to the on state, and the voltage at the output node N2 is PMO
82 and NMO84, the voltage stabilizes at a voltage proportionally divided by the on-resistance ratio of 5, but NMO83 gradually turns to the off state as the voltage of bit line B drops, and the voltage of output node N1 also returns to the power supply voltage VCC. shall be. Therefore, the output circuit (not shown) outputs the logic 'O' stored in the accessed cell based on the voltage difference of the output node Nil N2.
Outputs a signal representing #.

Here, since the dummy bit line 1)B of 0MO812 remains at approximately the power supply voltage VCC, the common drain N4 is not at ground potential, and although PMO8 maintains the on state, 0MO8
11 is inverted as the voltage on bit line B drops, and the voltage on common drain N3 begins to rise.

As a result, the PMO 82 moves toward the off state, and the voltage at the common drain N3, that is, the difference between the gate voltage of the PMO 82 and the power supply voltage VCC, becomes the threshold value VTR of the PMO 82.
When the PMO 82 is divided, the PMO 82 is turned off. therefore,
The current consumption of the differential amplifier is P as shown in Figure 3.
With the transition of MO82 to the off state, it decreases sharply, and NMO83
The transition to the off state causes the signal to become "0".

FIG. 4 shows a second embodiment of the present invention. In addition to the configuration of sb and the first embodiment, PMOS14.15 is connected in parallel to PMO8I, 2, and output nodes Nl and N2 are connected *PMO816.
t-L, PMO814-16 (7) Each gate is connected to the activation signal terminal of the control circuit.

In the second embodiment, when the activation signal SE goes low prior to starting a new read cycle,
When PMOs 814-16 are turned on, the output nodes are accurately precharged to equal voltages (see FIG. 5). Therefore, the speed of the amplification operation can be increased, and the sense amplifier can be used as a high-speed, low-power sense amplifier for a static memory that generates a trigger pulse at the edge of an address signal and resets each part.

〔effect〕

As explained above, according to the present invention, a closing means is provided to shift the load transistor connected to the amplification transistor that maintains the on state to the off state based on a minute voltage difference. Even after the dynamic amplification is completed, the current path for grounding the power supply current can be interrupted, resulting in the effect that power consumption can be reduced.

[Brief explanation of drawings]

Fig. 1 is an electric circuit diagram of the first embodiment of the present invention, Fig. 2 is a timing chart of the first embodiment, Fig. 3 is a graph showing changes in power supply current of the first embodiment, and Fig. 4 is a graph showing changes in power supply current of the first embodiment. Second aspect of the present invention
The electrical circuit diagram of the embodiment, Fig. 5 is the timing chart of the second embodiment, Fig. 6 is the electrical circuit diagram of the conventional example, Fig. 7 is the timing chart of the conventional example, and Fig. 8 is the power supply current of the conventional example. It is a graph showing changes in. B, DB...Minor voltage source, 1,2...
Load transistor, 3, 4...Amplification transistor, 5...Activation transistor, 13...
...is a closing means. Agent Patent Attorney Shinka Uchihara 1st and 2nd θvr￥f times B DB Kin Otsu V

Claims (1)

[Claims] A pair of minute voltage difference sources, two sets of load transistors and amplification transistors arranged in series between the power supply voltage and the ground voltage, and between the two amplification transistors and the ground voltage. Activation of the amplification transistor in a differential amplifier having an activation transistor provided in the amplification transistor for activating the amplification transistor, and a pair of micro voltage sources connected to the gates of the two amplification transistors, respectively. 1. A differential amplifier comprising: a closing means for switching a load transistor connected to an amplifying transistor that is maintained in an on state to an off state based on a minute voltage difference after a certain period of time has elapsed.