JPS6358698A - Static semiconductor memory device - Google Patents

Abstract

PURPOSE:To actuate a semiconductor memory device stably and at a high speed despite the power supply voltage lower than a normal level, by lowering the potential bit lines forming the semiconductor memory device less than a prescribed level via a potential lowering means and actuating a sense amplifier at the highest level of its sensitivity. CONSTITUTION:When data are read out of a memory cell 10, the specific column decoder lines 15 are selected by the outputs of a row decoder 21 and a column decoder 23 respectively. Then the specific one of cells 10 is selected. Thus the potential of either one of bit lines 11A and 11B is lowered slightly less than the power supply voltage VDD. Then MOS transistors 30A and 30B connected to both lines 11A and 11B conduct. Therefore a current path is produced between both lines 11A and 11B and a reference potential VSS respectively and the potentials of those bit lines are lowered less then the initial levels. As a result, a sense amplifier 17 has a potential close to the highest level of its sensitivity and the potential difference between input lines 18A and 18B is amplified with high sensitivity.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device, particularly a static random access memory, which can read data from memory cells at high speed. Regarding the improvements made.

(Prior Art) FIG. 4 is a block diagram showing a schematic configuration of a conventional static random access memory (hereinafter referred to as 5-RAM). In the figure, 1o is a static type memory cell, 11A and 113 are bit lines for exchanging data with each of these memory cells 10, and 12 is a word for simultaneously selecting the plurality of memory cells 10 in the row direction. Line, 13 connects line 11A, 11[3 to the above-mentioned pin 1
15 is a column decode line that selects the plurality of memory cells 10 in the column direction. 16A and 16B are a sense amplifier 17 that charges the data on the bit lines 11A and 11B. MOS transistors 18A and 1 for bit line selection to transfer data to
8B is an input line connected to a pair of input terminals of the sense amplifier 17, and 19 is an output line of the sense amplifier 17.

Figure 5 shows the load circuit 1 in the conventional S-RAM mentioned above.
FIG. 3 is a circuit diagram showing a specific configuration of No. 3; N'FA voltage V
Front distribution power supply terminal 14 to which oo is applied and a pair of bits $9
Between the sources and drains of n-channel MOS transistors 41 and 42 are inserted between 11A and 11B. Each gate of the transistors 41 and 42 is connected to a reference potential (Vss, ground potential),
Both transistors 41 and 42 are always in a conductive state.

FIG. 6 is a circuit diagram showing a specific configuration of each memory cell 10 in the conventional S-RAM. That is,
51 and 52 are n-channel MOS transistors for transfer gates, and 53 and 54 are n-channel MOS transistors for driving.
Transistors 55 and 56 are high resistance loads.

One end of each of the transfer gate MOS transistors 51 and 52 is connected to a pair of bit lines 11A and 11B, respectively, and the gates are commonly connected to the word line 12. The sources of the drive MOS transistors 53 and 54 are commonly connected to the reference potential VSs, the gates and drains are cross-connected, and each train is connected to the other end of the transfer gate MOS transistors 51 and 52. each connected. One end of each of the load high resistances 55 and 56 is connected to the drain of each of the MOS transistors 53 and 54, and the other end is commonly connected to the power supply terminal 14. Here, the transistor 53 and the high resistance 55 and the transistor 54 and the high resistance 56 each constitute an inverter, and by interconnecting the input and output of these two inverters, 1 bit of data is statically stored. A flip-flop circuit is configured.

Figure 7 shows the sense amplifier 1 in the conventional 5-RAM mentioned above.
FIG. 7 is a circuit diagram showing a specific configuration of No. 7; This sense amplifier is generally configured as shown in the figure in order to amplify a minute potential difference generated between a pair of bit lines at high speed.

That is, n-channel MOS transistors 61 and 6
2. Their respective sources are commonly connected to the power supply terminal 14, and the gates of both transistors 61 and 62 are commonly connected,
This gate common connection point is connected to the drain of the transistor 61.

An n-channel MOS is connected to the drain of the transistor 61.
The drain of transistor 63 is connected, and the source of transistor 63 is connected to reference potential VSS. Similarly, a train of an n-channel MOS transistor 64 is connected to the drain of the transistor 62, and the source of this transistor 64 is connected to the reference potential VSS. Then, the gates of both transistors 63 and 64 are connected to the input line 18.
Connect to A and 18B respectively. The amplified data is then output from the common drain of transistors 62 and 64. Such a sense amplifier is generally called a current mirror load type sense amplifier, and is widely used because of its high output driving ability.

In the 5-RAM with such a configuration, the memory cell 10
When writing data to, a specific word line 12 and column decode line 15 are selected by an address input, a row decoder, and a column decoder (not shown), and one specific memory cell 10 is selected. Subsequently, write data from a write circuit (not shown) is sent to the input line 18A,
18B.

At this time, this write data is supplied to the bit lines 11A and 11B via the pair of MOS transistors 16A and 16B selected by the column decode line 15, so that one of the bit lines +1A and 11B is set to II HI.
One signal is set to T level, and the other is set to "'L" level. Thereafter, data is stored in the preselected memory cell 1o according to the potentials of the bit lines 11A and 11B.

On the other hand, in a read operation, similarly to a write operation, a specific memory cell 10 is selected, and the bit line 11 is changed depending on the data read from the selected memory cell 10.
The potential of A, 1113 changes. This potential change is transmitted to the inputs 118A and 18[3 of the sense amplifier 17. Thereafter, the sense amplifier 17 amplifies this potential difference and outputs data corresponding to the read data of the memory cell 10 from the output terminal 19. This data is output to the outside through a data output circuit (not shown).

By the way, the N applied voltage VDD normally used in the 5-RAM is +5V. However, recently, in order to reduce the size and weight of systems using 5-RAM, battery operation is increasingly required. For example, in order to guarantee 3V battery operation, the MOS transistor 41.4 used in the load circuit 13 shown in FIG.
2 has no choice but to use a p-channel one. That is, instead of a p-channel MOS transistor, an n
If you use channel ones, bit lines 11A, 11
The potential of B is lowered from the power supply voltage +3V to a potential lower by the threshold voltage of the n-channel to 10S transistor, taking into account the back gate effect. That is, bit line 11A111
The potential of No. 3 does not rise above +1.5V, for example. At such a potential, data cannot be written or read correctly.

On the other hand, if p-channel MOS transistors are used as the MOS transistors 41 and 42, no voltage drop occurs in the load circuit 13 because the threshold voltage of the p-channel MO8 transistor is negative.

Therefore, the potential of either one of the bit lines 11A and 11B rises to the voltage a +3V, allowing correct data writing and reading.

By the way, conventionally, a ρ channel MOS transistor is used as a load for the bit lines 11A and 11B, so when the read data from the memory cell 10 is output to the bit lines 11A and 11B, the potential is not lower than the power supply voltage. It only decreases.

The reason for this is that the size of the driving MOS transistors 53 and 54 constituting the memory cell 10 is limited and cannot be increased unnecessarily. Therefore, rr
The bit line potential that drops to the L11 level drops only slightly from the power supply voltage. For example, if the power supply voltage is +5
In case (2), the potential of one bit line becomes +5V, and the potential of the other bit line becomes about +4.5V. sense amplifier 1
7 needs to amplify this slight potential difference at high speed.

However, the sense amplifier having the configuration shown in FIG. 7 is designed so that its sensitivity is highest at an input potential near a substantially intermediate potential between the power supply voltage Voo and the reference potential V99.

Therefore, in the conventional 5-RAM, since the bit line potential changes near the power supply voltage, the bit line potential difference cannot be amplified at high speed, and data reading cannot be performed at high speed.

(Problems to be Solved by the Invention) As described above, in the conventional memory device, there is a problem that data reading cannot be performed at high speed because the input potential of the sense amplifier cannot be lowered.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to provide a static semiconductor memory that can operate stably even at a power supply voltage lower than the normal voltage and can operate at high speed even at the normal power supply voltage. The goal is to provide equipment.

[Structure of the Invention (Means for Solving Problems)] A static semiconductor memory device of the present invention has a plurality of static memory cells for data storage and data transfer between the above-mentioned memory cells. a load circuit connected to the bit line, a sense amplifier that amplifies the potential generated on the bit line when reading data from the memory cell, and a sense amplifier that reduces the potential generated on the bit line by a predetermined potential. and potential lowering means.

(Function) In the static semiconductor memory device of the present invention, the potential lowering means lowers the potential of the bit line by a predetermined potential, so that the sense amplifier operates at the highest sensitivity.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a static semiconductor memory device according to the present invention. In the figure, 10 is a static type memory cell, 11A and 113 are bit lines for exchanging data with each of these memory cells 10, and 12 is a word for simultaneously selecting the plurality of memory cells 10 in the row direction. line, 13 is the bit line 11△
, 1iB with the power supply voltage Voo applied to the power supply terminal 14, 15 is a column decode line that selects the plurality of memory cells 10 in the column direction, 16Δ and 16[
3 is a MOS transistor for bit line selection that transfers data on the bit lines 11A and 11B to the sense amplifier 17;
18A and 18B are input lines connected to a pair of input terminals of the sense amplifier 17, 19 is an output line of the sense amplifier 17, 20 is a row address buffer, and 21 is connected to the word line according to the output of the row address buffer 20. 22 is a column address buffer; 23 is a column decoder that selects and drives the column decode line 15 according to the output of the column address buffer 22; 24 is read data output from the sense amplifier 17; and an I10 buffer for temporarily storing write data supplied from the outside, 25 is this ■/
- The old write data stored in the buffer 24 is supplied, and the input lines 18A and 18B of the sense amplifier 17 are connected according to the write data when writing data.
This is a write circuit that sets the potential of .

This embodiment device further includes a p-channel MOS transistor 3 between each bit line 11A and the reference potential VSS.
The source and drain of the OA are inserted between each bit line 11B and the reference potential Vss, and the source and drain of the p-channel N10S transistor 303 are inserted, respectively. The gates of each pair of transistors 30A and 303 are commonly connected to the corresponding column decode line 15.

The specific circuit configurations of the load circuit 13, memory cell 10, and sense amplifier 17 in this embodiment are the same as those shown in FIGS. 5, 6, and 7.

In such a configuration, when reading data from the memory cell 10, a specific word line 12 is selected by the output of the row decoder 21, and a specific column decode line 15 is selected by the output of the column decoder 23. memory cells 10 are selected.

Here, all the bit lines 11A and 11B are connected in advance to the p-channel M in the load circuit 13 shown in the concrete circuit of FIG.
N'FA potential VDD by OS transistors 41 and 42
is being charged. When one memory cell 1o is selected in this state, the potentials of the bit lines 11A and 11B to which this cell is connected change depending on the data read from the selected memory cell. That is, the potential of either one of the bit lines 11A, 11B is the power supply potential Voo.
However, the other potential slightly decreases from the power supply potential Voo in accordance with the read data. Further, when reading this data, a specific column decode line 15 is selected by the output of the column decoder 23, and a pair of transistors 16A and 16B are made conductive, so that the bit lines 11A and 11
B and input lines 18A and 18B are transistors 16A11
6[3, when connected through bit lines 11A, 11
The p-channel MO8l transistors 30A and 30B connected to B become conductive. Both transistors above 3OA
, 30B conduct, a current path is formed between each of the bit lines 11A, 11B and the reference potential Vss.

Therefore, data is read out from the bit lines 11A and 11B selected by the column decode line 15.
Each potential decreases from the initial potential. This potential drop is done according to the dimensional ratio of the transistors 41 and 42 in the load circuit 13 and the transistor 30, as well as the channel length and channel width, and by setting this ratio, the input potential after the potential drop is sensed. The potential can be set to a level near which the amplifier 17 is most sensitive. For example, when the transistors 30A and 130B are not provided and the "'1" level potential of the bit lines 11A and 11B after data reading is +5V and the "O" L/bell potential is +4.5V,
When the transistors 30A and 30B are provided, their potentials are lowered by, for example, 2V to +3V.

It can be set to +2.5V. Such an input potential almost coincides with an input potential near +2.5V, at which the sense amplifier 17 has the highest sensitivity.

Therefore, after this, the sense amplifier 17 inputs the input lines 18A, 1
The potential difference between the memory cells 83 is amplified with high sensitivity, and the data stored in the memory cell 10 is output from the output terminal 19 at high speed.

Further, this read data is output to the outside via the I10 buffer 24.

In this way, in the device of the above embodiment, the load circuit 13 is configured with a p-channel MOS transistor that does not cause a voltage drop due to the threshold voltage, so that the bit lines 11A, ilB
The electric potential is electric IT! The voltage increases to VDO. Therefore, stable operation can be achieved even with a low N applied voltage. Furthermore, by providing the transistor 30, the input potential can be set to a potential near which the sense amplifier 17 has the highest sensitivity, so data can be read out at high speed even when operating at a normal high power supply voltage. can.

FIG. 2 is a block diagram showing a configuration according to another embodiment of the invention. In this embodiment, the p-channel MOS transistor 30A used in the embodiment shown in FIG.
, 303, n-channel MO8 transistors 31A, 31B are connected between the bit lines 11A, 11B and the reference potential V99. In this case, the signal on the column decode line 15 is transmitted to each inverter 32.
are supplied to the gates of the corresponding pair of transistors 31A and 31B.

By the way, in each of the embodiment devices shown in FIGS. 1 and 2 above,
The input line 18 is connected by the write circuit 25 when writing data.
The potential of either A or 18B is "H" level,
The other input line 18 is set to the "L" level.Then, by providing the transistor 30 or 31, the input line 18, which is set to the "H" level potential by the write circuit 25, is set to the "L" level.
A current flows from the transistor 30 or 31 through the transistor 30 or 31. This leads to an increase in power consumption when writing data.

FIG. 3 is a block diagram showing the configuration of still another embodiment of the present invention, which prevents the increase in power consumption during data writing as described above.

In this embodiment device, an OR gate circuit 33 is newly added to the embodiment device shown in FIG. OR gate circuit 3
3, the corresponding set of transistors 30A, 30
The conduction of B is controlled. Here, the write enable signal WE is a signal that is activated (“H1 level”) only when writing data, and although not shown, the operation of the write circuit 25 and the like is controlled by this signal WE.

In this embodiment, the transistor 30 is made conductive only when the signal WE is made non-active and the column decode signal is made active, that is, when reading data. Therefore, when writing data with the signal WE activated, the input lines 18A, 1
A current path from 8B to the reference potential Vss is not generated, and wasteful power consumption can be suppressed. Note that in this embodiment, a p-channel MOS transistor may be used instead of the n-channel MOS transistor 30. and,
In this case, a NOR gate circuit is used instead of the OR gate circuit 33.

In the above embodiment, the case where the memory cell has a configuration of 4 transistors and 2 resistors using a high resistance load as shown in FIG. A six-transistor configuration may also be used.

[Effects of the Invention] As explained above, the static semiconductor memory device of the present invention has the advantage of operating stably even at a power supply voltage lower than the normal voltage and operating at high speed even at the normal power supply voltage.

Furthermore, in this type of memory device, the bit line potential and signal amplitude settings have an important relationship with reducing the delay time from the memory cell to the sense amplifier output.

Conventionally, the bit line potential and signal amplitude can only be set using a load circuit, but in the memory device of the present invention, this can also be done using potential lowering means, which has the effect of increasing the degree of freedom in design. Obtainable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of another embodiment of the present invention, FIG. 3 is a block diagram showing the configuration of still another embodiment of the present invention, and FIG. 4 is a block diagram showing the configuration of a conventional device.
FIGS. 5 to 7 are circuit diagrams specifically showing a portion of the conventional device and each of the embodiments described above, respectively. 10...Memory cell, 11A, 11B...Bit line, 12A, 12B...Word line, 13...Load circuit, 14...Power supply terminal, 15...Column decode line, 16A, 16B ...MOS transistor for bit line selection, 17...Sense amplifier, 18A, 18
B...Input line, 19...Output line, 20...Row address buffer, 21...Row decoder, 22...
Column address buffer, 23... column decoder,
24...I10 buffer, 25...Writing circuit,
30A, 30B...n-channel MOS for potential reduction
Transistors, 31A, 31B... n-channel MOS for potential reduction
Transistor, 32... Inverter, 33... OR gate circuit. Applicant's agent Patent attorney Takehiko Suzue Data No. 1 Figure 4

Claims (5)

[Claims] (1) A plurality of static memory cells for data storage, a bit line for exchanging data with each of the memory cells, a load circuit connected to the bit line, and reading data from the memory cell. A static semiconductor memory device comprising: a sense amplifier for amplifying a potential generated on the bit line; and a potential lowering means for lowering the potential generated on the bit line by a predetermined potential. (2) The potential lowering means is constituted by an n-channel MOS transistor connected between the bit line and a reference potential and whose conduction is controlled by a signal for selecting the bit line. 2. The static semiconductor memory device described in 2. (3) The potential lowering means is constituted by a p-channel MOS transistor connected between the bit line and a reference potential and whose conduction is controlled by a signal for selecting the bit line. 2. The static semiconductor memory device described in 2. (4) The potential lowering means is constituted by an n-channel MOS transistor connected between the bit line and a reference potential and conductive only when data is read from the memory cell. 2. The static semiconductor memory device described in 2. (5) The potential lowering means is comprised of a p-channel MOS transistor that is connected between the bit line and the reference potential and becomes conductive only when data is read from the memory cell. 2. The static semiconductor memory device described in 2.