JPH0555959B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and particularly to a dynamic semiconductor memory device used in computers and the like that require high integration, high speed, and high functionality.

[Technical background of the invention]

An example of a conventional dynamic semiconductor recording device is shown in FIG. Signals are exchanged between the memory cell 20 and the I/O line I/O via the bit line BL. Memory cell 20 is usually 1
It consists of two MOS transistors and one capacitor, which are arranged in a matrix to form a memory. Word lines WL ₁ and WL ₂ and a bit line BL are connected to the memory cell 20, and signals are sent to the memory cell 20 specified by the word lines WL ₁ and WL ₂ via the bit line BL. Giving and receiving takes place.

A sense amplifier 30 is connected to the memory cell 20 via a bit line BL, and the sense amplifier 30 is supplied with signal lines SAP and SAN. Thereby, the signal read from the memory cell 20 is level-converted and output. The output signal from the sense amplifier 30 is configured to be supplied to the I/O line I/O via the gate circuit 40. Then, when the signal line CSL connected to the gate circuit 40 is controlled to a high level, a signal from the sense amplifier 30 appears on the I/O line. Precharge circuits 50 and 60 are connected to the I/O line I/O, respectively.
The precharge circuits 50 and 60 are used to precharge the potential of the I/O line I/O to a predetermined potential, usually the power supply potential _Vcc , before the I/O buffer circuit 70 latches the signal. used.

These precharge circuits 50 and 60 are signal lines
It is configured to operate according to a control signal from CEQ, and when the potential of the signal line CEQ becomes low level, the precharge described above is performed.
The signal read to the I/O line I/O is transmitted to the I/O buffer circuit 70 via the gate circuit 80, and this gate circuit 80 is controlled by the write control signal WGT. Also, reading data from the I/O buffer circuit 70 is performed using a signal.
It is controlled by QSE, and when the signal QSE becomes high level, it latches data in the I/O buffer circuit 70, reads it out, sends it to the read data lines RD and RD, and sends it through the output buffer 90. The data is read externally. In addition, data from the outside is input via the write data line through the input buffer 900.
WD, transmitted over the write control circuit 11
0 to the I/O line I/O. The write control circuit 110 is controlled by the write control signal WGT mentioned above.

In such a conventional dynamic semiconductor memory device, when reading data from the memory cell 20, the signal line CSL is kept at a high level, and the signal from the sense up 30 is sent to the I/O line I/O,
Anticipating that it has appeared on the I/O, the signal line QSE is set to high level, and the data latched in the I/O buffer circuit 70, which is composed of a flip-flop circuit, is output via the read data line RD. It was designed to be transmitted to an external device such as a buffer 90 and retrieved. Similarly, when writing data,
The data taken in via the input buffer 900 is transmitted to the write control circuit 110 via the write data line WD, and the write control signal WGT is set to low level to transfer the data to the I/O line I/O,
The signal was transmitted to the I/O and sense amplifier 30.

[Problems with background technology]

However, such conventional dynamic semiconductor memory devices have the following problems. In other words, when reading data, the signal line CSL
Set the signal level of the I/O line to high level and connect the I/O line I/
When the signal on the bit line BL is fully expressed on O, the level of the signal line QSE is raised to latch the data, so dynamic operation is required and a margin for the operation timing must be allowed. Therefore, the read time is wasted.

Furthermore, since the read data lines RD and ride data lines WD must be run over long distances across one side of the semiconductor chip, there is a problem in that they occupy the chip area. especially,
In the future, it is expected that dynamic memories will be required to have configurations that transmit input/output data in multi-bit configurations such as 4 bits, 8 bits, and 16 bits.

Furthermore, in order to facilitate testing, it is necessary to perform logical operations on multi-bit information at the time of reading and then output it. In either case, even if the read data line RD and write data line WD can be shared, 4, 8, or 16 sets of data lines are required, so it is not possible to use complementary data lines as in the past. In this case, the data bus becomes thick, which is disadvantageous when it is housed in a small package.

[Purpose of the invention]

The present invention was made in consideration of the above circumstances, and
High-speed I/O of data latched to sense amplifier
It is an object of the present invention to provide a dynamic semiconductor memory device that can latch onto a line and transfer it to an output buffer.

[Summary of the invention]

To achieve the above object, the present invention provides a dynamic semiconductor memory device that transmits and receives signals between a memory cell and an I/O line via a bit line. a sense up means for dynamically latching and amplifying the signal on the bit line; and a sense up means provided between the bit line and the I/O line for amplifying the signal latched onto the bit line by the sense amplifier means. Said I/
a gate means coupled to the I/O line for feeding the applied signal onto the I/O line when the latched signal is applied from the bit line to the I/O line; The present invention provides a dynamic semiconductor memory device characterized by having I/O buffer means that independently and statically latches.

[Embodiments of the invention]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. It should be noted that the same parts as the circuit blocks of the circuit shown in FIG. 3 are given the same reference numerals, and the explanation thereof will be omitted.

In the storage device according to the present invention, the bit lines BL,
A means for statically latching the above signal onto the I/O line is employed, and this is the I/O buffer circuit 75 shown in FIG. This I/O buffer circuit 75 is configured as a current mirror type differential amplifier circuit. The signal path between the power supply potential V _cc and the ground potential V _ss is configured to be turned on or off by a transistor 2 to which the signal line DAE is input to the gate. This prevents unnecessary through-current from flowing.
The current mirror type differential amplifier circuit includes two N-type MOS transistors 11 and 12 forming a differential pair,
P-type MOS transistor 13, 1 forming a load
It consists of 4 pairs.

Further, in the present invention, a precharge circuit 55 is provided for precharging the I/O line to a predetermined potential before the I/O buffer circuit 75 starts latching. And this precharge circuit 5
The potential of the I/O line precharged by 5 is
The potential V _M is intermediate between the power supply potential V _cc and the ground potential V _ss . This precharge circuit 55 has three P-type
It is composed of MOS transistors 3, 4, and 5, and the sources of transistors 3 and 4 are connected to the power supply voltage.
It is connected to have an intermediate potential V _M between V _cc and ground potential V _ss .

Transistor 5 is used during the preparation period, that is, when the signal line
It has a function of equalizing the potential of the I/O line I/O during a period when the potential of CEQ is the ground potential _Vss . Furthermore, the two P-type transistors 3 and 4 have a function of fixing the potential of the I/O line I/O to the intermediate potential V _M during the preparation period.

The read control circuit 120 has N type and P type
Bidirectional transfer gate 7 consisting of MOS
At the time of reading, that is, when the signal line RDE becomes high level, the output data from the I/O buffer circuit 75 is transferred to the single read data line RD. Output buffer 90 and input buffer 100
Each of the read data line RD and the write data line WD connected to the read data line RD and the write data line WD is composed of one line, and is connected to the read control circuit 120 and the write control circuit 115. The write control circuit includes N-type and P-type bidirectional transfer gates 8 and 9,
It is composed of a CMOS inverter 10. Then, when writing, that is, the write control signal
When WGT becomes high level, data from the unified write data line WD is transferred to inverter 1.
It is inverted at 0 and transferred to the I/O line I/O, respectively.

Next, the operation of this circuit will be explained. I/O,
The data of bit line BL, is latched to the line pair as follows. That is, I/O,
When a signal that can be detected by the I/O buffer circuit 75 composed of a current mirror type differential amplifier is sent from the bit line BL to the I/O line pair, it automatically performs a static latch. Therefore,
Does not require control signal QSE like conventional equipment,
The circuit becomes simpler. Furthermore, in terms of time, conventionally it was necessary to raise the control signal QSE with some margin, but in the case of the present invention, the I/O
Since the latch is performed using the O, line signal itself, there is no need to take extra margin, and data can be quickly transferred to the read data line RD. The above is the first feature of the present invention.

Further, in the circuit of the present invention, the precharge circuit 55
The potential of the I/O line is set to the intermediate potential V _M by
I try to pre-charge. As before, the I/O and line potentials are set to the power supply potential during the preparation period.
When precharged to V _cc , the signal line CSL becomes high level and the signal on the bit line BL becomes I/
When appearing on the O, line, the bit line
BL, the signal with lower potential is I/O,
By simply lowering the potential of one of the I/O lines from the power supply potential _Vcc , the bit line BL connected to the higher potential remains at the level of the power supply potential _Vcc . Furthermore, if the signal line CSL is turned on when a sufficient signal is not yet output to the bit line BL, the I/O line connected to the bit line at the higher potential among the bit lines BL will also go to the power supply potential V. _cc level, and the I/O required for amplification with a Karetomirror differential amplifier.
The timing at which the I/O line level difference appears will be delayed. This often occurs when driving to shorten access time.

On the other hand, in the circuit of the present invention, the signal line CSL is turned off in order to precharge the potential of the I/O line to a potential V _M that is between the power supply potential V _cc and the ground potential V _ss during the preparation period. When the bit line BL is raised, the I/O line connected to the higher potential of the bit lines BL is always raised from the intermediate potential V _M to the power supply potential V _cc side. In addition, since the I/O line connected to the lower side can be lowered from the intermediate potential V _M to the ground potential V _ss side, the time when the level difference required for amplification by the current mirror differential amplifier appears. It's early.

The second feature of the present invention is that the precharge potential during the I/O line pair preparation period is precharged to the intermediate potential V _M where the sensitivity of the current mirror differential amplifier is highest.

Note that this configuration is suitable for a sensing method in which the bit line BL itself is precharged to an intermediate level between the power supply potential V _cc and the ground potential V _ss during the preparation period to reduce current consumption and eliminate fluctuations in the substrate potential. is particularly effective. Such a sense method is becoming mainstream in dynamic memory. In general, a current mirror amplifier has two
When two input signals V and a potential of V-ΔV are input, even though the potential difference ΔV is the same, the amplification factor differs depending on the value of V. When V=V _CC or V=V _SS +ΔV, the amplification factor is low.
Therefore, precharging the I/O line to the intermediate potential V _M is advantageous from the viewpoint of increasing the amplification factor of the differential amplifier.

Further, in the present invention, the read data line and the write data line are not configured in a complementary pair as in the prior art, but are configured as one line.
Such a configuration is preferable because it reduces the area occupied by the data bus due to the use of multi-bit dynamic memories, which are expected to increase in the future.

In addition, the precharge level of bit line BL,
V _BL and I/O, line precharge level V _M
It is also possible to keep them the same. This arrangement is effective in the sensing method, which is gradually becoming mainstream in dynamic memories, as described above.

Figure 2 shows the characteristics showing the relationship between the initial potential difference between the bit line BL and the I/O line and the level change of the I/O line after a certain period of time after the potential of the signal line CSL becomes high level. It is a diagram. As is clear from this figure, due to the connection of the I/O line to the bit line BL, the potential difference that separates from the intermediate potential V _M at a certain time is the initial I/O line and the bit line.
There is a tendency to saturate without being proportional to the potential difference between BL and BL. That is, when the potential difference is small, it is proportional to a good approximation. Therefore, when the potential difference between the bit lines BL and BL is constant, the signal line CSL is raised and the I/O
When applying a potential difference to lines, I/O, signal lines
When the level of CSL rises, when the precharge level V _M of the I/O line is at the intermediate potential of the bit line BL, that is, the precharge level V _BL of the bit line BL, after a certain period of time. I/O,
This increases as the potential difference between the I/O lines increases. Therefore, data appears on the read data line RD as quickly as possible.

The present invention is not limited to the above embodiments, and various modifications are possible. For example, circuits that statically latch signals on I/O lines are not limited to current mirror differential amplifiers. Furthermore, the number of write data lines WD and read data lines RD is not limited to one, but may be a pair.

〔Effect of the invention〕

As explained in detail above, the present invention includes means for statically latching the signal on the bit line onto the I/O line, and means for precharging the potential of the I/O line to the intermediate potential V _M before latching. ,
When latching the I/O line, it is not necessary to dynamically operate it as in the prior art, and therefore there is no need to take an operating margin, and data can be transmitted at high speed.

Furthermore, since the precharge level is selected at a point where the I/O buffer circuit operates at the highest speed, high-speed amplification is possible.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a characteristic diagram showing the relationship between the potential difference between the bit line and the I/O line and the I/O level displacement, and FIG. 3 is a circuit diagram showing the configuration of a conventional semiconductor memory device. 20...Memory cell, 30...Sense amplifier,
40... Gate circuit, 55... Precharge circuit, 75... I/O buffer circuit, 115... Write control circuit, 120... Read control circuit.

Claims (1)

[Scope of Claims] 1. In a dynamic semiconductor memory device in which signals are exchanged between a memory cell and an I/O line via a bit line, the memory cell is coupled to the bit line and the signal of the memory cell is transferred to the bit line. a sense amplifier means for dynamically latching and amplifying the signal on the bit line; and a sense amplifier means provided between the bit line and the I/O line to transfer the signal latched onto the bit line by the sense amplifier means from the bit line to the I/O line. /
a gate means coupled to the I/O line for supplying the supplied signal onto the I/O line when the latched signal is supplied from the bit line to the I/O line; 1. A dynamic semiconductor memory device comprising I/O buffer means that independently and statically latches. 2. The device further comprises precharging means for precharging the potential of the I/O line to an intermediate potential V _M between the first potential V _cc and the second potential V _ss before latching by the I/O buffer means. A dynamic semiconductor memory device according to claim 1. 3. The dynamic semiconductor memory device according to claim 1, wherein said I/O buffer means is constituted by a current mirror type differential amplifier circuit. 4. The dynamic semiconductor memory device according to claim 1, wherein the intermediate potential V _M is the same as the precharge potential of the bit line.