JPS62157398A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To execute a data transmission at high speed by providing a means to latch statically the signal on a bit line onto an I/O line and means to precharge the electric potential of the I/O line to the intermediate electric potential before latching. CONSTITUTION:To an I/O and the inverse of I/O line pair, the signal, which can be detected by an I/O buffer circuit 75, is sent from bit lines BL and the inverse of BL, and then, independently, the signal is latched. Thus, it is not necessary to obtain the spare allowance, and rapidly, the data can be transferred to a read data line RD. At the circuit, the electric potential of the I/O and the inverse of I/O lines is precharged to an intermediate electric potential VM of a power source electric potential and an earth electric potential by a precharging circuit 55. Thus, then a signal line CSL is led, the I/O and the inverse of I/O lines connected to the higher electric potential out of the bit liens BL and the inverse of BL are ascended to the power source electric potential from the electric potential VM without fail. Since the I/O line and the inverse of I/O line connected to the lower electric potential are descended from the electric potential VM, the time is hastened in which the necessary level difference is made.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and particularly to a dynamic semiconductor memory device used in computers and the like that require high integration, high speed, and high functionality.

[Technical blue use of invention]

An example of a conventional dynamic semiconductor memory device is shown in FIG. The memory cell 20 and I are connected via bit lines BL and BL.
/O line I/O. Signals are exchanged with Ilo. The memory cell 2o is normally composed of one MOS transistor and one capacitor, which are arranged in a matrix to form a memory. The memory cell 20 has the word FIIWL1. WL, , and bit line [
3L.

BL are connected, and the word lines WL1. For the memory cell 20 specified by WL2, the pin 1-lines BL, B
Signals are exchanged via L.

A sense amplifier 30 is connected to the memory cell 20 via a bit line 81.8L, and this sense amplifier 30 is supplied with signal lines SAP and SΔN. Thereby, the signal read from the memory cell 20 is level-converted and output. The output signal from the sense amplifier 30 is sent to l/O1iiI/O. through the circuit 40. Ilo. When the signal line C8L connected to the goo1-circuit 40 is controlled to a high level, a signal from the sense amplifier 30 is applied to the [/O line. I/O line I/O. Precharge circuits 50, 60 are connected to Ilo, respectively, and these precharge circuits 50, 60 connect I/O lines I/O. Il
It is used to keep the potential of 0 at a predetermined potential, usually the power supply potential VCC.

The precharge circuits 50 and 60 are configured to operate in response to a control signal from the signal line CEQ, and perform the aforementioned precharge when the potential of the signal line CEQ becomes low level.

I/O line r/O. The signal read out to [/O is transmitted to the I/O buffer circuit 70 via the gate circuit 80, and the circuits 1 to 80 are controlled by the write control signal WGT. Further, the reading of data from the I/O buffer circuit 70 is controlled by the signal QSE, and when the signal QSE becomes high level, the I/O buffer circuit 70
The data is latched in the buffer, read out and sent to the read data lines RD and RD, and output to the output buffer? It is read out to the outside via 90. Also, external data is transmitted via the input buffer 900 onto the write data lines WD, WD, and via the write control circuit 1/O to the I/O line I/O.
Manpower is provided by Ilo. The write control circuit 1/O is controlled by the write control signal WGT mentioned above.

In such conventional dynamic semiconductor memory devices,
When reading data from the memory cell 20, the signal line C3L is kept at a high level, and the signal line QSE is turned on when the signal from the sense amplifier 30 appears on the I/O line I/O゜Ilo. Read data 1! is set to high level and the data latched in the 1/O buffer circuit 70 made up of a flip-flop circuit is read data 1! The data was transmitted to the outside from the output buffer 790 via RD and ID and taken out. Similarly, when writing data, the data taken in via the input buffer 900 is transmitted to the write control circuit 1/O via the write 1 to data FAWD and WD, and the old control signal WGT is set to low level to write the data. , I/O line I/O゜ [/O Onibi sense amplifier 30
I was trying to set the transmission to 1.

(Problems with Background Art) However, such conventional dynamic semiconductor memory devices have the following problems.
When reading data, set the signal level of signal line C3L to high level, see that the I/O is sufficiently displayed, and then raise the level of signal line QSF to latch the data.J:
Since dynamic operation is required and a margin for operation timing must be considered,
Reading time is wasted.

Furthermore, read data lines RD, RO and write data line W
Since the D and WD have to run over a long distance along one side of the semiconductor chip, there is a problem that the chip area is occupied. In particular, dynamic memory will
It is expected that a configuration for transmitting input/output .gamma. data in a multi-pit configuration such as 4 bits, 8 bits, or 16 pitches will become required.

Furthermore, in order to facilitate testing, it is necessary to perform logical operations on multi-bit information before outputting it. In either case, even if the read data lines RD, R1) and the write data lines WD, WD can be shared, 4 sets of data lines and 811.16 sets are required, so it is not necessary to use the data lines as in the past. If they were configured in a complementary manner, the data bus would become thicker, making it difficult to accommodate it in a small package.

[Purpose of the invention]

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor memory device that can quickly latch data latched in a sense amplifier onto a 1/O line and transfer it to an output buffer. purpose.

[Summary of the invention]

In order to achieve the above object, the present invention includes a semiconductor memory device J3 that transmits and receives signals between a memory hill and an Ilo line via a bit line, and statically latches the signal on the bit line onto the 1/○ line. A first means and a second S means are provided for precharging the potential of the 1/O line to an intermediate potential v8 between the first potential vcC and the second potential V before latching by the first means. The present invention provides a semiconductor memory device characterized by the following.

[Embodiments of the invention]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

5) The same parts as the circuit blocks of the circuit shown in FIG. 3 are given the same reference numerals, and the explanation thereof will be omitted.

In the memory device according to the present invention, the bit line BL.

A means for statically transferring the signal on the BL onto the I/O line is adopted, and this is the I/O line shown in Figure 1.
This is an O buffer 7 circuit 75. This I/O buffer circuit 75 is configured as a current mirror type differential amplifier circuit. The signal path between the power supply potential VCC and the ground potential Vss is configured to be turned on or off by a transistor 2 whose gate receives the signal line DΔE. This prevents unnecessary through-current from flowing. The current mirror type differential amplifier circuit consists of two N-type MO3l transistors 11 and 12 forming a differential pair, and P-type MO8l transistors 13 and 14 forming a load.
It consists of a pair of .

Furthermore, in the present invention, the Ilo line is precharged to a predetermined potential before the I/O buffer circuit 75 starts latching. - circuit 55 is explained. The potential of the Ilo line precharged by this precharge circuit 55 becomes a potential vH and C, which are intermediate between the power supply potential V1 and the ground potential Vss. This precharge circuit 55 has three P-type MO8l
- consists of transistor 3.4.5, the source of transistor 3.4 is connected to supply voltage V and ground potential V
Connect cc so that it becomes the intermediate potential VH of
ss is continued.

Transistor 5 is in the preparation period, that is, in the i-line CEQ
During the period when the potential of the I/O line I/O. I
It has a function of equalizing the lo potential. In addition, the two 1] type transistors 3 and 7I are connected to I/O during the preparation period.
Line I/O. It has a function of fixing the potential of Ilo to the intermediate potential VH.

The read control circuit 120 is composed of bidirectional 1-transfer groups 1-7 consisting of N to P-type MOSs, and when reading, that is, when the signal line R1]13 goes to a high level, Time (I/O sofa circuit 75
Read data 'f consisting of one piece of output data from
Performs the operation of transferring to ARD.

The read data line Rl) 43 J: and the read data line WD connected to the output buffer 90 and the input buffer /O0 are each composed of one line, and are connected to the read control 11 circuit 120J5 and the write control circuit 115. The fortune-telling control circuit is composed of N-type and P-type bidirectional transfer gates 8.9 and a CMOS inverter/O. Then, during writing, that is, when the write control signal WGT becomes high level, the data from the unified write data line WD is inverted by the inverter /O and transferred to 1/OFll[/O and Ilo, respectively.

Next, the operation of this circuit will be explained. The data on the bit lines BL and BL are latched to the Ilo, 1, /O line pair as follows. That is, Ilo.

When a signal that can be detected by the I/O buffer circuit 75 composed of a current mirror type differential amplifier is sent from the bit lines BL and BL to the I/O line pair, static latching is performed autonomously. Therefore, unlike the conventional device, the control signal QSE is not required, and the circuit becomes simple. Furthermore, in terms of time, conventionally it was necessary to raise the control signal QSE with a certain margin of polishing, but in the case of the present invention, the control signal QSE has to be raised with a certain margin of polishing.

Since latching is performed using the I/O line signal itself, data can be transferred to the J/A13 cleat data line RD without the need for extra margin. The above is the first feature of the present invention.

Further, in the circuit of the present invention, the precharge circuit 55 precharges the potentials of the Ilo and I/O lines to the intermediate potential VFl. Ilo during the preparation period as before
, when the potential of the I/O line is bridged to the power supply potential vCC, the signal line C8L becomes high level and the signals from the pin I to the lines BL and BL appear on the Ilo and I/O lines. Then, the signal of the lower potential among the bit lines [3L and BL] connects the potential of either the 1/O or I/O line to the power supply potential vo.
By simply lowering it from c, the bit line BL and the one connected to the higher potential at the back of BL are at the power supply potential ■. It stays at level 0. Furthermore, if the signal line C3L is turned on when the bit lines BL and BL do not have sufficient signals yet,
The bit lines BL and Ilo and I/O lines connected to the bit line at the higher potential of BL are also at the power supply potential ■. As a result, the time when the level difference between the Ilo and I/O lines, which is necessary for amplification by the Kareto-mirror differential amplifier, appears will be delayed. This often occurs when driving to shorten access time.

In contrast, in the circuit of the present invention, I
In order to bridge the potential of the I/O line to the potential vH between the power supply potential and the ground potential V, when the signal line C8L is turned on, the bit line BL, 8m Ilo connected to the one with higher potential
, f/O line is always raised from the intermediate potential vH to the power supply potential vCc side. Also connected to the lower side Ilo, I
Since the /O line can be lowered from the intermediate potential ■8 to the ground potential vss side, the time when the level difference necessary for amplification by the current mirror type differential amplifier appears has been brought forward.

The second feature of the present invention is that the precharge potential of the Ilo and I/O line pair during the preparation period is precharged to the intermediate potential vH, which provides the best sensitivity of the Karen I/Miller differential amplifier. be.

Note that in this configuration, the pit lines BL and BL themselves are set to the power supply potential V during the preparation period. This is particularly effective in a sensing method in which the current consumption is reduced by precharging to an intermediate level between C and the ground potential vss to eliminate fluctuations in the substrate potential. Such a sense method is becoming mainstream in dynamic memory. Generally, when two input signals (2) and a potential of V-ΔV are input to a current mirror amplifier, the amplification factor differs depending on the value of V even if the potential difference (Δ) is the same. The amplification factor is lowest when ■=■oo or when v=vss+ΔVSS. Therefore, Ilo, I/O! ! Precharging il to the intermediate potential vH is advantageous from the viewpoint of increasing the amplification factor of the differential amplifier.

Further, in the present invention, the read data line and the write data line are not configured in a complementary pair as in the conventional case.
I try to make it consist of one piece.

This configuration is preferable because it reduces the area occupied by the data bus due to multi-bit dynamic memories that are expected to increase in the future.

Note that the precharge level VB[ of the bit lines BL and BL
It is also possible to make the Ilo, Ilo, and I/O line bridge level (8) the same. If you do it this way,
As mentioned above, this is effective in the sense method that is gradually becoming the mainstream of dynamic memory.

Figure 2 shows the characteristics showing the relationship between the initial potential difference between the bit line BL and the I/O line and the level change of the I/O line for a certain period of time after the potential of the signal line C8L becomes high level. It is a diagram. As is clear from this figure, the I/O line, I/C
1 is human r/AB L.

In the connection to BL, the potential difference that separates from the intermediate potential VH at a certain time is the initial Ilo, I/O line and bit line BL.
, BL tends to saturate in proportion to the potential difference with BL.

In other words, when the potential difference is small, it is proportional to a good approximation.

Therefore, when the potential difference between the pin 1 and the lines BL and BL is constant, when raising the signal line C3L- to create a potential difference between the I/O lines, Ilo and Ilo, when the level of the signal line C3L rises, ■/O ．． The pre-level t7-level vh of the I/O line is the intermediate potential of the bit line BL, that is, the bit line BL,
When the BL is at the precharge level VBL, the potential difference between the Ilo and I/O lines after a certain period of time becomes noticeable. Therefore, data appears on the read data line RD as quickly as possible.

The present invention is not limited to the above embodiments, and various modifications are possible. For example, a circuit that statically latches a signal on an I/O line is not limited to a current mirror type differential amplifier. Also, light data F1! The number of WD and read data line RD is not limited to one, and each may be a pair.

〔Effect of the invention〕

As explained in detail above, the present invention includes means for statically latching the signal on the bit line onto the I/O line, and means for changing the potential of the I/O line to an intermediate potential V, +7 before latching. Therefore, when latching the 1/OFJ, it is not necessary to dynamically operate as in the conventional case, and therefore there is no need to take an operating margin, and data can be transmitted at high speed.

Furthermore, since the bridge level is selected at a point where the I/O buffer circuit operates at high speed, high-speed amplification is possible.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an embodiment of the present invention, Figure 2 is a characteristic diagram showing the relationship between the potential difference between a bit line and an I/O line and I/O level displacement, and Figure 3 is a diagram of a conventional semiconductor. 3 is a circuit diagram showing the configuration of a memory table U. FIG. 20...Memory cell, 30...Sense amplifier, 40
... Gate circuit, 55 ... Precharge circuit, 75
. . . I/O buffer circuit, 115 . . . Write control circuit, 120 . . . Read control circuit.

Claims (1)

[Claims] 1. In a semiconductor memory device that transmits and receives signals between a memory cell and an I/O line via a bit line, a signal on the bit line is statically latched onto the I/O line. and a second means for precharging the potential of the I/O line to a potential V_M intermediate between the first potential V_C_C and the second potential V_S_S before latching by the first means. A semiconductor memory device characterized by: 2. The semiconductor memory device according to claim 1, wherein said first means is an I/O buffer circuit constituted by a current mirror type differential amplifier circuit and coupled to said I/O line. 3. The semiconductor memory device according to claim 1, wherein the intermediate potential V_M is the same as the precharge potential of the bit line.