JPH0370320B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an n-value logic storage circuit, and particularly to a multi-value logic storage circuit that writes and reads data in current mode. Regarding.

(Prior Art) Semiconductor memories, especially dynamic random access memory circuits that store data in the form of electric charges,
The storage capacity of so-called DRAM continues to increase rapidly as circuit technology, semiconductor manufacturing technology, etc. improve. However, the increase in storage capacity due to miniaturization of elements leads to a decrease in the capacity of charge storage capacitors, making it difficult to determine the storage state of data in memory cells.

In response to this, multivalued logic storage circuits are being researched as a means of increasing storage capacity. This multivalued logic storage circuit can increase the amount of information per cell compared to a binary logic storage circuit, so it can be highly integrated. Furthermore, multilevel circuits are expected to be applied to functional devices that use multilevel functions.

However, most of the multi-valued logic memory circuits announced so far have been written and read in voltage mode, and have various disadvantages, such as noise margin, than those of binary logic. For example, conventional multi-level logic storage circuits use CCDs as memory cells.
(charge-coupled device) and one-transistor type similar to binary logic.In the former case, it is difficult to reduce the voltage due to large charge transfer loss, and the capacitive load is difficult to reduce. There are problems such as high power consumption because it needs to be driven.
Further, in the latter case, there is a problem that the operating speed is slow.

(Problems to be Solved by the Invention) As described above, the conventional multivalued logic memory circuit has drawbacks such as difficulty in reducing the voltage, high power consumption, and slow operation speed.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to provide a multi-function device that can obtain a large noise margin with a simple circuit configuration, and can also write and read data at high speed. An object of the present invention is to provide a value logic storage circuit.

[Structure of the Invention] (Means for Solving the Problems) A multivalued logic storage circuit of the present invention includes a first current mirror circuit having a drive circuit and a load circuit;
n on the drive circuit side of the first current mirror circuit.
a current input means for passing a current of a certain value;
is connected to the load circuit side of the current mirror circuit of
A second current having a memory cell that stores a voltage having a value corresponding to the current flowing to the load circuit side, a drive circuit, and a load circuit, and a current flowing to the drive circuit side according to the voltage stored in the memory cell. It is comprised of a mirror circuit and a logic signal generating means connected to the load circuit side of the second current mirror circuit and generating a logic signal according to the value of the current flowing to the load circuit side.

(Function) In the multivalued logic storage circuit of the present invention, when writing data, currents of n different values are caused to flow to the drive circuit side of the first current mirror circuit according to the written data, and currents of n different values are caused to flow to the drive circuit side of the first current mirror circuit depending on the current flowing to the load circuit side. The value of the voltage is stored in the memory cell. Further, when reading data, a current corresponding to the voltage stored in the memory cell is passed through the drive circuit side of the second current mirror circuit, and a logic signal is generated that is connected to the load circuit side of the second current mirror circuit. The means generates a logic signal corresponding to the current value at this time.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a multivalued logic storage circuit according to the present invention. In the figure, 11 is a first current mirror circuit. This first current mirror circuit 11 is composed of a drive circuit 12 and a load circuit 13, and a current input circuit 14 is connected to the drive circuit 12 side. This current input circuit 14 generates a current _IW corresponding to a certain value of n-value logic expressed by a multi-bit binary logic signal supplied to an input terminal 15, and supplies this current _IW to the drive circuit 12. do.

A memory cell 16 is connected to the load circuit 13 side of the first current mirror circuit 11. This memory cell 16 is arranged at a differential position between a row line (not shown) and a column line, which are selectively driven by an X decoder (row decoder) and a Y decoder (column decoder) (not shown). And a voltage having a value corresponding to the current flowing to the load circuit 13 side when the column line is selectively driven is stored as data. The voltage storage method in this memory cell 16 is based on a dynamic type in which charges are temporarily stored.

Further, 17 is a second current mirror circuit. This second current mirror circuit 17 is composed of a drive circuit 13 and a load circuit 18, which are also used as the load circuit of the first current mirror circuit 11, and the drive circuit 13 side includes the memory cell 1.
6 is connected. When reading data, the memory cell 16 generates a current I _R corresponding to the voltage value stored in advance, and supplies this current to the drive circuit 13 of the second current mirror circuit 17.

A logic signal generation circuit 19 is connected to the load circuit 18 side of the second current mirror circuit 17. This logic signal generation circuit 19 generates a read control signal.
When RO is supplied, the current mirror circuit 17
The current I _R ' flowing to the load circuit 18 side is detected and a binary logic signal corresponding to the current value is generated. Then, the 2 generated by this logic signal generation circuit 19
The value logic signal is output from the output terminal 20.

As described above, since the above embodiment circuit writes and reads data in current mode, it has various advantages such as high speed writing and reading, large noise margin, and high reliability. It has advantages.

FIG. 2 is a circuit diagram specifically showing the circuit of the above embodiment, and parts corresponding to those in FIG. 1 are given the same reference numerals for explanation. The drive circuit 12 of the first current mirror circuit 11 includes a P-channel MOS transistor 21 whose source is connected to a positive power supply voltage _VDD , and a source and drain connected between the gate and drain of this transistor 21. , and a P-channel MOS transistor 22 whose conduction is controlled when data is written to the memory cell 16. The load circuit of the first current mirror circuit 11 or the drive circuit 13 of the second current mirror circuit 17 has a source connected to the positive power supply voltage V _DD and a gate connected to the gate of the transistor 21 . A P-channel MOS transistor 23, whose source and drain are connected between the gate and drain of the transistor 23, and is made non-conductive when writing data to the memory cell 16,
It is composed of a P-channel MOS transistor 24 whose conduction is controlled when reading data from the memory cell 16.

Load circuit 18 of second current mirror circuit 17
is composed of a plurality of P-channel MOS transistors 25 whose sources are connected to a positive power supply voltage V _DD and whose gates are connected in parallel to the gate of the transistor 23 . The output terminal 20 is connected to the drain of each transistor 25.

The current input circuit 14 has each drain commonly connected to the drain of the transistor 21 in the drive circuit 12 of the first current mirror circuit 11,
_A plurality of
It is composed of a channel MOS transistor 26. That is, in this embodiment, the current input circuit 14
is for converting a binary logic signal into an n-value current.

The memory cell 16 is an N channel whose drain is connected to the drain of the transistor 23 in the load circuit 13 of the first current mirror circuit 11.
It consists of a MOS transistor 27 and an N-channel MOS transistor 28 whose drain is connected to the drain of the transistor 27 and whose source is connected to the gate of the transistor 27.
The source of the transistor 27 is connected to one row line 29, and the gate of the transistor 28 is connected to one row line 29.
It is connected to the book column line 30. Note that the transistor 28 may be a P-channel transistor.

The logic signal generation circuit 19 has a drain connected to the drain of each transistor 25 in the load circuit 18 of the second current mirror circuit 17, a source commonly connected to the ground voltage V _SS , and a gate connected to the readout circuit 19. Each one supplied with control signal RO
N-channel MOS transistors 31, whose drains are connected to the drains of each transistor 25 in the load circuit 18 of the second current mirror circuit 17, whose sources are commonly connected to the ground voltage V _SS , and whose gates are connected to the upper All output terminals 2 of BIT
N-channel MOS transistors 32 each connected to VDD, their sources are commonly connected to _VDD , and their drains are connected to the drains of each transistor 25 in the load circuit 18 of the second current mirror circuit 17, and the memory cell The conduction is controlled when data is read from the transistor 16, and the transistor 25 is made up of the same number of N-channel MOS transistors 33 as the transistor 25. The element dimensions and the like are set so that when the transistor 33 is turned on, a current corresponding to logic "0.5" flows through each transistor 33, assuming that the current flowing through the transistor 25 is logic "1". Further, in this embodiment, the logic signal generation circuit 19 is used to convert n-value current into a binary logic signal.

In such a configuration, when writing data, the transistor 22 in the drive circuit 12 of the first current mirror circuit 11 is made conductive;
Transistor 24 in load circuit 13 is made non-conductive. As a result, a current In having one of the n values flowing through the current input circuit 14 in accordance with the binary logic signal supplied to the input terminal 15 flows through the transistor 21 . For example, the transistor 21
If the channel dimensions of and 23 are set equal, the same value of current In will flow through transistor 23
and is supplied to the memory cell 16. In this memory cell 16, the row line 29 is set to the ground voltage and the column line 30 is set to the ground voltage according to the address signal when writing data.
Selectively set to V _DD voltage. That is, the gate of the transistor 28 is brought to a high potential and becomes conductive. However, in this case, an N-channel transistor is used as the transistor 28. Then, the current In flows between the source and drain of the transistor 27, and the gate voltage of the transistor 27 is maintained at a voltage corresponding to the connection state between the drain and the gate.
That is, when the gate voltage of the transistor 27 at this time is V _G and the threshold voltage is V _T , the following equation holds between them.

In=β(V _G −V _T ) ² ...1 However, β is a proportionality constant. That is, when data is written, the voltage V _G given to the memory cell 16 according to the relationship of equation 1 above is accumulated at the gate of the transistor 27 . After this, if the transistor 28 is made non-conductive, the transistor 27
The gate voltage of is maintained dynamically.

On the other hand, when reading data, the first
The transistor 22 in the drive circuit 12 of the current mirror circuit 11 is made non-conductive, and the transistor 24 in the load circuit 13 is made conductive. In the memory cell 16, the row line 29 is set to the ground voltage.
Then, due to the voltage stored at the gate of the transistor 27, a current In corresponding to one of the n values flows through the transistor 27 and the transistor 23. At this time, in the logic signal generation circuit 19, the transistor 31 is made conductive by the readout control signal RO, so that the above-mentioned current
A binary logic signal corresponding to In is generated.

The detailed operation at the time of reading the data will be explained by taking as an example the case where the value of n is 4 as shown in FIG. In addition, Fig. 4 shows the output terminal 2 of this Fig. 3 circuit.
2 is a characteristic diagram showing the relationship between the voltages of binary logic signals D ₀ and D ₁ obtained at 0 ₀ and 20 ₁ and the current I. FIG. Fourth
In the figure, broken line curves 41 to 43 indicate currents corresponding to logical values "1", "2", and "3" of the memory cell 16, and solid line curves 44 to 47 indicate these curves 41 to 43. 43 and the logical value “0”, the logical value “0” is added by the amount equivalent to the logical “0.5” flowing through the transistor 33.
+ “0.5”, “1” + “0.5”, “2” + “0.5”, “3”
”＋
The solid curves 48 to 50 indicate the current corresponding to "0.5", and the solid curves 48 to 50 represent the transistors 31 ₀ ,
The static characteristics of 31 ₁ alone and when transistors 31 ₀ and 32 are connected in parallel are shown respectively. Then, the voltage at the intersection of these characteristics is the signal
They are output from terminals 20 ₀ and 20 ₁ as D ₀ and D ₁ .

First, when stored data with a logic value of "0" is read out, both signals _D0 become "L" of binary logic.

When stored data with logical value “1” is read,
The signal D ₀ is the voltage at the intersection of curve 45 and curve 48,
In other words, it becomes “H” of binary logic, and D ₁ is curve 4
5 and the curve 49, that is, the voltage is "L" in binary logic.

When the stored data with logical value “2” is read,
Signal D ₁ is the voltage at the intersection of curve 46 and curve 49,
In other words, it becomes "H" of binary logic. At this time, the signal D ₁ makes the transistor 32 conductive, so the other signal D ₀ is connected to the curve 46 and the transistor 3
The voltage at the intersection with the characteristic curve 50 when 1 ₀ and 32 are connected in parallel, ie, the binary logic "L".

When the stored data with logical value “3” is read,
Signal D ₁ is the voltage at the intersection of curve 47 and curve 49,
In other words, it becomes "H" of binary logic. At this time too,
Since this signal D ₁ makes the transistor 32 conductive, the other signal D ₀ is connected to the curve 48 and the characteristic curve 50.
The voltage at the intersection with , that is, the binary logic "H".

The signals D ₀ and D ₁ obtained from the output terminals 20 ₀ and 20 ₁ in this way are supplied to a buffer circuit constructed by connecting two stages of inverters in series and having characteristics as shown in FIG. By buffer amplifying, the "H" of the binary logic can be moved to a value closer to V _DD , and the "L" to a value closer to 0V, making it possible to reliably output data with a larger noise margin. I can do it.

FIG. 6 shows the stored data in the circuit shown in FIG. 3 and the corresponding binary logic signals D ₀ ,
FIG. 3 is a diagram collectively showing the truth values of D ₁ .

The method using the four-value logic explained above can be extended to the n-value logic in the embodiment circuit of FIG.

In this way, according to the above embodiment, a memory circuit of any n-value logic can be configured. Furthermore, there is an advantage that the design and manufacturing process are simple for any n value by considering only the shape of the transistor.

The circuit of the above embodiment has advantages such as a large noise margin, high reliability, a simple memory cell configuration and a small occupied area, and a short access time. These advantages will become clear in the description below.

When manufacturing the specific circuit shown in Figure 2 above using CMOS process technology, we investigated the difference in characteristics between using an N-channel transistor and a P-channel transistor as the transistor 28 in the memory cell 16. Ta. When the transistor 28 is an N-channel transistor, a well region is not required when configuring the memory cell 16, and the area occupied by the cell can be reduced, but the noise margin is reduced.

FIG. 7 shows the relationship between write current I _W , read current I _R and gate voltage V _G of transistor 27 for each logic value when transistor 28 is configured with an N-channel or P-channel MOS transistor with power supply _voltage V DD 5V. FIG. As shown in the figure, write current I _W , read current I _R and gate voltage V _G can be increased when transistor 28 is configured with a P-channel MOS transistor. Further, regardless of whether the transistor 28 is configured as a P channel or an N channel, the values of the write current I _W and the read current I _R are equal, and this is one of the factors that can improve reliability.

FIG. 8 shows the cases shown in FIG. 7 above, that is, when an N-channel MOS transistor is used as the transistor 28, and when a P-channel MOS transistor is used, and when the gate voltage V _G is divided into three equal parts. , is a characteristic diagram when the write and read current I is divided into three equal parts. That is, Figure 8a
is a characteristic diagram when the gate voltage V _G is divided into three equal parts when an N-channel MOS transistor is used as the transistor 28, and FIG. 8b shows the write and read current when an N-channel MOS transistor is used as the transistor 28. This is a characteristic diagram when I is divided into three equal parts, and FIG. 8c is a characteristic diagram when the gate voltage V _G is divided into three equal parts when a P channel MOS transistor is used as the transistor 28. d is a characteristic diagram when the write/read current I is equally divided into three when a P-channel MOS transistor is used as the transistor 28. When using N-channel MOS transistors, transistor 28 has a small noise margin.
This is because the actual threshold voltage increases due to the backgate bias effect and becomes non-conductive at a certain source voltage (gate voltage of transistor 27) lower than V _DD .

On the other hand, when a P-channel MOS transistor is used as the transistor 28, there is no back gate bias effect as described above, and V _G up to V _DD can be used, so a large noise margin can be obtained. In other words, the write and read currents I are set to 3
When divided into equal parts, the noise margin can be as large as 36.5μA.

Furthermore, in the above embodiment circuit, the logic value "0",
The access time for “1”, “2”, and “3” is 0 nanoseconds, respectively, when the minimum line width is 5 μm.
They were 50 nanoseconds, 68 nanoseconds, and 28 nanoseconds. Also,
Power consumption is 170μW, 465μW, 750μW, and 900μW for logic values “0”, “1”, “2”, and “3”, respectively.
It was hot. In addition, considering the fact that if the minimum line width is set to 1/k, the access time becomes approximately 1/k ² and that it is possible to pursue optimal conditions, it has excellent performance with very high speed and low power consumption. It is possible to configure a memory circuit with

In addition, the above example circuit is a normal binary CMOS
-Can be manufactured using exactly the same process technology as LSI technology.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, the example circuit described above is composed of MOS transistors, but this
It goes without saying that the configuration is not limited to MOS transistors, but can also be configured with bipolar transistors.

Further, in the above embodiment circuit, the case where the input signal and the output signal are binary logic signals has been explained, but it goes without saying that these may be any multi-value signals, depending on the multi-value signal used. Therefore, the configurations of the current input circuit 14 and the logic signal generation circuit 19 may be changed.

[Effects of the Invention] As explained above, according to the present invention, a large noise margin can be obtained with a simple circuit configuration.
Moreover, it is possible to provide a multivalued logic storage circuit that can write and read data at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram specifically showing the circuit of the embodiment described above, and FIG. 3 is a diagram showing the value of n in the circuit shown in FIG. , a partially extracted circuit diagram, FIG. 4 is a characteristic diagram of the circuit shown in FIG. 3 above, FIG. 5 is an input/output characteristic diagram when the signal obtained by the circuit shown in FIG. is a diagram showing the truth value of the output signal of the circuit shown in FIG. 3, FIG. 7 is a diagram collectively showing the write and read currents and gate voltages of the circuit shown in FIG. 3, and FIG. 8 explains the circuit shown in FIG. 3. FIG. 11...first current mirror circuit, 14...
Current input circuit, 16...Memory cell, 17...Second current mirror circuit, 19...Logic signal generation circuit, 21, 22, 23, 24, 25, 33...
P channel MOS transistor, 26, 27, 2
8, 31, 32...N channel MOS transistor, 29...row line, 30...column line.

Claims (1)

[Scope of Claims] 1. A first current mirror circuit having a drive circuit and a load circuit, and a current that supplies n values of input current to the drive circuit side of the first current mirror circuit when writing data. The input means and one end between the source and drain are connected to the load circuit side of the first current mirror circuit, and the source and drain are connected to the load circuit side of the first current mirror circuit.
The first one whose other end between the drains is connected to the row line
A second MOS transistor whose source and drain is inserted between the drain and gate of the first MOS transistor, and whose gate is connected to the column line.
A MOS transistor is supplied with a current flowing to the load circuit side of the first current mirror circuit, and has a memory cell that stores a voltage corresponding to this current value, a drive circuit, and a load circuit, and has a data readout circuit. At times, a second current mirror circuit supplies a current corresponding to the voltage stored in the memory cell to the drive circuit side, and a current flows to the load circuit side of the second current mirror circuit, and this current 1. A multivalued logic storage circuit, comprising: logic signal generation means for generating a logic signal according to a value. 2. The multivalued logic storage circuit according to claim 1, wherein the load circuit of the first current mirror circuit also serves as a drive circuit of the second current mirror circuit. 3 On the load circuit side of the second current mirror circuit, there are N circuits each having one end connected to the power supply.
= log ₂ n) load elements are provided, each other end of each of these N load elements is connected to each output terminal of a bit signal consisting of a plurality of bits, and the logic signal generating means is configured to: One end between the source and drain is connected to the other end of each of the N load elements of the current mirror circuit No. 2, and conduction is controlled when reading data.
one end between the source and drain is commonly connected to the other end of the corresponding one of the N third MOS transistors,
At least one fourth bit whose gate is connected to the output terminals of all bits higher than that bit.
2. The multivalued logic storage circuit according to claim 1, which comprises a MOS transistor. 4. The logic signal generating means includes means for adding and flowing a current corresponding to 0.5 in logical value to each of the N load elements of the second current mirror circuit. A multivalued logic storage circuit as claimed in claim 3 provided.