JPS60239994A - Multivalued dynamic random access memory - Google Patents

Abstract

PURPOSE:To increase substantially the storage capacity with the same chip area by setting three and more potentials stored in one memory cell. CONSTITUTION:A digital input signal from an input terminal 103 is converted into a corresponding potential between a positive potential VDD of a power source and a negative potential -VSS by an input converter circuit 102. A memory cell of a dynamic RAM formed by one capacitor selected in a memory cell group 205 is charged, and multivalued information of two bits or more is written. When this information is read out, a storage signal decision circuit 106 supplies a potential corresponding to that of the memory cell to a bit line and a bus line, referring to plural voltages set by a comparison voltage generator circuit 107 formed by plural dynamic cells for charging an output of a plural reference potential generator circuit 101 to a capacitor. As soon as the storage content is read out through an output converter circuit 104, the memory cell is refreshed. By this multivalued system the storage capacity can be substantially increased with the same chip area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor memory, and in particular to a semiconductor memory with one transistor and one transistor.
The present invention relates to a method for increasing the storage capacity of a dynamic random access memory (hereinafter abbreviated as dynamic RAM) using a capacitor memory cell.

[Prior art]

The basic configuration of a conventional dynamic RAM is that, as shown in FIG.
06 and the memory cell at the address specified by the column decoder 204 is selected by the memory cell group 205, and a signal of 1 or 0 is output to the output terminal 210 via the output circuit 208 during a read operation. Further, during writing, a 1 or 0 signal input through the input terminal 209 is written into a designated memory cell via the input circuit 207.

Note that FIG. 2 shows the configuration of the memory cell. In the above-mentioned dynamic system, one memory cell consisting of one transistor and one capacitor could only store information corresponding to 1 or 0, that is, 1 bit of information. Now, dynamic RAM is required to rapidly increase its storage capacity year by year.In order to increase the number of memories, it is necessary to miniaturize the elements inside the integrated circuit in inverse proportion to the increase in storage capacity. I ended up piling up a lot of difficult questions.

〔the purpose〕

The purpose of the present invention is to increase the memory capacity by means of circuit improvements using the same conventional manufacturing technology and approximately the same step area.

[Approximately cheap]

The present invention increases the amount of information stored in one memory cell by setting the potential stored in one memory cell to a plurality of potentials exceeding two leaps.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the invention.

In FIG. 1, 201 is an address terminal, 202 is an address circuit, 206 is a row decoder, 204 is a column decoder, 2
05 is a memory cell group. The above components 201 to 205 are common components to the conventional dynamic ram. Now, the characteristic circuit of the present invention is a circuit in a single-point chain circuit 109, in which 101 is a plurality of reference potential generation circuits, 102 is an input inverse circuit, 106 is an input terminal, 104 is an output conversion circuit, 1
05 is an output terminal, 106 is a storage signal determination circuit, 107 is a comparison voltage generation circuit, and 108 is a selection potential supply circuit.

Next, the functions of the circuits of each block 101 to 108 and a specific circuit example are shown in 11@.

The multiple potential generation circuit 101 generates potentials corresponding to more than two potential levels stored in the memory cells, and a ratio f potential used in the comparison voltage generation circuit 107 and the output conversion circuit 104. FIG. 2 shows a specific circuit example of the multiple reference potential generation circuit 101 when one memory cell stores 2 bits of information.

The following concrete circuit diagrams 2.3.4.5.6.7 show examples in which one memory cell stores 2 bits of information. Second
In the example shown in the figure, g, +VDDSE, is set as -yss, and by resistance division, g, ,"!,g,, ,"23,
It produces E34. Here KI>Ki2> m
There is a relationship of t>Ews,>J>l1184>F'4, Et, )lj2, Tj2B, and W4 correspond to the potential level of the memory cell, and at ℃12, g
, 3, "!14 is used for comparison potential.

The input conversion circuit 102 is a circuit that converts a digital signal input from an input terminal 103 into a potential level of a memory cell. FIG. 3 shows a specific circuit example of the input conversion circuit 102. The 2-bit signal input through the input terminals 117 and 118 is sent to TD1- by the decoder shown by the dashed line 119.
W4 is selected and the selected potential appears at the terminal 124 following the null line. Note that E1 to E4 in FIG.
# is continued in E1 to E4 in the figure, respectively. Also, input terminal 1
17.118 signals (0,0), (0,1), (1,0
)(1,1) are sequentially E4, E3, E at terminal 124.
2. Converted to EI.

5- The output conversion circuit 104 converts the output signal represented by the potential level coming from the pass line into a digital signal and outputs it to the output terminal 105. FIG. 4 shows a specific circuit example of the output conversion circuit 104. In Figure 4, 1
Reference numerals 64, 135, and 136 are comparators, and terminals 130 connected to the reference terminals are connected together, and potentials -2, 2B, and !14 are applied to the comparison terminals, respectively.

A dashed line 129 is an encoder, and 137.13B is an output terminal. In the circuit of FIG. 4, the output signal of
,'E'2n,F! 84, and the encoder 129 is configured to convert the result into a digital signal corresponding to 1, K2, EI, and "4" and output it to the output terminal 1!17.13B.

The storage signal determination circuit 106 compares the signal of the selected memory cell in the cell group 205 with the memory signal lI! f
This circuit detects the potential stored in the memory cell by comparing it with the signal supplied from the 8107.

Figure 5 shows the memory signal judgment time W! Specific circuit example of r106
6-. In FIG. 5, the circuit inside the dashed line 169 is a sense amplifier circuit consisting of a circuit in which the gates and drains of transistors 151 and 152 are connected to each other in a raccoon-like manner, and the terminal 143 is connected to the bit line of the memory cell. The transistors 144-145, 146 are connected to one end of a sense amplifier having a terminal 140, 141, 142 at one end, respectively. terminal 14
The potentials generated by the comparison voltage generation circuit are applied to 0.141 and 142, respectively. In the circuit shown in Figure 5, terminal 1
The bit line signal input from 46 is DMI in three sense amplifier circuits 169.

It is compared with DM2 and DM3 city rank, and the comparison result is terminal 1.
Signal 01% C2, C1 at 48.149.150 respectively
is output as Here, the bit line signals, that is, the signal information of the memory cells are compared, and C1, C2, C3
This means that it is detected as a signal. Note that transistor 1
44, 145, and 146 are the input terminals of the bit line @# sense amplifier and are disconnected from the terminal 143.

The ratio e-voltage regeneration l@107 is a circuit that supplies a comparison voltage to the storage signal determination circuit 106. FIG. 6 shows a specific circuit example of the comparison voltage generation circuit. In FIG. 6, transistors 155, 156, 157 correspond to the transistors of the memory cell, and capacitors 167, 168, 169 correspond in principle to the capacitors of the memory cell. Transistors 15B, 159.160 have g, , , E, respectively.
8, E3. It is used to charge the potential of . Now, when the charge stored in the capacitor of the memory cell is read out and placed on the bit line, it is diffused due to parasitic capacitance, and the potential of the capacitor in the memory cell and the potential on the bit line are different. In order to obtain a potential for comparing the potentials on this bit line, the circuit of FIG. 6 uses a comparison potential.1. b...
, K34 is once charged into the capacitor by the control signal 9 times, and then discharged by the control signal ψ2, the comparison value DM, .
DM, , DM8 are outputted and used in the storage signal determination circuit shown in FIG.

The selection potential supply circuit 108 is a circuit that provides a potential corresponding to the bit line based on the result of determining the potential of the memory cell by the storage signal determination circuit 106. FIG. 7 shows a specific circuit example of the selection potential supply circuit ins. Terminal 17 in FIG.
1.172.173 are given the respective signals C1, C2, and C3 obtained by the storage signal determination circuit shown in FIG.

170 is a decoder, and the output of this decoder causes transmission gates 179.180.181.1
82 is controlled, and a potential of J-%-E is selectively supplied to a terminal 178 connected to the bit line and the pass line.

The multivalued dynamic RAM of the present invention is basically configured by the above circuit. Next, the circuit operation of the present invention will be explained. The essential operations for the dynamic RAM are the u+g read operation, (Ifl write operation, and wholesale refresh operation. Therefore, these six operations will be explained. First, read In operation, the memory cell selected by the address releases one accumulated load to the bit line, and the 1112 billion signal determination circuit 106 refers to the plurality of comparison voltages obtained by the comparison voltage generation circuit 1079-. The selected potential supply circuit 108 supplies a potential corresponding to the potential of the memory cell to the bit line and the pass line.The potential supplied to the pass line is applied to the output conversion circuit 1.
04 into a 2-bit signal and output to the output terminal 105.
It is output from

- The memory cell is charged again with the original signal potential by the potential supplied to the 10,000-pit line, and information is secured. The above is the read operation. Next, in a write operation, a digital signal is input from the input terminal 106 to the memory cell selected by the address, and the input conversion circuit 102
This is completed by converting the voltage into a corresponding potential and charging the memory cell with that potential. For the fresh refresh operation, it is sufficient to stop the output from the output terminal during the read operation. As described above, it has been found that the multivalued dynamic RAM of the present invention can perform the three basic operations of the dynamic RAM without any problems.

Furthermore, it is clear that the above can be easily extended even when the number exceeds 2 bits.

-10- [Effect] As described above, the present invention has one transistor and one capacitor.
Since more than 1 bit of information can be stored in a memory cell, I
It is possible to provide a circuit that can double the storage capacity in the same chip area using the same manufacturing technology as TyI, and is particularly suitable for a dynamic RAM having an input/output configuration of 2 bits or more.

[Brief explanation of the drawing]

FIG. 1 shows the basic configuration of the multi-level dynamic random access memory of the present invention. FIG. 2 is a block diagram showing a specific circuit example of the evening voltage quasi-potential generation circuit used in the present invention, and FIG. 6 is a specific circuit example of the input conversion circuit used in the present invention. 4 is a diagram showing a specific circuit example of the blade conversion circuit used in the present invention, FIG. 5 is a diagram showing a specific circuit example of the storage signal determination circuit used in the first part of the present invention, and FIG. 7 is a diagram showing a specific circuit example of the comparison voltage generation circuit used in the present invention, FIG. 7 is a diagram showing a specific circuit example of the selection potential supply circuit used in the present invention, and FIG. FIG. 9 is a block diagram showing the basic structure of a dynamic random access memory, and is a diagram showing the structure of a memory cell consisting of one transistor and one capacitor. DESCRIPTION OF SYMBOLS 101...Number-based enemy position generation circuit, 102...Input conversion circuit, 106...Input terminal, 104...Deba conversion circuit 105...Output terminal, 106...Note 1 Keishin-
¥j judgment circuit, 107... comparison voltage generation circuit, 108
...Selection potential supply circuit, 125-128...Transmission gate, 161-133...Comparator, 144.145.146.155.156.157.
158.159.160.211... MO8h transistor, 167.168.169.212... Capacitor, 170... Decoder, 179-183... Transmission gate, 201... Address terminal, 20
2... Address circuit, 206... Row decoder, 20
4... Column decoder, 205... Memory cell group, 20
6...Sense amplifier 101 path, 207...Input circuit, 208...Output circuit, 209...Input terminal, 21
0... Output terminal, 213... Word line, 214
...Bit line, 109...Visibility between the circuit of the present invention and the circuit common to the conventional circuit, 119...Decoder, 129
... Encoder, 139 ... Sense amplifier, 151
．． 152...MOS) transistor. Applicant: Tsutomu Mogami-13- ~ Yako, Patent Attorney, Patent Attorney, Vagina Hashikosha Co., Ltd.

Claims (1)

[Claims] In a dynamic random access memory in which one memory cell is composed of a transistor and one capacitor, there is provided a plurality of reference potential generation circuits that generate a plurality of reference potentials between yss, which is a negative electrode, and +VDD, which is a positive electrode, and the plurality of reference potential generation circuits. A comparison voltage generation circuit consisting of a plurality of dummy cells that charges a plurality of capacitors with a plurality of potentials, and a storage signal determination circuit that compares and determines a plurality of voltages generated by the comparison voltage generation circuit and a signal voltage read from a memory cell. and a selection potential supply circuit that again supplies the signal level detected by the storage signal determination circuit to the bit line of the memory cell.
comprising at least an output conversion circuit that converts the output signal supplied by the selected potential supply circuit into an external output signal, and an input conversion circuit that converts an input signal from the outside into a potential corresponding to the input signal, 5. A multi-level dynamic random access memory characterized in that it is configured to store more than one bit of information in one memory cell consisting of one transistor and one capacitor.