JPH0265268A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a latch-up from occurring and an unnecessary coupling between a power current and an inner circuit by a method wherein a semiconductor substrate is so constituted as not to serve as a path of the power current. CONSTITUTION:Provided that a control signal 115 is at '1' level and a reset signal 116 is at '0' level. Here, when the control signal 113 changes at '0' level, a PMOS transistor 102 is turned ON and an NPN transistor 101 is also turned ON. At this time, a power current is supplied from an outer power terminal 111 to an inner circuit 130. Voltage Vout of an inner power output is represented by a formula, Vout=VIN-VBE-VLrp/beta, where VIN denotes the voltage of a terminal 112, VBE is the voltage between a base and an emitter of the NPN transistor 101, rp is the ON-resistance of the PMOS transistor 102, beta is an amplification factor of the NPN transistor 101, and a current IL is a load current. By making the third term of the above formula small enough, an voltage can be optically set inside an integrated circuit chip 100 through varying the voltage of the outer terminal 112.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit that includes an internal voltage generating means for generating an internal voltage lower than an externally supplied power supply voltage and using it as a power source for an internal circuit. related to semiconductor integrated circuits.

[Prior Art] In general, semiconductor integrated circuits, as typified by CMOS transistors, use a 5V power source as their operating power source.

On the other hand, as the miniaturization of each element progresses, the electric field inside the element also increases. This may cause fluctuations in the threshold voltage vth of the MOS transistor, occurrence of punch-through, etc., and may have a serious effect on the performance and reliability of the device. teeth,
It has become difficult to operate with a 5V power supply, and it is predicted that a power supply of about 3.3V will be used.

However, at present, general electronic circuits still use a standard power supply of 5V, so semiconductor integrated circuits input a voltage of 5V and operate internal circuits that internally generate a lower voltage. It becomes necessary to do so.

FIG. 12 is a configuration diagram showing an example of a conventional semiconductor integrated circuit incorporating such an internal voltage generation circuit. In the same figure, 1200 is a semiconductor chip, 1201 is an NPN
Transistor (hereinafter referred to as NPN). 1202 is NP
N parasitic collector resistance, 1203 external power input terminal,
1204 is voltage detection means consisting of resistors R1, R, 12
05 is an amplifier 1206 is a reference voltage generator, 1207 is P
Channel MOS transistor (hereinafter abbreviated as PMO8)
Ml and N-channel MoS transistor (hereinafter referred to as NMO8)
Cw is a capacitance due to internal wiring or a capacitance formed internally.

This circuit compares the output of the reference voltage generator 1206 and the output of the voltage detection means 1204, and uses the output of the amplifier 1205 to
By controlling the base potential of PNI 201, V
An output voltage of out≠VREF is obtained.

Figure 13 shows the circuit in Figure 12 (7) NPN and PMO8°N.
The cross-sectional structure of MO8 is shown. In the figure, 1300 is an N-type semiconductor substrate, 1301 and 1302 are P-type wells,
NPN has an N-type substrate 1300 as a collector and a P-type well 13
01 as the base and the N raw mineral dispersion layer 1303 as the emitter, and the N raw mineral dispersion layer 1304 and the P raw mineral dispersion layer M1305 serve as the collector and base electrodes, respectively. , LaO2,130
7 is an NPN collector parasitic resistance, which corresponds to the resistor 1202 in FIG.

PMO8 is formed using the P raw mineral dispersion layers 1308 and 1309 as source and drain electrodes, and the polysilicon 1310 as a gate electrode. Also, NMO8 is P-type well 1
302 is used as a substrate, N raw mineral dispersion layers 1311 and 1312 are formed as drain and source electrodes, and polysilicon 1313 is used as a gate electrode.

Further, FIG. 14 is a configuration diagram showing another example of a conventional semiconductor integrated circuit incorporating an internal voltage generation circuit. In the same figure, 1400 is a semiconductor chip, 1401 is a PNP transistor (hereinafter referred to as PUP), and 14.02 is a PNP transistor.
NP parasitic collector resistance, 1403 is an external power supply input terminal, 1404 is a voltage detection means consisting of resistors R1°R2,]
-405 is an amplifier, 1406 is a reference voltage generator, 140
7 is an internal circuit consisting of PMO8Ml and NMO8M2, C
w is a capacitance due to internal wiring or a capacitance formed internally.

This circuit compares the output of the reference voltage generator 1406 and the output of the voltage detection means 1404, and outputs P at the output of the amplifier 14O5.
By controlling the base potential of NP1405, V
Out 4 V REF output voltage is obtained.

Figure 15 shows the PNP and PMO8°NMO of the circuit in Figure 14.
8 is shown. In the figure, 1.500 is a P-type semiconductor substrate, 1501 and 1.502 are N-type wells,
PNP has a P type substrate 1500 as a collector and an N type well 15
01 as a base, P raw mineral dispersion layer 1503 is formed as an emitter, P raw mineral dispersion layer 1504, N raw mineral dispersion! 1505 each consists of a collector electrode and a base electrode. 1506.15
07 is a collector parasitic resistance of the PNP, which corresponds to the resistance] 402 in FIG.

NMO8 is formed using the N raw mineralization layers 1508 and 1509 as source and drain electrodes, respectively, and the polysilicon 1510 as a gate electrode. In addition, PMO8 is an N-type well 15
02 as a substrate, P raw mineral dispersion layers 1511 and 1512 as train and source electrodes, and polysilicon 1513 as a gate electrode.

[Problem to be solved by the invention]

The internal voltage generating circuit built into the semiconductor integrated circuit is required to meet at least the following conditions.

1) Do not use the semiconductor substrate as a path for electrical current.

However, as the power supply current flows through the semiconductor substrate, the substrate potential fluctuates, causing latch-up or unnecessary coupling to internal circuits.

2) When the internal voltage generation circuit supplies a predetermined load current, the difference with the external power supply voltage must not become excessive.

However, if the internal voltage is 3.3v, for example, 5v
In order to use an external power supply of 1.7 cm, a voltage drop of only 1.7 cm is allowed. Otherwise, a non-standard power supply higher than 5V would be required.

3) If noise is superimposed on the output of the internal voltage generation circuit due to switching of the internal circuit that acts as a load, the noise must be effectively removed.

This is because the switching speed of internal circuits increases due to miniaturization and higher performance of elements, and the switching noise superimposed on the power supply also increases.

On the other hand, since the noise margin of internal circuits decreases due to a decrease in power supply voltage, it is essential to effectively remove power supply noise.

As is clear from the above, in the configuration shown in FIG. 13, the power supply current path from the external power supply VIN to the internal power supply Vout is first
It is formed in

Furthermore, since the semiconductor substrate 1300 is normally of low concentration, the collector parasitic resistance 1"C□1r+4 becomes large. This collector parasitic resistance rcl.

It is desirable to suppress re2 to a predetermined value or less for the following reasons. That is, FIG. 16 shows a model of a voltage drop section in which VIN is an external power supply input and Vout is an internal power supply output. In this case, the conditions for maintaining the NPN transistor 1601 in the active state (non-saturated operating region) are VIN≧Vout+BBE+IL・re,
FIG. 17 shows the relationship between the lower limit value of external power supply VrN and load current IL, using collector parasitic resistance rc as a parameter. From the same figure, for example, external power supply v
When In=5V and internal power supply Vout=3, 3V, in order to flow the load current I+ of 100mA, the collector parasitic resistance rc needs to be 10Ω or less.

The same thing can be said about the configuration shown in FIG.

Therefore, the present invention was made based on such circumstances, and an object thereof is to provide a semiconductor integrated circuit that prevents latch-up and unnecessary coupling to internal circuits. That is.

Another object of the present invention is to provide a semiconductor integrated circuit that enables voltage control, on/off control, etc. of an internal power supply.

[Means to solve the problem]

In order to solve such problems, the present invention.

In a semiconductor integrated circuit comprising an internal voltage generating means for generating an internal voltage lower than an externally supplied power supply voltage and using it as a power source for an internal circuit, the internal voltage generating means comprises a P
It is composed of an NPN transistor formed on a type semiconductor substrate and a PMOS transistor formed on an N type island, and the collector of the NPN transistor and the PMOS8+
- The source of the transistor is connected to the external power supply terminal, the drain of the PMOS transistor is connected to the base of the NPN transistor, and its gate is connected to the control signal terminal, and the emitter of the NPN transistor is connected to the internal power output terminal. At the same time, the current path flowing through the external power input terminal and the internal power output terminal is formed as an N-type layer.

Furthermore, in the basic configuration described above, the output of the internal voltage generating circuit is led out to an external pin outside the semiconductor integrated circuit.

Furthermore, in the basic configuration described above, a switching means that is controlled on and off by an external control signal is provided between the internal power supply and the reference potential, and when the switching means is on, the internal power supply potential is set to the reference potential or a potential close to it. It was designed to switch to .

[Operation] The semiconductor integrated circuit configured in this manner has an NPN transistor and a P
Since the MOS transistors are each formed on an N-type island, the path of the power supply current can be limited to the N-type island.

In addition, the PMoS transistor that supplies the base current to the NPN transistor has an external power input input to its source and an on/off control signal to its gate, so it can perform internal power voltage control functions, on/off control functions, etc. You will be able to do this.

By adopting a configuration in which the output of the internal voltage generation circuit is led out to an external pin, it is possible not only to remove internal power supply noise by adding an external bypass capacitor, but also to monitor the status of the internal power supply voltage and connect it to other semiconductor integrated circuits. This makes it possible to supply power, etc.

Furthermore, by providing a circuit that resets the output of the internal voltage generation circuit, it becomes possible to perform power supply sequence control that controls the order in which power is turned on and off for a plurality of semiconductor integrated circuits.

〔Example〕

FIG. 1 shows a first embodiment of a semiconductor integrated circuit according to the present invention. In the figure, 100 is an integrated circuit chip, ], 0
1 is an NPN transistor whose collector is connected to an external power supply 111 and its emitter is connected to an internal power supply output 140; 102 is a PMOS transistor 103 whose source is connected to the external power supply 112; its gate is a control signal 113; and its drain is connected to the base of the NPN transistor 101. Source is external power supply 114
, a PMOS transistor whose gate is connected to the control signal 115 and whose drain is connected to the base of the NPN transistor 101, 104 and 105 are NMOS transistors connected in series between the base of the NPN transistor 101 and the reference potential Vss, and whose gates are connected to the control signal 115. 113 and 115. 120 is a set circuit that switches the internal power supply output 140 to a low potential, and the collector is connected to the internal power supply output 14. O, NPNI-transistor 121 whose emitter is connected to the reference potential Vss and NM whose drain and source are connected to the collector and base of the NPN transistor 121 and whose gate is connected to the reset control signal 116;
It consists of an OS transistor and a resistor 123 connected between the base and emitter of an NPN transistor 121. 130 is an internal circuit that operates using the internal power output 140 as a power source, and includes a PMOS transistor 131, NM
An example of an inverter circuit consisting of an OS transistor 132 is shown.

Next, the operation of this circuit will be explained. Now, terminal 111.
First, second, and third voltages are applied to the terminals 112 and 114, the control signal 115 is at the II II I+ level, and the reset control signal 116 is at the "0" level. At this time, when the control signal 113 becomes "O" level, the PMOS transistor 102 is turned on, supplying the base current to the NPN transistor 101, and the NPN transistor 101 is turned on. However, at this time, a power supply current is supplied from the external power supply terminal 111 to the internal circuit 130 through the NPN transistor 101. At this time, internal power supply output 140f7) voltage Vo
ut is the voltage at the terminal 112, VtN, the voltage between the emitters of the NPN transistor 101 is VBB, and P M
Letting the on-resistance of the OS transistor 102 be rp, it is as follows.

Vout=Vui-VBE --Ibrp --
(1) β Here, β: Current amplification factor of the NPN transistor 101: Load current Therefore, if the above third term is designed to be sufficiently small, the internal voltage V out will be
02 source voltage and the VB of the NPN transistor 101
It can be determined by E.

This means that any voltage can be set inside the integrated circuit chip 100 by changing the voltage on the external pin 112.

Similarly, when the control signal 115 is at the "02 level" and the PMOS transistor 103 is on, the voltage of the output Vout can be set by the potential of the terminal 114.The control signals 113, 115
When both are at the “1” level, PMOS transistor
2 and 103 are both off, NoS transistors 104 and 1
05 are both turned on, the base potential of the NPN transistor 101 becomes Vss level, and the NPN transistor 101 is turned off. Therefore, at this time, the power supply from the external power supply terminal 111 to the internal circuit 130 is stopped. At this time, the potential of the internal power supply decreases to the reference potential Vss at a speed determined by the time constant of the load circuit. That is, N
It is difficult to control the rate of decrease in the power supply potential just by turning off the PN transistor 101. For this reason 12
0 is an internal voltage reset circuit to solve this problem, and when the reset control signal 116 is set to ll I II, the NMOS transistor 122 and the NPN transistor 1
21 is turned on and quickly switches the internal voltage level to the level of Vss.

The terminal 110 is provided to draw out the internal voltage to the outside of the integrated circuit chip, and by providing this terminal, various applications such as removing noise from the internal power supply and monitoring and controlling the state of the internal power supply from the outside can be performed. can do.

FIG. 2 shows an NPN transistor 10 which constitutes the main part of the invention shown in FIG.
The device cross-sectional structure of the O8I-transistor 104 is shown.

In the figure, 201 is a P-type semiconductor substrate, and N-type wells 204 and 205 have N0 buried layers 202 and 203.
is formed. The NPNI-transistor 101 is formed using the N-type well 205 as a collector, the P-type diffusion layer 206 as a base, and the N raw mineralization layer 207 as an emitter electrode, and the base electrode is taken out from the P raw mineralization layer 208. The collector electrode is taken out from the N raw mineralization layer 209, and a deep N4 diffusion layer 210 connecting the N+ collector electrode 209 and the N+ buried layer 203 is formed.

The N0 buried layer 203 and the N mineralized layer 210 are necessary to reduce the collector parasitic resistance. Further, the collector is electrically isolated from the P-type semiconductor substrate 201.

PMO8) - The transistor 102 has the P raw mineral dispersion layer 211 as the source, the polysilicon 212 as the gate, and the P raw mineral dispersion layer 213
is formed as the drain, and the PMOS transistor 10
The N-type well 204 serving as the second substrate is connected to the external power source 111 through the N-mineralized layer 214. The NMOS transistor 104 is formed using the N raw mineralization layer 215 as a drain, the polysilicon 216 as a gate, and the N raw mineralization layer 217 as a source. Note that the substrate of the NMOS transistor 104 is common to the substrate 201 of the chip, and is connected to the reference potential Vss through the P mineralization layer 218.

FIG. 3 shows a second embodiment of the semiconductor integrated circuit according to the present invention. In the figure, 300 is a semiconductor chip, 301 is an NPN transistor whose collector is connected to an external power supply terminal 311 and its emitter is connected to an internal power supply output 320, and 302 is an NPN transistor whose collector and emitter are respectively connected to the collector and base of NPN transistor 301. ,3
03 is a PMOS transistor whose source is connected to the external power supply terminal 312, the gate is connected to the control signal 24= the terminal 313, and the drain is connected to the base of the NPN transistor 302; 304 and 305 are PMOS transistors whose respective drains are connected to the base of the NPN transistor 302 and the
The NMOS transistors are connected to the base of the N transistor 301, have gates commonly connected to the control signal terminal 313, and have respective sources connected to a reference potential. 306
307 is an internal circuit, 307 is a voltage reset circuit, and 314 is a reset signal terminal. Further, 310 is a terminal for leading the internal power output to the outside of the semiconductor chip.

Next, the operation of this circuit will be explained. Now, terminal 311.
1st on 312. The second power supply is applied, and the reset signal 3]-4 is set to the x'Ort level.

At this time, when the control signal 313 reaches the II OI+ level, the PMOS transistor 303 is turned on, supplying a base current to the NPN transistor 302, the NPN transistor 302 is turned on, and the NPN transistor 301 is also turned on. Therefore, at this time, power supply current is supplied from the external power supply 311 to the internal circuit 306 through the NPNI-transistor 301. At this time, internal power output 320
The voltage Vout is as follows, where Vui is the voltage at the terminal 312, V Bp is the voltage between the NPN transistors 301 and 302 (7), and rp is the on-resistance of the PMOS transistor 303.

Vout=VxN-2VBE--Ibrp--
(2) β2 Here, β: NPN transistor 301°302
Current amplification factor IL = load current Therefore, if the third term in the above equation is designed to be sufficiently small, the internal voltage Vout will be reduced by the PMOS transistor 30.
2 source voltage and NPNt-transistor 301, 30
It can be determined by the base-emitter voltage of 2.

For example, if VIN=5V and VBE=0, 8V, then Vout valves 3 and 4V will be turned on.

When the control signal 313 becomes “1” level, the PMOS transistor 303 is turned off and the NMOS transistor 3
04. ,．． 305 is turned on. Therefore, NPN transistors 301 and 302 are also turned off, and power supply from external power supply terminal 311 to internal circuit 306 is stopped. 307 corresponds to 120 in FIG. 2, and when the reset signal 314 is set to "1" level, the internal voltage 320
This is a voltage reset circuit that quickly switches the level of Vss to the level of Vss. 110 is a terminal for leading out the internal voltage to the outside of the integrated circuit chip.

FIG. 4 shows a third embodiment of a semiconductor integrated circuit according to the present invention. In the same figure, 400 is a semiconductor chip, 4.01
, 402, 4.03 are shown in FIG. 1, for example.

This is an internal voltage generation circuit as shown in FIG.
Input the external power supply from 0 to Vc and vcl, and output the same voltages 4.21, 422, and 423 from 1. Also,
These outputs are commonly connected internally and are connected to internal circuit 4.
．． Delivered on 07, 4.08, 409. 401-40
3 C□ is an on/off control terminal, and in this example, V
ss to keep 401 to 4.03 always active, but there is no particular limitation, and they may be connected to external pins for on/off control. 4-0
Reference numerals 4 to 406 are voltage reset circuits shown, for example, at 120 in FIG. 1, which are turned on or off depending on the level of the reset signal terminal. When these are on, 401
The output of ~403 ■0 is switched to Vss level, and when off, the output of 401 ~ 403 is the input power supply voltage 410
Outputs a lower constant voltage and internal circuits 407 to 409
supply to. 412 is a terminal for leading out the internal voltage to the outside of the semiconductor chip. Internal circuit 4 for internal power supply
High-frequency noise is generated by switching between 07 and 409, but since miniaturized devices that operate at low voltages have a reduced noise margin, it is essential to effectively remove power supply noise for safe operation without malfunction. be. Inserting a bypass capacitor between the power supply and Vss is effective in removing high-frequency noise, but in semiconductor integrated circuits that include conventional internal voltage generation circuits, it is difficult to incorporate large-capacity capacitors inside the chip. Since it is impossible in terms of area, it is almost powerless to eliminate power supply noise.

However, in this embodiment, the output of the internal voltage generation circuit is led out to the external terminal 412 for the purpose of solving this problem and for other purposes. 413 is a bypass capacitor connected between the terminal 412 and GND. in this way,
Since the bypass capacitor can be attached externally, the capacity of the bypass capacitor 412 can be freely selected according to the noise of the internal power supply, so that the internal power supply noise can be effectively removed.

Therefore, the internal circuits 407 to 409 can operate with high reliability without being affected by noise.

Further, in this embodiment, a plurality of internal voltage generation circuits 401 to 4
Since the outputs of the circuits 03 are commonly connected, the internal circuits 07 to 409 can always operate under the same power supply voltage even if there are variations in their respective output voltages. Therefore, variations in operating speed between internal circuits due to variations in power supply voltage are eliminated. Furthermore, mismatch in power supply voltages between circuits is one of the major causes of latch-up in CMOS transistor circuits, but this problem can also be resolved.

FIG. 5 shows a fourth embodiment of a semiconductor integrated circuit according to the present invention. In the figure, 501 to 503 are integrated circuit chips, respectively, and input terminals 521 to 523 of an external power supply 510
．． Reference potential terminals 531 to 533, internal voltage output terminal 54
1 to 543, each having an internal voltage generating circuit 50.
4 to 506, and supplies power to respective internal circuits 507 to 509.

In this embodiment, each internal voltage generation circuit 504 to 506
supplies power to each of the internal circuits 507 to 509, is taken out to external terminals 541 to 543, and is connected to external wiring 5.
11 and are commonly connected. This has the advantage that the internal circuits 507 to 509 of the plurality of semiconductor chips can operate under exactly the same power supply conditions. Further, although the power supply current of each internal circuit changes from moment to moment, this embodiment has the advantage that when the power supply current of a certain chip increases, it is possible to accommodate the power supply current from other chips.

Note that capacitors 513 to 515 connected between the respective terminals 541 to 543 and the reference potential are bypass capacitors for removing high frequency noise.

FIG. 6 shows a fifth embodiment of the semiconductor integrated circuit according to the present invention. In the figure, semiconductor depths 600 to 602 include internal circuits 603 to 605, respectively. The semiconductor chip 600 includes an internal voltage generation circuit 610,
The output is supplied to the internal circuit 603 and the terminal 62
1. Internal voltage generation circuit 6] 0 is terminal 614
The operation is controlled by an on/off control signal 620, which is not particularly limited. The output of the internal voltage generation circuit is derived from the terminal 621 and is connected to the external wiring 63.
3, the power is supplied to other semiconductor chips 601 and 602. Note that 61'' to 613 are reference potential terminals, and 622 is a bypass capacitor for noise removal. According to this embodiment, since the semiconductor chips 601 and 602 do not need to include an internal voltage generation circuit,
This has the advantage of increasing the degree of integration of internal circuits.

FIG. 7 shows a sixth embodiment of the semiconductor integrated circuit according to the present invention. In the figure, 700 is an integrated circuit chip, 701
702 is an NPN transistor whose collector is an external power supply terminal 710°, whose emitter is an internal voltage output for the internal circuit 704, whose source is the external power supply terminal 711, whose gate is connected to the control signal 712, and whose train is the NPN transistor 7.
PMOS transistor connected to the base of 01, 70
3, the drain is the base of the NPN transistor 701,
It is an NMOS transistor whose gate is connected to the control signal 7]2 and whose source is connected to a reference potential. Further, 720 is a stabilized power supply provided externally, and its output is connected to the external power supply terminal 711 of the semiconductor chip 700. moreover,
The internal power supply output led to the terminal 713 is the stabilized power supply 72
By monitoring the voltage, the stabilized power supply 720 controls the output voltage to the terminal 711 so that it becomes a predetermined voltage. Note that 714 is a bypass capacitor for removing high frequency noise.

According to this embodiment, high-frequency power supply noise is removed by the bypass capacitor 714, and slowly fluctuating internal voltage can be compensated for by controlling the output potential of the external stabilized power supply. It has the advantage of being able to supply

FIG. 8 shows a seventh embodiment of a semiconductor integrated circuit according to the present invention. In the figure, reference numerals 801 and 802 are internal voltage generation circuits, and their respective outputs are supplied to internal circuits 803 and 804. 810 is an external power supply terminal, 811
is a reference potential terminal, and 812 is a lead-out terminal of the internal voltage generation circuit 802 to the outside. A diode and an external power supply 830 are connected between the terminal 812 and the reference potential. Further, 840 is a bypass capacitor connected between the terminal 812 and the reference potential.

According to this embodiment, there is an advantage that the terminal 812 can also serve as a power supply terminal from the external power supply 830. Although not particularly limited, when the power supply voltage of the internal circuit 804 consisting of a memory element falls below a predetermined value, Power is supplied from a power source 830, and the memory contents can be saved.

FIG. 9 shows an eighth embodiment of a semiconductor integrated circuit according to the present invention. In the figure, 900 is a timing control circuit;
01-903 are integrated circuit chips, which include internal voltage generation circuits 911, 921, 931 and internal circuits 941-94, respectively.
It has 3. 901 to 903 are external power supply Vcc,
A reference potential Vss is connected, and on/off control signals 01 to C1 are input from a timing control circuit. Also, 90
1 to 903 are connected by a control line 961 and a data line 962.

The timing control circuit 900 includes integrated circuit chips 901 to 9
In order to control the power-on and power-off sequence of each of the power supply units 03 and 03, timing signals such as those shown in C□ to C3 in FIG. 10 are generated, for example.

As a result, internal power supply circuit 911. ．． The output voltages v1 to v3 of 921 and 931 are turned on and off in a timing sequence as shown in FIG.

According to this embodiment, internal voltage generation circuits 911, 921.
Since 931 itself has an on/off control function,
It has the advantage that the sequence of power-on and power-off between multiple integrated circuit chips can be controlled freely by an external timing control circuit, and can provide useful functions for system applications.

A ninth embodiment of the semiconductor integrated circuit according to the present invention is shown in FIGS. 11(a) and 11(b). In the figure, 1100 is a multi-value memory cell for storing multi-value information, and is composed of a MOS transistor 110 and a capacitor 1102.

The read operation of this cell is as follows. Word line W
When the potential of the word line WL is increased in a stepwise manner, M
The OS transistor 1101 turns on and lowers the pins 1 to BL, which have been precharged to a high level, to a low level. A sense circuit 1103 detects this, and a binarization circuit 1104 converts its output into binary information. By the way, in this case, since the potential of the word line WL has to be increased in a stepwise manner as described above in order to read the multilevel memory, there is a problem that the read time becomes extremely slow. For this reason, the word line WL,
The key to high-speed readout is how quickly the multi-stage switching of the potential can be made.

Therefore, 1110 is a reference voltage generation circuit, Vo, V
□,...l Vl41 Generates power of Vts. These voltages are applied to PMOS transistors 1120-1-12.
Connected to 5 sources. The gates of the PMO 81 to transistors 1120 to 1125 are supplied with a timing signal ψ. ,ψ
4. ..., ψ14. ψ1. , and their drains are connected in common to the base of the NPN transistor 1130. 1130 is an NPN transistor whose collector is connected to the power supply V+ and whose emitter is connected to the word line WL. ψ the timing signal. , ψ□,..., ψ11. ψ1.
When the transistors are energized in this order, the PMO8+MOS transistors 1101, 1122, . According to such an embodiment, the word line WL is driven by an emitter follower circuit of the NPN transistor 1130, and a large load (not shown) on the word line WL can be driven at high speed, so that multi-level memory can be read at high speed. There are advantages. Also, the potential of the word line is the reference potential V. , Vl.

V 2 T ”' l Vl41 V, 5 and NPU 1
130(7) has the advantage of being determined only by VBE.

In addition, in the figure, NMOS transistors 1126 and 1127
are for switching the potentials of the base of the NPN transistor 1130 and the word line WL to the Vss level in accordance with the control signal Rs.

〔Effect of the invention〕

As is clear from the above-1- explanation, according to the semiconductor integrated circuit according to the present invention, since the semiconductor substrate is not used as a path for power supply current, it may cause latch-up or damage to internal circuits. This makes it possible to prevent unnecessary connections from occurring.

In addition, voltage control and on/off control of the internal power supply become possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a second embodiment of a semiconductor integrated circuit according to the present invention, FIG. 2 is a diagram showing a cross-sectional structure of the device in FIG. 1, and FIG. 3 is a diagram showing a second embodiment of the present invention. 4 is a block diagram showing a third embodiment of the present invention, FIG. 5 is a block diagram showing a fourth embodiment of the present invention, and FIG. 6 is a block diagram showing a fifth embodiment of the present invention. 7 is a block diagram showing a sixth embodiment of the present invention, FIG. 8 is a block diagram showing a seventh embodiment of the present invention, and FIG. 9 is a block diagram showing an eighth embodiment of the present invention. A configuration diagram showing an example,
Figure 10 is a diagram showing the operation time chart of Figure 9,
1(a) and 1(b) are block diagrams showing a ninth embodiment of the present invention, FIG. 12 is a block diagram showing a conventional internal voltage generation circuit, and FIG. 13 shows a cross-sectional structure of the device in FIG. 10. Figure, 14th
The figure shows a configuration diagram of a conventional internal voltage generation circuit, Fig. 15 shows a cross-sectional structure of the device shown in Fig. 14, Fig. 16 shows a model of a voltage drop section, and Fig. 17 shows the one shown in Fig. 16. It is a characteristic diagram of a model. 100...Semiconductor circuit chip, 101-...NPN
Transistor, 102...PMOS transistor, 1
03...PMOS transistor, ]20...Reset circuit, 130...Internal circuit.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit comprising an internal voltage generating means for generating an internal voltage lower than an externally supplied power supply voltage and using it as a power source for an internal circuit, the internal voltage generating means is a P-type semiconductor. an NPN transistor formed on a substrate;
a PMOS transistor formed in an N-type island, and the collector of the NPN transistor and the PMOS transistor are connected to each other.
The source of the S transistor is used as an external power supply terminal, the drain of the PMOS transistor is connected to the base of the NPN transistor, and its gate is used as a control signal terminal, and the emitter of the NPN transistor is used as an internal power supply output terminal. A semiconductor integrated circuit characterized in that a current path flowing through the external power input terminal and the internal power output terminal is formed as an N-type layer. 2. In claim 1, the PMOS transistor is controlled to be turned on and off by a control signal applied to the gate of the PMOS transistor, and the internal power generation circuit is controlled to be active or inactive. A semiconductor integrated circuit characterized by: 3. The semiconductor integrated circuit according to claim 2, wherein the control signal for turning on and off the PMOS transistor is supplied from outside the circuit. 4. In claim 1, N on a P-type semiconductor substrate
The NPN transistor formed on the semiconductor island has a highly doped N-type buried layer and a high-doped N-type buried layer on the main plane of the semiconductor.
1. A semiconductor integrated circuit comprising a highly doped N-type region connecting type collector electrodes with low resistance. 5. In claim 1, the transistor has a plurality of P-channel MOS transistors whose drains are commonly connected to the base of the NPN transistor 4 and whose respective sources and gates are supplied with different power supply voltages and on/off control signals, A semiconductor integrated circuit characterized in that an internal voltage is generated from the voltage supplied to the source of a PMOS transistor and the base-emitter voltage of one or more NPN transistors by switching and controlling a gate control signal. . 6. In a semiconductor integrated circuit that receives an external power source and generates an internal voltage lower than that to be used as a power source for an internal circuit, a switching means that is controlled on/off by an external control signal is provided between the internal power source and a reference potential. . A semiconductor integrated circuit device, characterized in that when the switching means is on, the internal power supply potential is switched to a reference potential or a low potential level close to the reference potential. 7. In claim 6, the switching means has a collector connected to an internal power supply and an emitter connected to a reference potential.
A semiconductor integrated circuit device comprising a PN transistor and an NMOS transistor whose drain is connected to an internal power supply, whose gate is connected to an on/off control signal, and whose source is connected to the base of the NPN transistor. 8. A semiconductor integrated circuit device which inputs an external power source and generates an internal voltage lower than that to be used as a power source for an internal circuit, characterized in that the internal power output is led to an external pin of the semiconductor integrated circuit device. Integrated circuit device. 9. A semiconductor integrated circuit comprising at least one semiconductor integrated circuit according to claim 8, characterized in that a bypass capacitor for removing high frequency noise is connected between an internal power output terminal led out to an external pin and a reference potential. circuit. 10. In a semiconductor integrated circuit device that includes a plurality of internal voltage generation circuits that input an external power source and generate a lower internal voltage to be used as a power source for the internal circuit, the outputs of each internal voltage generation circuit are commonly connected. A semiconductor integrated circuit device characterized by: 11. The semiconductor integrated circuit device according to claim 10, wherein the outputs of the commonly connected internal voltage generating circuits are led out to an external pin. 12. It includes at least one semiconductor integrated circuit device according to claim 10 or claim 11, and a bypass capacitor for high frequency noise removal is connected between the internal power output terminal led out to the external pin and the reference potential. A semiconductor integrated circuit characterized by: 13. Connect the internal power output of each of the plurality of semiconductor integrated circuit devices to an external pin, which includes at least one internal voltage generation circuit that receives an external power supply and generates a lower internal voltage to be used as a power supply for the internal circuit. What is claimed is: 1. A semiconductor integrated circuit characterized in that each external pin is connected in common with external wiring. 14. The semiconductor integrated circuit according to claim 13, wherein a bypass capacitor for attenuating high frequency noise is connected to the internal power supply output which is commonly connected externally. 15. Contains at least one semiconductor integrated circuit device having an internal voltage generation circuit that inputs an external power supply and generates a lower internal voltage to be used as a power supply for the internal circuit, and outputs its internal voltage to an external pin. A semiconductor integrated circuit characterized by supplying power to other semiconductor integrated circuits via external wiring. 16. The semiconductor integrated circuit according to claim 15, characterized in that a bypass capacitor for removing high frequency noise is connected between the internal power supply output led out to the external pin and the reference potential. 17. The semiconductor integrated circuit device according to claim 15 or claim 16, wherein the semiconductor integrated circuit device having an internal power generation circuit has a function of switching the internal power output to a reference potential level by an external control signal. integrated circuit. 18. The collector is connected to the external power supply, the emitter is connected to the internal power supply line and the external output pin, the source is connected to the output of the external stabilized power supply, and the drain is connected to the NPN transistor.
P channel M connected to the base of the PN transistor
In a semiconductor integrated circuit device including an internal voltage generator including an OS transistor and an internal circuit that operates using the output of the internal voltage generator as a power source, the output of the internal voltage generator is fed back to the external stabilized power supply, and the output thereof is A semiconductor integrated circuit device characterized in that the output of an internal voltage generating circuit is controlled to a predetermined voltage level by controlling a potential. 19. The semiconductor integrated circuit device according to claim 18, characterized in that a bypass capacitor for removing high frequency noise is connected between the internal voltage generating circuit led out to the external output pin and the reference potential. 20.Includes at least one internal voltage generation circuit that inputs an external power supply, generates a lower internal voltage and uses it as a power supply for the internal circuit, leads its output to an external terminal, and connects a diode to the external terminal. A semiconductor integrated circuit device characterized in that it is connected to a backup power source via a. 21. The semiconductor integrated circuit device according to claim 20, wherein the internal circuit operated by an internal power source led to an external pin is a memory element. 22. A semiconductor integrated circuit device according to claim 20, characterized in that a bypass capacitor for removing high frequency noise is connected between the output of the internal voltage generating circuit led out to the external pin and the reference potential. 23. A plurality of semiconductor integrated circuit devices and a plurality of semiconductor integrated circuits including an internal generation circuit that inputs an external voltage and generates a lower internal voltage in response to an external control signal to be used as a power source for the internal circuit. It consists of a timing control section that generates the operation of the internal voltage generation circuit at a predetermined timing,
A semiconductor integrated circuit characterized in that the outputs of a plurality of internal voltage generating circuits can be controlled in a predetermined sequence. 24. A multilevel memory cell whose drain is connected to a bit line, gate to a word line, and source to a charge storage capacitor.It is connected to two bit lines, and means for detecting the potential change and binarizing its output. a multilevel memory including at least means for generating a plurality of reference voltage outputs, an NPN transistor having a collector connected to a fixed power supply and an emitter connected to a word line of the memory cell; a plurality of P-channel MOS transistors whose drains are commonly connected to the base of the NPN transistor, whose respective sources are connected to corresponding outputs of the reference voltage generating means, and whose respective gates are respectively connected to timing signals having different phases; 1. A semiconductor integrated circuit, wherein a stepped voltage is generated on a word line of a memory cell by applying the timing signal to each gate in a predetermined order.