JPH0317888A - Storage device - Google Patents

Abstract

PURPOSE:To attain the making of a device into high integration and large capacity by accumulating three kinds of information in a unit storage cell and identifying them separately. CONSTITUTION:When the device is operated, transistors(TR) Q1, Q2 and Q3 are turned off with a control signal phi1, and a word line WL is selected, and a bit line BL is connected to a storage cell capacitor Co. At this time, electric charges equivalent to power source potential Vcc, ground potential and 1/2Vcc corresponding to storage information '1', '0' and '1/2' are accumulated in a capacitor part. And '1' and '1/2' are outputted as Vcc and '0' as the ground potential to a node N1 by starting up a sense amplifier SA1 by separating from the bit line BL. Next, '1' as Vcc and '0' and '1/2' as the ground potential are outputted to a node N2 by starting up a sense amplifier SA2 by separating from the bit line BL. Thereby, it is possible to identify the three kinds of information accumulated in the unit storage cell, and to make the device into high integration and large capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a memory device capable of storing three-value information in a unit memory cell constituted by one transistor and one capacitor.

Conventional technology A memory device in which a unit memory cell is composed of one transistor and one capacitor, a so-called dynamic memory device, is as follows.
The unit memory cell has a simple structure and a small number of elements, making it suitable for high integration, and advances in microfabrication technology have led to the realization of megabit-class memory cells.

A conventional storage device will be explained below. FIG. 4 shows a memory cell of a conventional memory device and its peripheral control circuit, and FIG. 5 shows a timing chart of control signals during reading of the conventional memory device. The operation of the storage device configured as shown in FIG. 4 will be explained below. First, during standby, the control signal ΦI becomes low level and the transistors Q+, Q2
．． Q3 turns on, and both bit lines BL and BL have a bit line precharge potential VBp (= 1/2Vcc
) is charged. During operation, the control signal Φ1 becomes high level, transistors Q+, Q2, and Q3 are turned off, word l$WL is selected, transistor Q4 is turned on, and the bit line BL and storage cell capacitor CO are connected. At this time, a charge corresponding to the power supply potential is accumulated in the capacitor section, which is the memory information storage section, in the case of the memory information "1", and a charge corresponding to the ground potential in the case of the memory information "O". . If the counter electrode potential VCP of the storage cell capacitor is 1/2Vcc and the storage cell capacitance is Cs, the amount of accumulated charge is 1/2VccC when the storage information is "1".
In the case of s, "O", the charge becomes -1/2VccCs, and if the bit line capacitance is CB, then this charge moves by dividing the capacitance of calCs, causing a slight displacement in the potential of the bit line BL. On the other hand, the potential of the bit line BL on the comparison reference potential side is 1/
2 It remains at Vcc and does not change. Next, sense amplifier SA
is activated by control signals Φ2 and Φ3, and bit lines BL. BL
After amplifying the minute potential difference between them, the control signal Φ10 is set to high level and the stored information is read onto the I/O line.

Problems to be Solved by the Invention However, in the above-mentioned conventional configuration, the storage information stored in the unit storage cell capacitor section is ``1'' or ``O''.
It has the problem that it can only store 1 bit of information and is not efficient in achieving higher integration and larger capacity.

Means for Solving the Problems In order to achieve this object, the memory device of the present invention has a unit storage cell capacitor section with a power supply potential representing "1" information and a ground potential representing "O" information as stored information. Accumulates the amount of charge corresponding to the third potential, and stores the main memory information as "1" above.
, "0" and is equipped with a control device to distinguish it from stored information.

Effect: With this configuration, it is possible to store ternary storage information in a unit storage cell, and it is possible to efficiently achieve high integration and large capacity of a storage device.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 1 is a diagram of a memory cell and its peripheral control circuit of a memory device according to an embodiment of the present invention, FIG. 2 is a timing chart of control signals during reading of a memory device according to an embodiment of the present invention, and FIG. 3 is a diagram of a control signal according to the present invention. 2 is a diagram showing a rewrite operation control circuit diagram of a storage device in an embodiment of the present invention. VBP is a bit line precharge potential, VCP is a storage cell capacitor counter electrode potential, WL is a word line, BL. BL is a bit line pair,
Co is a storage cell capacitor, SA+ + SA2 is a dummy word line for controlling a switching transistor for generating a sensing reference potential, CI and C2 are capacitors for generating a comparison reference potential, I/O, I/ O is a data line, Φ1 is a control signal for precharging the bit line, Φ2, Φ3, Φ6, Φ7 is a control signal for starting the sense amplifier, Φ4, Φ8 is a capacitor storage for generating a comparison reference potential. Control signals for initializing charges during standby, Φ5 and Φ9 are control signals for controlling transfer gates for time-division sensing amplification, ΦIO+Φ1
! are control signals for connecting the sense amplification output and the data line, Q+, Q2 . Q3 is a P-channel MOS transistor, Q4, Qs, Qs, Q7, Q8, Q9,
Q+o・QllI Q+2. Q+3, QI4.
Q+s, Q+e are N-channel MOS transistors, VC
C is the power supply potential, VSS is the ground potential, l is the Φ1 generation circuit,
2 is a Φ5 generation circuit.

Next, the operation of the storage device of this embodiment will be explained. First, during standby, the control signal Φ1 becomes low level and the transistor Q+. Q2 and Q3 turn on, and both bit lines BL and BL reach the bit line precharge potential Vap.
(= 1/2Vcc), and control signals Φ5,
Φ9 becomes high level and transistor Q9. Q+a,
Ql1. Ql2 is turned on and the sense amplifier output N+ .
N+, N2, and N2 also have an initial state of 1/2VCC. On the other hand, the control signals Φ4, Φ8 become high level, and the transistors Qs. When Q7 is turned on, a charge corresponding to the ground potential is accumulated in the capacitor C, and a charge corresponding to the power supply potential is accumulated in the capacitor C2. During operation, the control signal Φi goes high and the transistors Q+, Q2 . Q3 is turned off, and then word line WL is selected, transistor Q4 is turned on, and bit line BL and storage cell capacitor Co are connected. At this time, the capacitor section which is the storage information storage section has a charge corresponding to the power supply potential when the storage information is "1", and a charge corresponding to the ground potential when the storage information is "O". If the information is different from ``1'' and ``0'' (hereinafter referred to as storage information ``1/2''), a charge corresponding to 1/2 Vcc, which is half of the power supply potential, is accumulated.

The counter electrode potential vcp of the memory cell capacitor is set to 1/21/
2Vcc, and the storage cell capacity is Cs, the amount of accumulated charge is 1/2VccCs when the storage information is "1" and - when the storage information is "0".
If 1/2VccCs is "1/2", it becomes O, and if this charge represents the bit line capacitance as CB, then CB. cs
The potential of the bit line BL is 1/2Vcc+Cs Vcc/2 (Co+cs
), “O” 1/2Vcc-CS VCC/2 (
Cn+Cs), and in the case of "1/2", 1/2V
It remains cc and does not change. On the other hand, at the same time that word *WL is selected, dummy word line D W L + is selected, and the potential of bit IBL on the comparison reference potential side is set to capacitor C! If the capacitance of CO is 1/2Cs, the accumulated charge of -1/4VccCs moves by capacitance division with CO, and becomes 1/2Vcc-
Cs Vcc/4 (Cs + Cs). Next, set the control signal Φ6 to low level and connect the bit line and sense amplifier S.
After disconnecting A+, SA is set by control signals Φ2 and Φ3.
By activating + and amplifying the minute potential difference, the stored information "1" 2 "1/2" is outputted to N1 as the power supply potential Vcc, and the stored information "0" is outputted as the ground potential. Next, the dummy word &il D W L 2 is selected, and the potential of the bit line BL on the comparison reference potential side is determined by the fact that if the capacitance of the capacitor C2 is Cs, the accumulated charge of 1/2 VccCs moves by capacitance division with CB, and /2Vcc+Cs VCC/4
(CB + CS). Thereafter, the control signal Φ9 is set to low level to disconnect the bit line and the sense amplifier SA2, and then the control signal Φ6. By starting SA2 with Φ7 and amplifying the minute potential difference, the stored information "1" is stored at the power supply potential V.
As a CC, stored information "0" and "1/2" are outputted to N2 as a ground potential. Reading of stored information onto the I/O line is achieved by sequentially setting the control signals Φ10 and Φ■ to high level. To rewrite stored information, the output Nl of SA+ and SA2 is activated before the word line becomes low level.
, N2 and perform exclusive OR, and the result is “1”.
” (when the memory information is “1” or “O”), by setting the control signal Φ5 to high level, and when it is “O” (when the memory information is “1/2”), This is achieved by setting the control signal Φ1 to a low level.

Effects of the Invention As described above, according to the present invention, the storage cell capacitor section is supplied with a power supply potential which is "1" information or "O" as stored information.
The configuration includes a control device for accumulating a charge amount corresponding to a third potential different from the ground potential that is information and distinguishing this stored information from the above-mentioned "1" and "O" stored information. This makes it possible to store ternary storage information in a unit storage cell, and provides a storage device that can efficiently achieve high integration and large capacity.

[Brief explanation of drawings]

FIG. 1 is a diagram of a memory cell of a memory device and its peripheral control circuit in an embodiment of the present invention, FIG. 2 is a timing chart of control signals during reading of a memory device in an embodiment of the present invention, and FIG.
The figure is a rewrite operation control circuit diagram of a storage device in an embodiment of the present invention, and FIG. 4 is a signal dimming diagram. vsp・・・Bit line precharge potential, VCP
...Memory cell capacitor counter electrode potential, WL・
...Word line, BL, BL...Bit line pair, Co...Storage cell capacitor, SAI,
SA2...Sense amplifier, No., Φ5, Φ9...
... Control signal for controlling the transfer gate for time-division sense amplification, Φ10, ΦI1 ... Control signal for connecting the sense amplification output and the data line, Q+
,Q2,Q3...P channel MOS
Transistor, Q4. Qs. Q61 Q71 Q8
, Qs, Q+o. Qll, Ql2, Ql3I
Q+4. Q+5. Q+e...N channel M
OS transistor, VCC......power supply potential, VSS...ground potential, l...ΦI
Generation circuit, 2...Φ5 generation circuit.

Claims (4)

[Claims] (1) One end of a word selection switching MOS transistor is connected to a capacitor part and the other end to a bit line to form a unit memory cell, and the capacitor part has a power supply potential that is "1" information or "0" information as stored information. It is characterized by comprising a control device for accumulating an amount of charge corresponding to a third potential different from the ground potential, and for distinguishing the main storage information from the above-mentioned storage information of "1" and "0". Storage device. (2) In order to generate a comparison reference potential for each bit line, the control device is equipped with two sets of control circuits in which one end of a switching MOS transistor is connected to a capacitor section and the other end is connected to a bit line. The other end is set to a power supply potential and a ground potential, respectively, and the capacitance value of the capacitor part is set to be the same as the unit memory cell at one end and 1/2 of the unit memory cell at the other end. The storage device according to item 1. (3) The control device operates the two sets of comparison reference potential generation control circuits in a time-division manner to generate minute potential differences between the bit line pairs using two sets of sense amplifiers via transfer gates for each bit line pair. Claim 1 characterized in that the ternary storage information is amplified and the ternary storage information is identified based on the output state.
Storage device described in section. (4) During the rewrite operation associated with the read operation, the above 2.
Claim 1, characterized in that the sense amplifier, the transfer gate provided between the bit line pair, and the bit line precharge start timing are controlled by potential information latched in the sense amplifier pair. Storage device.