JPS63195897A - Dynamic ram device for multivalued storage - Google Patents

Abstract

PURPOSE:To shorten a rewriting time and the cycle time of reading operation by mixing sub-bit lines for dividing writing data at the time of rewriting of data, generating a writing level at a time and writing data in memory cells. CONSTITUTION:At the time of writing data from registers 66, 70, 74 again in a memory cell 17, clocks phi11, phi12 are turned to 'L' and respective sub-bit lines are separated. On the other hand, a word line WL2n is turned to 'H', word lines WL2, WL3 for non-selected block writing dummy cells are turned on and the capacity of respective sub-bit lines it set up to CB+CS. Under said status, clocks phi15, phi9 are turned to 'H' and the potential values of respective sub-bit lines are written correspondingly to the registers 66, 70, 74. The clock phi9 is turned to 'L', a transistor 19 is turned off and then the clock phi11 is turned on and the potential accumulated in the sub-bit lines are mixed with each other. Consequently, a value corresponding to the contents of the registers 66, 70, 74, i.e. rewriting, can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a multi-value storage memory circuit.

[Conventional technology]

Figure 5 shows, for example, I, S S CC85 lecture number FAM
17.5 is a basic configuration diagram of a multilevel storage memory circuit using the same memory cells as the dynamic RAM shown in 1.
is a row decoder, and 2 and 2' are bit lines.

Bit line, 3 is a memory cell, 4 is a dummy cell, 5 is a write gate, 6 is a charge transfer preamplifier, 7
is a sense amplifier, 8 is a staircase voltage generation circuit, 9 is a control register, 10 is a column register, 11 is a column I10 line, 12 is an encoder circuit, 13 is a column decoder, 14 is a data-in decoder, 15 is a word line ,
16 is a dummy word line.

Next, the operation will be explained. The memory array made up of memory cells 3 is exactly the same as a general dynamic RAM,
A differential sensing method using dummy cells 4 is used. The difference from a normal DRAM is that a staircase wave voltage Φ generated by a staircase wave generation circuit 8 is applied to the word line 15 and dummy word line 16, and information on a control pulse synchronized with ΦX (the voltage value of Φ8 is Each data line is provided with a control register 9 for controlling the associated information (corresponding information), a column register 10 for storing the information, and an encoder 12. The charge transfer preamplifier 6 is a charge transfer type preamplifier using a bias charge injection method so that the signal voltage becomes 1/(M-1) (M is the number of levels) when performing multi-value storage. This allows the connection from the node with large capacity (data line D) to the node with small capacity (data line D).
The voltage is amplified by transferring charge to the input terminal of the sense amplifier 7. The charge transfer preamplifier 6 and the sense amplifier 7 determine whether or not a charge has flowed from the memory cell to the data line each time the staircase wave Φ8 rises by one step, and input the result into the column register 10. During rewriting, the timing at which the write gate 5 opens is controlled by the information in the column register 10.

FIG. 6 is a diagram showing readout in the case of 2 bits/cell (n-2) and the voltage waveform of the data line at that time.
The figure is a diagram showing the potential of the memory cell at each time (a) to (di) corresponding to FIG. 6.

When reading information, an ascending staircase wave is applied.

Considering the case where (0, 1), that is, the second lowest voltage is stored as memory information, charge flows out from the memory cell 3 to the data line for the first time at time C.
Data line potential ■ゎ decreases.

Sense amplifier 7 detects this change, and column register 1
0 and temporarily stores digital information (0, 1).

Figure 8 shows writing in the same case < (0, 1) and the voltage waveform of the data line at that time, and Figure 9 shows each time period (e) to (h) corresponding to Figure 8. ) shows a potential diagram of a memory cell.

At the time of writing, a descending staircase wave is applied, and the information in the control register 9 and the contents in the column register 10 are compared, and when they match, the write gate 5 is turned on, and the charge on the memory cell divided bit line pair is extracted to the data line side.

These enable accumulation of each voltage ((each step voltage value of the i-stage wave) - (threshold voltage of the memory cell)).

[Problem that the invention seeks to solve]

Conventional multilevel storage dynamic RAM devices are configured as described above, and since the reading is destructive, it takes n to rewrite.
It is necessary to read out the counter register and write each level of the n-value staircase wave into the memory cell according to the contents of the register, and there is a problem in that the cycle time of the read operation is long.

This invention was made to solve the above-mentioned problems. By shortening the rewrite time, the read operation cycle time can be shortened, and the n value can be calculated without using a staircase wave. An object of the present invention is to obtain a multilevel storage dynamic RAM device that can realize bell storage.

[Means for solving problems]

The multilevel storage dynamic RAM device according to the present invention changes the potential of the bit line from which the contents of the memory cell are read out to (n-1
) reference potentials, an (n-1) bit register for storing the comparison results, and charge injection into each of the registers according to the contents of the registers when writing to the memory cell. The bit line is divided into (n-1) sub-bit lines, and a switching means is provided for connecting the sub-bit lines into one and realizing a desired voltage level on the bit line. be.

[Effect]

The multi-level storage dynamic RAM device in this invention includes:
The potential of the bit line from which the contents of the memory cell were read is set to (n-
1) Comparison means for sequentially comparing with each of the reference potentials, an (n-1) bit register for storing each comparison result, and charge injection into each according to the contents of the register when writing to a memory cell. The bit line is divided into (n-1) sub-bit lines on which data processing is performed, and a switching means is provided for connecting the sub-bit lines into one to realize a desired voltage level on the bit line. By mixing the data to be written during rewriting of (n-1) divided sub-bit lines, a level to be written at once is generated and this is written to the memory cell. It can save time,
The cycle time of read operation can be shortened.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a multilevel storage dynamic RA according to an embodiment of the present invention.
This is a block configuration diagram of the memory cell array of the M device. In the figure, 76 is a memory array section, 77 is a multilevel data readout intensifier section, 78 is a data store and input/output control section centered on a data register, and 79 is a column decoder. be. 37°38.39 are register data transfer lines to the sub-bit lines.

Further, FIG. 2 is a detailed circuit diagram of the memory array section 76, and FIG.
The figure shows a detailed circuit diagram of the multilevel data readout amplifier 77, and FIG. 4 shows a detailed circuit diagram of the data store/input/output control unit 78.
29.30 is a memory cell. 80, 81.82 are dummy cells for writing, C, , C,! ,C,,,C,,,C
, □, C23 is a dummy cell for read comparison, 54.55
is a charge transfer preamplifier, 56 is a differential amplifier, 66.7
0.74 is a register.

Next, the operation will be explained.

First, consider reading data from the memory cell 17. Φ13. Set Φ1□ and Φ7 to "H" and bit line 35.
36 are precharged to Vcc-Vth, and at the same time, read dummy cells C, , C, z.

C10, Cz+, Cz□, and C23 are set to the ground level, and the value of any one of the prechars is written, and the dummy cell Cl1l cz+ is 1/6 times the capacitor Cs of memory cell 17 + CIZI C22+ C1s+
Ctn is set to 1/3 times Cs. Word line W
In response to the fact that L z h was rare, the output of the charge transfer type preamplifier 54 becomes a charge transfer type preamplifier when the clock Φ1 is raised, assuming that its capacitance is Co. th)
charges pass through. Therefore, the output of the charge transfer preamplifier 55 changes compared to before starting up Φ1.

Therefore, the result of amplifying the charge transfer type preamplifier output by the differential amplifier 56 is the clock Φ3. Φ2. The table below shows the rise of Φ3.

However, when the memory cell 18 connected to the bit line 36 is selected, 0.1 in the table is inverted. Therefore, the differential amplifier 5
When memory cell 17 is selected to store the output of 6 in register 66.70°74, Φ13 is set to "L" and Φ1 is
4 is set to “H” and conversely, when memory cell 18 is selected, Φ
, 3 sets H', Φ14 to "H", and conversely, the memory cell 18
When is selected, Φ13 is set to "H" and Φ14 is set to "L".

Clock Φ, UΦ2 is a clock that becomes "H" when Φ or Φ2 becomes "H", and similarly, Φ3uΦ4 . Φ5UΦ
6 is also a similar clock. For these, the outputs of the differential amplifier 56 are Φl (Φ2) and Φ, (Φ4) and Φ5
(Φ,) is written to register 66.70.74. When selected by column decoder 79, 64.
Transistor 68.72 turns on and resistor 66.70
．． 74 data are l101, l102, l10
3, and this is output as 2-bit data by an encoder (not shown).

Next, considering the case of writing or rewriting, when writing the data in the registers 66, 70, 74 to the memory cell 17 again (when writing from the outside, the decoded data is I10+, I10□.

It is written to the register from l103. )Φ1. .

Set Φ1□ to "L" and separate each sub-bit line, and then W L 2. is set to "H" and the word line DWL2. of the write dummy cell of the unselected block is set to "H". Turn on DWL3 (at this time, the capacitance of dummy cells 77 and 78 is set to be the same as the capacitance Cs of the memory cell), and set the capacitance of each sub-bit line to (CB + C5). In this state Φ1
5. Set Φ9 to "H" and make the potentials of each sub-pit and T line correspond to registers 66, 70, and 74 (Vcc-
Vth) and 0■. Further, after turning Φ1 to "L" and turning off the transistor 19, Φ1. is turned on to mix the charges stored in the sub-bit lines.

This causes level shift 66. 'Value corresponding to the contents of L0,74 (Vcc -V th) (m is O~3
It is. ) In other words, rewriting is realized. Finally W
L z h , D W L z , D W L 3
Set to “L”.

When writing to 18 memory cells, set Φ to “L”
, 0 is set to "H" to perform the same operation.

〔Effect of the invention〕

As described above, according to the present invention, the comparison means sequentially compares the potential of the bit line from which the contents of the memory cell have been read out with each of the (n-1) reference potentials, and the comparison result of each is stored. (n-1) bit registers and bit lines into which charges are injected according to the contents of the registers when writing to memory cells are divided (n-1).
The structure includes two sub-bit lines and a switching means for connecting the sub-bit lines into one to realize a desired voltage level on the bit line, and is configured so that rewriting operations can be performed at once without using a staircase wave. Therefore, the rewrite time can be shortened, and the read operation cycle time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multilevel storage dynamic RAM device according to an embodiment of the present invention. Figures 3 and 4 are detailed diagrams of the memory array section, multilevel data reading underground section, data store centering on the data register, and input/output control section, respectively, and Figures 5 to 9 are conventional multilevel storage devices. FIG. 2 is a diagram for explaining a dynamic RAM device. 17.1B, 23.24, 29.30 are memory cells, 3
5.36 is a bit line, 37 to 39 are register data transfer lines, 54.55 is a charge transfer preamplifier, 56 is a differential amplifier, and 60, 70.74 are registers.

Claims (3)

[Claims] (1) In a multilevel storage dynamic RAM device that stores n levels (n≧3) in a memory cell composed of one transistor and one capacitor, the potential of the bit line from which the contents of the memory cell are read is set to (n-1 ) reference potentials, an (n-1) bit register for storing the comparison results, and charge injection into each of the registers according to the contents of the registers when writing to the memory cell. (n-1) sub-bit lines formed by dividing the bit line to be processed; and switching means for connecting the sub-bit lines into one to realize a desired voltage level on the bit line. A multi-value storage dynamic RAM device with special features. (2) The comparison means is configured to calculate (n-1) threshold values of the n value, which are connected to the bit line and only those connected to the bit lines of non-selected blocks are sequentially activated during reading. 2. The multilevel storage dynamic RAM device according to claim 1, further comprising 2(n-1) read dummy cells. (3) A patent claim characterized by comprising a writing dummy cell having the same configuration as a memory cell, which is provided connected to each sub-bit line and only those connected to the sub-bit line of a non-selected block are activated during writing. range 1
3. The multilevel storage dynamic RAM device according to item 1 or 2.