JPS63195896A - Dynamic ram device for multivalued storage - Google Patents

Abstract

PURPOSE:To shorten a rewriting time and the cycle time of reading operation by mixing potential levels charged in capacitor elements corresponding to the number of registers to write writing data in a selected memory cell at the time rewriting of data. CONSTITUTION:When a memory cell connected to a bit line 1a is selected, a clock phi9 is turned to 'H', and when a memory cell connected to a bit line 1b is selected, a clock phi8 is turned to 'H' and clock phi12 is also turned to 'H'. Consequently, the bit line 1a or 1b is charged with the capacitor element CB1 of a register 38 and the capacitor element CB2 of a register 36 are charged with the value of a register 37. Since the elements CB1, CB2 are set up to a value equal to the sum of the capacity of the bit line and that of the memory cell, the two capacitor elements are connected to the bit lines in parallel at a cock phi13, the potential of the bit line and the memory cells are set up to 1/3 potential written in the registers 36-38, so that rewriting operation is ended.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a multi-value storage memory circuit.

[Conventional technology]

Figure 4 shows, for example, l5SCC85 lecture number FAM17.5
This is a basic configuration diagram of a multilevel storage memory circuit using the same memory cells as the dynamic RAM shown in FIG.
is a memory cell, 4 is a dummy cell, 5 is a write gate, 6
is a charge transfer preamplifier, 7 is a sense amplifier, 8 is a step wave voltage generation circuit, 9 is a control register, 10 is a column register, 11 is a column I10 line, 1
2 is an encoder circuit, 13 is a column decoder, 14 is a data-in decoder, 15 is a word line, and 16 is a dummy word line.

Next, the operation will be explained. The memory array made up of memory cells 3 is exactly the same as a general dynamic RAM,
A differential sensing method using dummy cells 4 is used. The difference from a normal DRAM is that a staircase voltage Φ8 generated by a staircase wave generation circuit 8 is applied to the word line 15 and dummy word line 16, and information on control pulses synchronized with Φ8 (corresponding to the voltage value of Φ8) is applied to the word line 15 and dummy word line 16. Each data line is provided with a control register 9 for controlling the generated information, a column register 10 for storing the information, and an encoder 12. The charge transfer preamplifier 6 is a charge transfer type preamplifier using a bias charge injection method so that the signal voltage becomes 1/(M-1) (M is the number of levels) when performing multi-value storage. This allows the connection from the node with large capacity (data line D) to the node with small capacity (data line D).
The voltage is increased by transferring charge to the input terminal of the sense amplifier 7. The charge transfer preamplifier 6 and the sense amplifier 7 determine whether or not a charge has flowed from the memory cell to the data line every time the staircase wave Φ8 rises by one step, and input the result into the column register 10. For rewriting, the timing at which the write gate 5 opens is controlled by the information in the column register 10.

Figure 5 shows readout in the case of 2 bits/cell (n = 2) and the voltage waveform of the data line at that time.
The figure shows a potential diagram of the memory cell at each time (al to (dl) corresponding to FIG. 5.

When reading information, an ascending staircase wave is applied.

Considering the case where (0, 1), that is, the second lowest voltage is stored as memory information, charge flows out from the memory cell 3 to the data line for the first time at time C.
Data line potential VD decreases.

Sense amplifier 7 detects this change, and column register 1
0 and temporarily stores digital information (0, 1).

Figure 7 shows writing in the same case < (0, 1) and the voltage waveform of the data line at that time, and Figure 8 shows each time period (e) to (h) corresponding to Figure 7. ) shows a potential diagram of a memory cell.

At the time of writing, a descending staircase wave is applied, and the information in the control register 9 and the contents in the column register 10 are compared, and when they match, the write gate 5 is turned on, and the charge in the memory cell portion is drawn out to the data line side. These enable accumulation of each voltage ((each step voltage value of the staircase wave) - (threshold voltage of the memory cell)).

[Problem that the invention seeks to solve]

A conventional multilevel storage dynamic RAM device is configured as follows, and since the reading is destructive, rewriting is required. In the case of n-embedded Bell memory, this rewrite is 0.
This invention requires the operation of reading the register twice and writing each level of the n-value staircase wave to the cell according to the contents of the register, and the cycle time of the read operation is long. The purpose of this invention is to provide a multilevel storage dynamic RAM device that can shorten the read operation cycle time by shortening the rewrite time.

[Failure to solve the problem]

Multilevel storage dynamic RA according to the first invention of the present invention
The M device includes comparing means for sequentially comparing the potential of the bit line from which the contents of the memory cell have been read out with each of (n-1) reference potentials, and (n-1) bits of comparing means for storing the results of each comparison. A register with a capacitance (n
-2) capacitive elements and the parasitic capacitance of the bit line to which the read memory cell is connected, totaling (n-1) capacitive elements, and the above (n-1) capacitive elements to 1 and switching means for connecting the bit line to the bit line to achieve a desired voltage level on the bit line.

Further, the multilevel storage dynamic RAM device according to the second aspect of the present invention includes comparing means for sequentially comparing the potential of the bit line from which the contents of the memory cell have been read out with each of three reference potentials, and comparing results of each of the comparisons. The system uses two bit lines: a 3-bit register that stores the data, and a shared sense amplifier configuration in which charge is injected into each register according to the contents of the register when writing to the memory cell. A total of three capacitive elements, including a capacitive element and a parasitic capacitance of the bit line to which the read memory cell is connected, are connected to one capacitor, and the desired voltage level is applied to the bit line. It is equipped with a switching means for realizing on-line.

[Effect]

The first aspect of this invention. The multi-value storage dynamic RAM device according to the second invention has the above-described configuration, and when rewriting data, the written data is generated at once by mixing the potentials charged in the number of capacitors corresponding to the registers. Since the data is then written into the selected memory cell, the time required for rewriting can be shortened, and the cycle time of the read operation can be shortened.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
2 and 2 are circuit diagrams showing a multilevel storage dynamic RAM device according to an embodiment of the present invention.
la and lb are bit lines, 2 to 31 are transfer gates, 32 is a charge transfer type preamplifier, 33 is a current mirror type differential amplifier, 34.35 is an inverter, 36 to 38 are registers, cd, , Cd+□, Cd2 ．． , Cd2□,
Cdzl and Cd3□ are dummy cells, C□ and CIl□ are capacitors, and 39 to 42 are signal lines.

WZI%l Wtn+t is a word line, Φ1 to Φ11. Φ
1UΦ2. Φ, UΦ4. Φ5UΦ6. Φ2 is a clock signal, I10. , I10□, l10t is I10
The line Cs is a memory cell capacity, and 43 is a memory cell block.

Next, the operation will be explained.

When reading a memory cell connected to bit line 1a, first, clock signal Φ7. With Φ2 set to "I" level, bit lines 1a and lb are set to ■. , -V7H, dummy cell Cd, 1. Cd tz, Cd 21.
Precharge Cd2□, Cd, , Cd3□ to 0.

One of the following four values is written in the memory cell capacity Cs, and the capacity of the dummy cell is Cd++, Cd12 is 1/6 times Cs,
Cd2. , Cd, □, Cd3. ．． Cd3□ is 1/ of Cs
It is set to 3 times.

When the word line is raised, the charge transfer preamplifier 32 on the bit line 1a side is set to ('V((V714)
+ Cs (Vcc Vto) +-Cs (
VccVTH), since a charge of 0 passes through, the output of the charge transfer type preamplifier is: If the output capacitance of the charge transfer type preamplifier is 00, the output of the charge transfer type preamplifier is:
Each decreases in height. On the other hand, when the clock Φ is started, the charge transfer preamplifier on the bit line 1b side is activated (Vc-VT
The charge of H) passes through and then R. Therefore, the output of the charge transfer preamplifier changes compared to before starting the clock Φ1.

Therefore, the outputs of the two charge transfer preamplifiers are connected to the operational amplifier 3.
The result of amplification by clock Φ1. The table shows the results according to Φ2 and Φ3.

However, if a memory cell connected to bit line 1b is selected, 1.0 in the table is reversed. Therefore, when storing the differential amplifier output in registers 36, 37, and 38,
When selecting a memory cell connected to bit line 1a,
When Φ1□ is set to “L” and Φ1□ is set to “H” and the memory cell connected to bit line 1b is selected, Φ11 is set to “H”.
”, Φ1□ is “L”.

Clock Φ1UΦ2 is Φ1 or Φ2, clock Φ3
0Φ4 is Φ, or Φ4 is clock Φ.

The same Φ6 is a clock that becomes "H" when Φ5 or Φ5 becomes "H", and the output of the differential amplifier is Φ1° (Φ2
), Φ3 (Φ4), and Φ5 (Φ6), and are written to registers 36, 37, and 38.

Next, bit &? When the memory cell connected to bit line 11a is selected, Φ is set to H', and when the memory cell connected to bit line 1b is selected, Φ8 is set to H', and at the same time, Φ1□ is set to "H".
shall be. In this way, the bit line la (or lb) becomes
The capacitor C1 of the resistor 38 is the same as the capacitor C1 of the resistor 36.
Capacitor Cl1z is charged to the value of register 37.

Capacitor C8,.

Since C8□ is set equal to the sum of the bit line capacitance and the memory cell capacitance, the clock Φ1. When the two capacitors and the bit line are connected in parallel, the potentials of the bit line and the memory mole become the following potential depending on the number of 1's written in the registers 36 to 38, and the rewriting operation ends.

When retrieving externally read data, the transfer gate 23 is activated by the column selection signal 42 from the column decoder.
, 27.31 are in a conductive state, and the I10 line (I10+
, l102, l103) by reading the contents of the registers.

When writing data from outside, transfer gates 23, 27 .
31 is in a conductive state and the I10 line (I10+, l10z
, l103), and the subsequent operation is similar to the rewrite operation described above.

In the above embodiment of the first aspect of the present invention, two capacitors and a bit line capacitance were used to generate the rewrite level, but a multilevel storage dynamic RAM device that stores four levels can be used. If so, according to the second aspect of the present invention, a shared sense amplifier configuration as shown in FIG. 3 may be used, and the bit line of the unselected block may be used in place of the two capacitors.

Next, the operation of the multilevel storage dynamic RAM device according to the second embodiment of the present invention shown in FIG. 3 will be described. In the circuit shown in FIG. 3, the sense amplifier is shared by two memory cell blocks (A block and B block), which are equivalent to the block 43 consisting of memory cells and dummy cells shown in FIG. A case will be described in which a memory cell connected to bit line 1a of block A is read.

First, set Φ2゜ and Φ2I to "L" to disconnect the B block, set Φ32.ΦI6 to "H" and connect the A block to the sense amplifier.After this, similarly to the first invention of the present invention, the bit line 1a The other bit line 1b to which a dummy cell is connected with the level synchronized with the clock Φ1.Φ2.Φ.
level and compare the results to registers 36, 37, and 38.
Store it in. Next, Φ11 and Φ3. When Φ24 is set to "H", the Soto wire la' and the capacitor 59 are connected to the resistor 36.
The bit line 1b' and the capacitor 61 charge the bit line 1a of the register 37 and the memory cell connected to the bit line 1a to the stored contents of the register 38. Capacitor 45, 4
6,59.61 has the same capacity as the memory cell. After this, set Φ16 to "L" and Φ17 to "H".

With Φ2゜ as "H" and Φ2I as "H", bit line 1a,
A rewrite level is generated by connecting la' and lb' in parallel. In the manner described above, it is possible to rewrite the memory cells connected to the bit line 1a.

To read and write data to/from the outside, connect the I10 line (Ilo, , I1) to the register in the row selected by the column decoder.
This is carried out by reading and writing through 0□, 1103) as in the case of the multilevel storage dynamic RAM device according to the first embodiment of the invention described above.

〔Effect of the invention〕

As described above, according to the first aspect of the present invention, in a multilevel storage dynamic RAM device, the potential of the bit line from which the contents of the memory cell are read is sequentially compared with each of (n -1) reference potentials. means, an (n-1) bit register for storing the respective comparison results, and the sum of the bit line capacitance and the memory cell capacitance into which charge is injected into each according to the contents of the register when writing to the memory cell. A total of (n-1) capacitors, including (n-2) capacitors with a capacitance equal to , and the parasitic capacitance of the bit line to which the read memory cell is connected, and a switching means for realizing a desired voltage level on the bit line by connecting two capacitive elements into one, and according to a second aspect of the present invention, four levels are stored. Comparing means for sequentially comparing the potential of a bit line from which the contents of a memory cell have been read out in a multi-level storage dynamic RAM device with each of three reference potentials, a 13-bit register for storing the results of each comparison, and a memory. When writing to a cell, charge is injected into each of the registers according to the contents of the register.The shared sense amplifier is configured with two capacitive elements using two bit lines in the unselected block of bit lines, and a A total of three capacitive elements including the parasitic capacitance of one bit line to which the memory cell is connected, and the above three
and a switching means for realizing a desired voltage level on the bit line by connecting several capacitive elements into one, and is configured so that the rewriting operation can be performed at once without using a step method. This has the effect of shortening rewriting time and shortening read operation cycle time.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing a multilevel storage dynamic RAM device according to an embodiment of the first aspect of the present invention, and FIG.
Figures 4 to 8 are block diagrams showing a multilevel storage dynamic RAM device according to an embodiment of the second invention of the present invention.
The figure is a diagram for explaining a conventional multilevel storage dynamic RAM device. Cdz, Cd+z, Cdz+, Cdz□, C(JH3C
d3□ is a dummy cell, 32 is a charge transfer preamplifier, 3
3 is a current mirror type differential amplifier, 36, 37.38
is a resistor, CBI, CB□ is a capacitor, la,
la, lb, and lb' are bit lines. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (4)

[Claims] (1) In a multilevel storage dynamic RAM device that stores n levels (n≧3) in a memory cell composed of a one-transistor capacitor, the potential of the bit line from which the contents of the memory cell are read is set to (n-1). ) reference potentials, an (n-1) bit register for storing each of the comparison results, and a charge injected into each of the registers according to the contents of the registers when writing to the memory cell. The sum of (n-2) capacitive elements with a capacitance equal to the sum of the bit line capacitance to be read and the memory cell capacitance, and the parasitic capacitance of the bit line to which the read memory cell is connected (n-1) a multi-level memory dynamic device comprising: a capacitive element; and a switching means for connecting the (n-1) capacitive elements into one to realize a desired voltage level on the bit line. RAM device. (2) The comparison means is configured to calculate (n-1) threshold values of the n value, which are connected to the bit line and only those connected to the non-selected bit line are sequentially activated during reading. 2. The multilevel storage dynamic RAM device according to claim 1, further comprising 2(n-1) read dummy cells. (3) Multi-level dynamic RA that stores four levels in a memory cell composed of one transistor and one capacitor
In the M device, a comparison means for sequentially comparing the potential of the bit line from which the contents of the memory cell have been read out with each of three reference potentials, a 3-bit register for storing the results of each comparison, and writing to the memory cell. The read memory cell is connected to two capacitive elements using the two bit lines of the non-selected block of bit lines, which have a shared sense amplifier configuration in which charge is injected into each according to the contents of the above register. a total of three capacitive elements including the parasitic capacitance of the bit line, and switching means for connecting the three capacitive elements into one to realize a desired voltage level on the bit line. Characteristic multivalued dynamic R
AM device. (4) The comparison means is provided with six units connected to the bit line, and determines the three threshold values of the four values, in which only those connected to the non-selected bit line are sequentially activated during reading. 4. A multilevel storage dynamic RAM device according to claim 3, characterized in that the multi-value storage dynamic RAM device is equipped with a read dummy cell.